r600g: Move fetch shader register setup to r600_state.c / evergreen_state.c.
[mesa.git] / src / gallium / drivers / nv50 / nv50_screen.h
1 #ifndef __NV50_SCREEN_H__
2 #define __NV50_SCREEN_H__
3
4 #define NOUVEAU_NVC0
5 #include "nouveau/nouveau_screen.h"
6 #include "nouveau/nouveau_fence.h"
7 #include "nouveau/nouveau_mm.h"
8 #undef NOUVEAU_NVC0
9 #include "nv50_winsys.h"
10 #include "nv50_stateobj.h"
11
12 #define NV50_TIC_MAX_ENTRIES 2048
13 #define NV50_TSC_MAX_ENTRIES 2048
14
15 struct nv50_context;
16
17 #define NV50_CODE_BO_SIZE_LOG2 19
18
19 #define NV50_SCRATCH_SIZE (2 << 20)
20 #define NV50_SCRATCH_NR_BUFFERS 2
21
22 struct nv50_screen {
23 struct nouveau_screen base;
24 struct nouveau_winsys *nvws;
25
26 struct nv50_context *cur_ctx;
27
28 struct nouveau_bo *code;
29 struct nouveau_bo *uniforms;
30 struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
31 struct nouveau_bo *stack_bo;
32 struct nouveau_bo *tls_bo;
33
34 uint64_t tls_size;
35
36 struct nouveau_resource *vp_code_heap;
37 struct nouveau_resource *gp_code_heap;
38 struct nouveau_resource *fp_code_heap;
39
40 struct {
41 void **entries;
42 int next;
43 uint32_t lock[NV50_TIC_MAX_ENTRIES / 32];
44 } tic;
45
46 struct {
47 void **entries;
48 int next;
49 uint32_t lock[NV50_TSC_MAX_ENTRIES / 32];
50 } tsc;
51
52 struct {
53 uint32_t *map;
54 struct nouveau_bo *bo;
55 } fence;
56
57 struct nouveau_notifier *sync;
58
59 struct nouveau_mman *mm_VRAM_fe0;
60
61 struct nouveau_grobj *tesla;
62 struct nouveau_grobj *eng2d;
63 struct nouveau_grobj *m2mf;
64 };
65
66 static INLINE struct nv50_screen *
67 nv50_screen(struct pipe_screen *screen)
68 {
69 return (struct nv50_screen *)screen;
70 }
71
72 void nv50_screen_make_buffers_resident(struct nv50_screen *);
73
74 int nv50_screen_tic_alloc(struct nv50_screen *, void *);
75 int nv50_screen_tsc_alloc(struct nv50_screen *, void *);
76
77 static INLINE void
78 nv50_resource_fence(struct nv04_resource *res, uint32_t flags)
79 {
80 struct nv50_screen *screen = nv50_screen(res->base.screen);
81
82 if (res->mm) {
83 nouveau_fence_ref(screen->base.fence.current, &res->fence);
84
85 if (flags & NOUVEAU_BO_WR)
86 nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);
87 }
88 }
89
90 static INLINE void
91 nv50_resource_validate(struct nv04_resource *res, uint32_t flags)
92 {
93 struct nv50_screen *screen = nv50_screen(res->base.screen);
94
95 if (likely(res->bo)) {
96 nouveau_bo_validate(screen->base.channel, res->bo, flags);
97
98 if (flags & NOUVEAU_BO_WR)
99 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
100 if (flags & NOUVEAU_BO_RD)
101 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
102
103 nv50_resource_fence(res, flags);
104 }
105 }
106
107 struct nv50_format {
108 uint32_t rt;
109 uint32_t tic;
110 uint32_t vtx;
111 uint32_t usage;
112 };
113
114 extern const struct nv50_format nv50_format_table[];
115
116 static INLINE void
117 nv50_screen_tic_unlock(struct nv50_screen *screen, struct nv50_tic_entry *tic)
118 {
119 if (tic->id >= 0)
120 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
121 }
122
123 static INLINE void
124 nv50_screen_tsc_unlock(struct nv50_screen *screen, struct nv50_tsc_entry *tsc)
125 {
126 if (tsc->id >= 0)
127 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
128 }
129
130 static INLINE void
131 nv50_screen_tic_free(struct nv50_screen *screen, struct nv50_tic_entry *tic)
132 {
133 if (tic->id >= 0) {
134 screen->tic.entries[tic->id] = NULL;
135 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
136 }
137 }
138
139 static INLINE void
140 nv50_screen_tsc_free(struct nv50_screen *screen, struct nv50_tsc_entry *tsc)
141 {
142 if (tsc->id >= 0) {
143 screen->tsc.entries[tsc->id] = NULL;
144 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
145 }
146 }
147
148 #endif