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117d3d1894b69d2cb58816510fc05f17edd61157
[mesa.git] / src / gallium / drivers / nv50 / nv50_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "tgsi/tgsi_ureg.h"
33
34 #include "os/os_thread.h"
35
36 #include "nv50_context.h"
37 #include "nv50_resource.h"
38 #include "nv50_blit.h"
39
40 #include "nv50_defs.xml.h"
41 #include "nv50_texture.xml.h"
42
43 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
44
45 /* return TRUE for formats that can be converted among each other by NV50_2D */
46 static INLINE boolean
47 nv50_2d_format_faithful(enum pipe_format format)
48 {
49 uint8_t id = nv50_format_table[format].rt;
50
51 return (id >= 0xc0) &&
52 (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0)));
53 }
54
55 static INLINE uint8_t
56 nv50_2d_format(enum pipe_format format)
57 {
58 uint8_t id = nv50_format_table[format].rt;
59
60 /* Hardware values for color formats range from 0xc0 to 0xff,
61 * but the 2D engine doesn't support all of them.
62 */
63 if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
64 return id;
65
66 switch (util_format_get_blocksize(format)) {
67 case 1:
68 return NV50_SURFACE_FORMAT_R8_UNORM;
69 case 2:
70 return NV50_SURFACE_FORMAT_R16_UNORM;
71 case 4:
72 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
73 default:
74 return 0;
75 }
76 }
77
78 static int
79 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
80 struct nv50_miptree *mt, unsigned level, unsigned layer,
81 enum pipe_format pformat)
82 {
83 struct nouveau_bo *bo = mt->base.bo;
84 uint32_t width, height, depth;
85 uint32_t format;
86 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
87 uint32_t offset = mt->level[level].offset;
88
89 format = nv50_2d_format(pformat);
90 if (!format) {
91 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
92 util_format_name(pformat));
93 return 1;
94 }
95
96 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
97 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
98 depth = u_minify(mt->base.base.depth0, level);
99
100 offset = mt->level[level].offset;
101 if (!mt->layout_3d) {
102 offset += mt->layer_stride * layer;
103 depth = 1;
104 layer = 0;
105 } else
106 if (!dst) {
107 offset += nv50_mt_zslice_offset(mt, level, layer);
108 layer = 0;
109 }
110
111 if (!nouveau_bo_memtype(bo)) {
112 BEGIN_NV04(push, SUBC_2D(mthd), 2);
113 PUSH_DATA (push, format);
114 PUSH_DATA (push, 1);
115 BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
116 PUSH_DATA (push, mt->level[level].pitch);
117 PUSH_DATA (push, width);
118 PUSH_DATA (push, height);
119 PUSH_DATAh(push, bo->offset + offset);
120 PUSH_DATA (push, bo->offset + offset);
121 } else {
122 BEGIN_NV04(push, SUBC_2D(mthd), 5);
123 PUSH_DATA (push, format);
124 PUSH_DATA (push, 0);
125 PUSH_DATA (push, mt->level[level].tile_mode);
126 PUSH_DATA (push, depth);
127 PUSH_DATA (push, layer);
128 BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
129 PUSH_DATA (push, width);
130 PUSH_DATA (push, height);
131 PUSH_DATAh(push, bo->offset + offset);
132 PUSH_DATA (push, bo->offset + offset);
133 }
134
135 #if 0
136 if (dst) {
137 BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
138 PUSH_DATA (push, 0);
139 PUSH_DATA (push, 0);
140 PUSH_DATA (push, width);
141 PUSH_DATA (push, height);
142 }
143 #endif
144 return 0;
145 }
146
147 static int
148 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
149 struct nv50_miptree *dst, unsigned dst_level,
150 unsigned dx, unsigned dy, unsigned dz,
151 struct nv50_miptree *src, unsigned src_level,
152 unsigned sx, unsigned sy, unsigned sz,
153 unsigned w, unsigned h)
154 {
155 const enum pipe_format dfmt = dst->base.base.format;
156 const enum pipe_format sfmt = src->base.base.format;
157 int ret;
158
159 if (!PUSH_SPACE(push, 2 * 16 + 32))
160 return PIPE_ERROR;
161
162 ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt);
163 if (ret)
164 return ret;
165
166 ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt);
167 if (ret)
168 return ret;
169
170 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
171 PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
172 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
173 PUSH_DATA (push, dx << dst->ms_x);
174 PUSH_DATA (push, dy << dst->ms_y);
175 PUSH_DATA (push, w << dst->ms_x);
176 PUSH_DATA (push, h << dst->ms_y);
177 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
178 PUSH_DATA (push, 0);
179 PUSH_DATA (push, 1);
180 PUSH_DATA (push, 0);
181 PUSH_DATA (push, 1);
182 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
183 PUSH_DATA (push, 0);
184 PUSH_DATA (push, sx << src->ms_x);
185 PUSH_DATA (push, 0);
186 PUSH_DATA (push, sy << src->ms_y);
187
188 return 0;
189 }
190
191 static void
192 nv50_resource_copy_region(struct pipe_context *pipe,
193 struct pipe_resource *dst, unsigned dst_level,
194 unsigned dstx, unsigned dsty, unsigned dstz,
195 struct pipe_resource *src, unsigned src_level,
196 const struct pipe_box *src_box)
197 {
198 struct nv50_context *nv50 = nv50_context(pipe);
199 int ret;
200 boolean m2mf;
201 unsigned dst_layer = dstz, src_layer = src_box->z;
202
203 /* Fallback for buffers. */
204 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
205 util_resource_copy_region(pipe, dst, dst_level, dstx, dsty, dstz,
206 src, src_level, src_box);
207 return;
208 }
209
210 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
211 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
212
213 m2mf = (src->format == dst->format) ||
214 (util_format_get_blocksizebits(src->format) ==
215 util_format_get_blocksizebits(dst->format));
216
217 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
218
219 if (m2mf) {
220 struct nv50_m2mf_rect drect, srect;
221 unsigned i;
222 unsigned nx = util_format_get_nblocksx(src->format, src_box->width);
223 unsigned ny = util_format_get_nblocksy(src->format, src_box->height);
224
225 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
226 nv50_m2mf_rect_setup(&srect, src, src_level,
227 src_box->x, src_box->y, src_box->z);
228
229 for (i = 0; i < src_box->depth; ++i) {
230 nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
231
232 if (nv50_miptree(dst)->layout_3d)
233 drect.z++;
234 else
235 drect.base += nv50_miptree(dst)->layer_stride;
236
237 if (nv50_miptree(src)->layout_3d)
238 srect.z++;
239 else
240 srect.base += nv50_miptree(src)->layer_stride;
241 }
242 return;
243 }
244
245 assert((src->format == dst->format) ||
246 (nv50_2d_format_faithful(src->format) &&
247 nv50_2d_format_faithful(dst->format)));
248
249 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
250 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
251 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
252 nouveau_pushbuf_validate(nv50->base.pushbuf);
253
254 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
255 ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
256 nv50_miptree(dst), dst_level,
257 dstx, dsty, dst_layer,
258 nv50_miptree(src), src_level,
259 src_box->x, src_box->y, src_layer,
260 src_box->width, src_box->height);
261 if (ret)
262 break;
263 }
264 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
265 }
266
267 static void
268 nv50_clear_render_target(struct pipe_context *pipe,
269 struct pipe_surface *dst,
270 const union pipe_color_union *color,
271 unsigned dstx, unsigned dsty,
272 unsigned width, unsigned height)
273 {
274 struct nv50_context *nv50 = nv50_context(pipe);
275 struct nouveau_pushbuf *push = nv50->base.pushbuf;
276 struct nv50_miptree *mt = nv50_miptree(dst->texture);
277 struct nv50_surface *sf = nv50_surface(dst);
278 struct nouveau_bo *bo = mt->base.bo;
279 unsigned z;
280
281 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
282 PUSH_DATAf(push, color->f[0]);
283 PUSH_DATAf(push, color->f[1]);
284 PUSH_DATAf(push, color->f[2]);
285 PUSH_DATAf(push, color->f[3]);
286
287 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
288 return;
289
290 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
291
292 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
293 PUSH_DATA (push, 1);
294 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
295 PUSH_DATAh(push, bo->offset + sf->offset);
296 PUSH_DATA (push, bo->offset + sf->offset);
297 PUSH_DATA (push, nv50_format_table[dst->format].rt);
298 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
299 PUSH_DATA (push, 0);
300 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
301 if (nouveau_bo_memtype(bo))
302 PUSH_DATA(push, sf->width);
303 else
304 PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
305 PUSH_DATA (push, sf->height);
306 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
307 PUSH_DATA (push, 1);
308
309 if (!nouveau_bo_memtype(bo)) {
310 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
311 PUSH_DATA (push, 0);
312 }
313
314 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
315
316 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
317 PUSH_DATA (push, (width << 16) | dstx);
318 PUSH_DATA (push, (height << 16) | dsty);
319
320 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
321 for (z = 0; z < sf->depth; ++z) {
322 PUSH_DATA (push, 0x3c |
323 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
324 }
325
326 nv50->dirty |= NV50_NEW_FRAMEBUFFER;
327 }
328
329 static void
330 nv50_clear_depth_stencil(struct pipe_context *pipe,
331 struct pipe_surface *dst,
332 unsigned clear_flags,
333 double depth,
334 unsigned stencil,
335 unsigned dstx, unsigned dsty,
336 unsigned width, unsigned height)
337 {
338 struct nv50_context *nv50 = nv50_context(pipe);
339 struct nouveau_pushbuf *push = nv50->base.pushbuf;
340 struct nv50_miptree *mt = nv50_miptree(dst->texture);
341 struct nv50_surface *sf = nv50_surface(dst);
342 struct nouveau_bo *bo = mt->base.bo;
343 uint32_t mode = 0;
344 unsigned z;
345
346 assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
347
348 if (clear_flags & PIPE_CLEAR_DEPTH) {
349 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
350 PUSH_DATAf(push, depth);
351 mode |= NV50_3D_CLEAR_BUFFERS_Z;
352 }
353
354 if (clear_flags & PIPE_CLEAR_STENCIL) {
355 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
356 PUSH_DATA (push, stencil & 0xff);
357 mode |= NV50_3D_CLEAR_BUFFERS_S;
358 }
359
360 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
361 return;
362
363 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
364
365 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
366 PUSH_DATAh(push, bo->offset + sf->offset);
367 PUSH_DATA (push, bo->offset + sf->offset);
368 PUSH_DATA (push, nv50_format_table[dst->format].rt);
369 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
370 PUSH_DATA (push, 0);
371 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
372 PUSH_DATA (push, 1);
373 BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
374 PUSH_DATA (push, sf->width);
375 PUSH_DATA (push, sf->height);
376 PUSH_DATA (push, (1 << 16) | 1);
377
378 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
379 PUSH_DATA (push, (width << 16) | dstx);
380 PUSH_DATA (push, (height << 16) | dsty);
381
382 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
383 for (z = 0; z < sf->depth; ++z) {
384 PUSH_DATA (push, mode |
385 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
386 }
387
388 nv50->dirty |= NV50_NEW_FRAMEBUFFER;
389 }
390
391 void
392 nv50_clear(struct pipe_context *pipe, unsigned buffers,
393 const union pipe_color_union *color,
394 double depth, unsigned stencil)
395 {
396 struct nv50_context *nv50 = nv50_context(pipe);
397 struct nouveau_pushbuf *push = nv50->base.pushbuf;
398 struct pipe_framebuffer_state *fb = &nv50->framebuffer;
399 unsigned i;
400 uint32_t mode = 0;
401
402 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
403 if (!nv50_state_validate(nv50, NV50_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
404 return;
405
406 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
407 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
408 PUSH_DATAf(push, color->f[0]);
409 PUSH_DATAf(push, color->f[1]);
410 PUSH_DATAf(push, color->f[2]);
411 PUSH_DATAf(push, color->f[3]);
412 mode =
413 NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
414 NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
415 }
416
417 if (buffers & PIPE_CLEAR_DEPTH) {
418 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
419 PUSH_DATA (push, fui(depth));
420 mode |= NV50_3D_CLEAR_BUFFERS_Z;
421 }
422
423 if (buffers & PIPE_CLEAR_STENCIL) {
424 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
425 PUSH_DATA (push, stencil & 0xff);
426 mode |= NV50_3D_CLEAR_BUFFERS_S;
427 }
428
429 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
430 PUSH_DATA (push, mode);
431
432 for (i = 1; i < fb->nr_cbufs; i++) {
433 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
434 PUSH_DATA (push, (i << 6) | 0x3c);
435 }
436 }
437
438
439 /* =============================== BLIT CODE ===================================
440 */
441
442 struct nv50_blitter
443 {
444 struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
445 struct nv50_program vp;
446
447 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
448
449 pipe_mutex mutex;
450 };
451
452 struct nv50_blitctx
453 {
454 struct nv50_context *nv50;
455 struct nv50_program *fp;
456 uint8_t mode;
457 uint16_t color_mask;
458 uint8_t filter;
459 enum pipe_texture_target target;
460 struct {
461 struct pipe_framebuffer_state fb;
462 struct nv50_program *vp;
463 struct nv50_program *gp;
464 struct nv50_program *fp;
465 unsigned num_textures[3];
466 unsigned num_samplers[3];
467 struct pipe_sampler_view *texture[2];
468 struct nv50_tsc_entry *sampler[2];
469 uint32_t dirty;
470 } saved;
471 };
472
473 static void
474 nv50_blitter_make_vp(struct nv50_blitter *blit)
475 {
476 static const uint32_t code[] =
477 {
478 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
479 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
480 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
481 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
482 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
483 };
484
485 blit->vp.type = PIPE_SHADER_VERTEX;
486 blit->vp.translated = TRUE;
487 blit->vp.code = (uint32_t *)code; /* const_cast */
488 blit->vp.code_size = sizeof(code);
489 blit->vp.max_gpr = 4;
490 blit->vp.max_out = 5;
491 blit->vp.out_nr = 2;
492 blit->vp.out[0].mask = 0x3;
493 blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
494 blit->vp.out[1].hw = 2;
495 blit->vp.out[1].mask = 0x7;
496 blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
497 blit->vp.out[1].si = 0;
498 blit->vp.vp.attrs[0] = 0x73;
499 blit->vp.vp.psiz = 0x40;
500 blit->vp.vp.edgeflag = 0x40;
501 }
502
503 void *
504 nv50_blitter_make_fp(struct pipe_context *pipe,
505 unsigned mode,
506 enum pipe_texture_target ptarg)
507 {
508 struct ureg_program *ureg;
509 struct ureg_src tc;
510 struct ureg_dst out;
511 struct ureg_dst data;
512
513 const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg);
514
515 boolean tex_rgbaz = FALSE;
516 boolean tex_s = FALSE;
517 boolean cvt_un8 = FALSE;
518
519 if (mode != NV50_BLIT_MODE_PASS &&
520 mode != NV50_BLIT_MODE_Z24X8 &&
521 mode != NV50_BLIT_MODE_X8Z24)
522 tex_s = TRUE;
523
524 if (mode != NV50_BLIT_MODE_X24S8 &&
525 mode != NV50_BLIT_MODE_S8X24 &&
526 mode != NV50_BLIT_MODE_XS)
527 tex_rgbaz = TRUE;
528
529 if (mode != NV50_BLIT_MODE_PASS &&
530 mode != NV50_BLIT_MODE_ZS &&
531 mode != NV50_BLIT_MODE_XS)
532 cvt_un8 = TRUE;
533
534 ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
535 if (!ureg)
536 return NULL;
537
538 out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
539 tc = ureg_DECL_fs_input(
540 ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
541
542 data = ureg_DECL_temporary(ureg);
543
544 if (tex_s) {
545 ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
546 target, tc, ureg_DECL_sampler(ureg, 1));
547 ureg_MOV(ureg, ureg_writemask(data, TGSI_WRITEMASK_Y),
548 ureg_scalar(ureg_src(data), TGSI_SWIZZLE_X));
549 }
550 if (tex_rgbaz) {
551 const unsigned mask = (mode == NV50_BLIT_MODE_PASS) ?
552 TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
553 ureg_TEX(ureg, ureg_writemask(data, mask),
554 target, tc, ureg_DECL_sampler(ureg, 0));
555 }
556
557 if (cvt_un8) {
558 struct ureg_src mask;
559 struct ureg_src scale;
560 struct ureg_dst outz;
561 struct ureg_dst outs;
562 struct ureg_dst zdst3 = ureg_writemask(data, TGSI_WRITEMASK_XYZ);
563 struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
564 struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y);
565 struct ureg_src zsrc3 = ureg_src(data);
566 struct ureg_src zsrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_X);
567 struct ureg_src ssrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_Y);
568 struct ureg_src zshuf;
569
570 mask = ureg_imm3u(ureg, 0x0000ff, 0x00ff00, 0xff0000);
571 scale = ureg_imm4f(ureg,
572 1.0f / 0x0000ff, 1.0f / 0x00ff00, 1.0f / 0xff0000,
573 (1 << 24) - 1);
574
575 if (mode == NV50_BLIT_MODE_Z24S8 ||
576 mode == NV50_BLIT_MODE_X24S8 ||
577 mode == NV50_BLIT_MODE_Z24X8) {
578 outz = ureg_writemask(out, TGSI_WRITEMASK_XYZ);
579 outs = ureg_writemask(out, TGSI_WRITEMASK_W);
580 zshuf = ureg_src(data);
581 } else {
582 outz = ureg_writemask(out, TGSI_WRITEMASK_YZW);
583 outs = ureg_writemask(out, TGSI_WRITEMASK_X);
584 zshuf = ureg_swizzle(zsrc3, TGSI_SWIZZLE_W,
585 TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z);
586 }
587
588 if (tex_s) {
589 ureg_I2F(ureg, sdst, ssrc);
590 ureg_MUL(ureg, outs, ssrc, ureg_scalar(scale, TGSI_SWIZZLE_X));
591 }
592
593 if (tex_rgbaz) {
594 ureg_MUL(ureg, zdst, zsrc, ureg_scalar(scale, TGSI_SWIZZLE_W));
595 ureg_F2I(ureg, zdst, zsrc);
596 ureg_AND(ureg, zdst3, zsrc, mask);
597 ureg_I2F(ureg, zdst3, zsrc3);
598 ureg_MUL(ureg, zdst3, zsrc3, scale);
599 ureg_MOV(ureg, outz, zshuf);
600 }
601 } else {
602 unsigned mask = TGSI_WRITEMASK_XYZW;
603
604 if (mode != NV50_BLIT_MODE_PASS) {
605 mask &= ~TGSI_WRITEMASK_ZW;
606 if (!tex_s)
607 mask = TGSI_WRITEMASK_X;
608 if (!tex_rgbaz)
609 mask = TGSI_WRITEMASK_Y;
610 }
611 ureg_MOV(ureg, ureg_writemask(out, mask), ureg_src(data));
612 }
613 ureg_END(ureg);
614
615 return ureg_create_shader_and_destroy(ureg, pipe);
616 }
617
618 static void
619 nv50_blitter_make_sampler(struct nv50_blitter *blit)
620 {
621 /* clamp to edge, min/max lod = 0, nearest filtering */
622
623 blit->sampler[0].id = -1;
624
625 blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
626 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
627 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
628 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
629 blit->sampler[0].tsc[1] =
630 NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
631
632 /* clamp to edge, min/max lod = 0, bilinear filtering */
633
634 blit->sampler[1].id = -1;
635
636 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
637 blit->sampler[1].tsc[1] =
638 NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
639 }
640
641 unsigned
642 nv50_blit_select_mode(const struct pipe_blit_info *info)
643 {
644 const unsigned mask = info->mask;
645
646 switch (info->dst.resource->format) {
647 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
648 case PIPE_FORMAT_Z24X8_UNORM:
649 switch (mask & PIPE_MASK_ZS) {
650 case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
651 case PIPE_MASK_Z: return NV50_BLIT_MODE_Z24X8;
652 default:
653 return NV50_BLIT_MODE_X24S8;
654 }
655 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
656 switch (mask & PIPE_MASK_ZS) {
657 case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
658 case PIPE_MASK_Z: return NV50_BLIT_MODE_X8Z24;
659 default:
660 return NV50_BLIT_MODE_S8X24;
661 }
662 case PIPE_FORMAT_Z32_FLOAT:
663 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
664 switch (mask & PIPE_MASK_ZS) {
665 case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
666 case PIPE_MASK_Z: return NV50_BLIT_MODE_PASS;
667 default:
668 return NV50_BLIT_MODE_XS;
669 }
670 default:
671 return NV50_BLIT_MODE_PASS;
672 }
673 }
674
675 static void
676 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
677 {
678 struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
679
680 const enum pipe_texture_target ptarg =
681 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
682
683 const unsigned targ = nv50_blit_texture_type(ptarg);
684 const unsigned mode = ctx->mode;
685
686 if (!blitter->fp[targ][mode]) {
687 pipe_mutex_lock(blitter->mutex);
688 if (!blitter->fp[targ][mode])
689 blitter->fp[targ][mode] =
690 nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
691 pipe_mutex_unlock(blitter->mutex);
692 }
693 ctx->fp = blitter->fp[targ][mode];
694 }
695
696 static void
697 nv50_blit_set_dst(struct nv50_blitctx *ctx,
698 struct pipe_resource *res, unsigned level, unsigned layer,
699 enum pipe_format format)
700 {
701 struct nv50_context *nv50 = ctx->nv50;
702 struct pipe_context *pipe = &nv50->base.pipe;
703 struct pipe_surface templ;
704
705 if (util_format_is_depth_or_stencil(format))
706 templ.format = nv50_blit_zeta_to_colour_format(format);
707 else
708 templ.format = format;
709
710 templ.u.tex.level = level;
711 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
712
713 if (layer == -1) {
714 templ.u.tex.first_layer = 0;
715 templ.u.tex.last_layer =
716 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
717 }
718
719 nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
720 nv50->framebuffer.nr_cbufs = 1;
721 nv50->framebuffer.zsbuf = NULL;
722 nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
723 nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
724 }
725
726 static void
727 nv50_blit_set_src(struct nv50_blitctx *blit,
728 struct pipe_resource *res, unsigned level, unsigned layer,
729 enum pipe_format format, const uint8_t filter)
730 {
731 struct nv50_context *nv50 = blit->nv50;
732 struct pipe_context *pipe = &nv50->base.pipe;
733 struct pipe_sampler_view templ;
734 uint32_t flags;
735 enum pipe_texture_target target;
736
737 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
738
739 templ.format = format;
740 templ.u.tex.first_level = templ.u.tex.last_level = level;
741 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
742 templ.swizzle_r = PIPE_SWIZZLE_RED;
743 templ.swizzle_g = PIPE_SWIZZLE_GREEN;
744 templ.swizzle_b = PIPE_SWIZZLE_BLUE;
745 templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
746
747 if (layer == -1) {
748 templ.u.tex.first_layer = 0;
749 templ.u.tex.last_layer =
750 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
751 }
752
753 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
754 if (filter && res->nr_samples == 8)
755 flags |= NV50_TEXVIEW_FILTER_MSAA8;
756
757 nv50->textures[2][0] = nv50_create_texture_view(
758 pipe, res, &templ, flags, target);
759 nv50->textures[2][1] = NULL;
760
761 nv50->num_textures[0] = nv50->num_textures[1] = 0;
762 nv50->num_textures[2] = 1;
763
764 templ.format = nv50_zs_to_s_format(format);
765 if (templ.format != res->format) {
766 nv50->textures[2][1] = nv50_create_texture_view(
767 pipe, res, &templ, flags, target);
768 nv50->num_textures[2] = 2;
769 }
770 }
771
772 static void
773 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
774 {
775 struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
776
777 if (blit->nv50->cond_query) {
778 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
779 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
780 }
781
782 /* blend state */
783 BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
784 PUSH_DATA (push, blit->color_mask);
785 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
786 PUSH_DATA (push, 0);
787 BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
788 PUSH_DATA (push, 0);
789
790 /* rasterizer state */
791 #ifndef NV50_SCISSORS_CLIPPING
792 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
793 PUSH_DATA (push, 1);
794 #endif
795 BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
796 PUSH_DATA (push, 0);
797 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
798 PUSH_DATA (push, 0);
799 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
800 PUSH_DATA (push, 0);
801 BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
802 PUSH_DATA (push, 0xffff);
803 PUSH_DATA (push, 0xffff);
804 PUSH_DATA (push, 0xffff);
805 PUSH_DATA (push, 0xffff);
806 BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
807 PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
808 PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
809 PUSH_DATA (push, 0);
810 BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
811 PUSH_DATA (push, 0);
812 BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
813 PUSH_DATA (push, 0);
814 BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
815 PUSH_DATA (push, 0);
816
817 /* zsa state */
818 BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
819 PUSH_DATA (push, 0);
820 BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
821 PUSH_DATA (push, 0);
822 BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
823 PUSH_DATA (push, 0);
824 }
825
826 static void
827 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx)
828 {
829 struct nv50_context *nv50 = ctx->nv50;
830 struct nv50_blitter *blitter = nv50->screen->blitter;
831 int s;
832
833 ctx->saved.fb.width = nv50->framebuffer.width;
834 ctx->saved.fb.height = nv50->framebuffer.height;
835 ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
836 ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
837 ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
838
839 ctx->saved.vp = nv50->vertprog;
840 ctx->saved.gp = nv50->gmtyprog;
841 ctx->saved.fp = nv50->fragprog;
842
843 nv50->vertprog = &blitter->vp;
844 nv50->gmtyprog = NULL;
845 nv50->fragprog = ctx->fp;
846
847 for (s = 0; s < 3; ++s) {
848 ctx->saved.num_textures[s] = nv50->num_textures[s];
849 ctx->saved.num_samplers[s] = nv50->num_samplers[s];
850 }
851 ctx->saved.texture[0] = nv50->textures[2][0];
852 ctx->saved.texture[1] = nv50->textures[2][1];
853 ctx->saved.sampler[0] = nv50->samplers[2][0];
854 ctx->saved.sampler[1] = nv50->samplers[2][1];
855
856 nv50->samplers[2][0] = &blitter->sampler[ctx->filter];
857 nv50->samplers[2][1] = &blitter->sampler[ctx->filter];
858
859 nv50->num_samplers[0] = nv50->num_samplers[1] = 0;
860 nv50->num_samplers[2] = 2;
861
862 ctx->saved.dirty = nv50->dirty;
863
864 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
865 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
866
867 nv50->dirty =
868 NV50_NEW_FRAMEBUFFER |
869 NV50_NEW_VERTPROG | NV50_NEW_FRAGPROG | NV50_NEW_GMTYPROG |
870 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS;
871 }
872
873 static void
874 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
875 {
876 struct nv50_context *nv50 = blit->nv50;
877 int s;
878
879 pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
880
881 nv50->framebuffer.width = blit->saved.fb.width;
882 nv50->framebuffer.height = blit->saved.fb.height;
883 nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
884 nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
885 nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
886
887 nv50->vertprog = blit->saved.vp;
888 nv50->gmtyprog = blit->saved.gp;
889 nv50->fragprog = blit->saved.fp;
890
891 pipe_sampler_view_reference(&nv50->textures[2][0], NULL);
892 pipe_sampler_view_reference(&nv50->textures[2][1], NULL);
893
894 for (s = 0; s < 3; ++s) {
895 nv50->num_textures[s] = blit->saved.num_textures[s];
896 nv50->num_samplers[s] = blit->saved.num_samplers[s];
897 }
898 nv50->textures[2][0] = blit->saved.texture[0];
899 nv50->textures[2][1] = blit->saved.texture[1];
900 nv50->samplers[2][0] = blit->saved.sampler[0];
901 nv50->samplers[2][1] = blit->saved.sampler[1];
902
903 if (nv50->cond_query)
904 nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
905 nv50->cond_mode);
906
907 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
908 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
909
910 nv50->dirty = blit->saved.dirty |
911 (NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR | NV50_NEW_SAMPLE_MASK |
912 NV50_NEW_RASTERIZER | NV50_NEW_ZSA | NV50_NEW_BLEND |
913 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS |
914 NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG | NV50_NEW_FRAGPROG);
915 }
916
917
918 static void
919 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
920 {
921 struct nv50_blitctx *blit = nv50->blit;
922 struct nouveau_pushbuf *push = nv50->base.pushbuf;
923 struct pipe_resource *src = info->src.resource;
924 struct pipe_resource *dst = info->dst.resource;
925 int32_t minx, maxx, miny, maxy;
926 int32_t i;
927 float x0, x1, y0, y1, z;
928 float dz;
929 float x_range, y_range;
930
931 blit->mode = nv50_blit_select_mode(info);
932 blit->color_mask = nv50_blit_derive_color_mask(info);
933 blit->filter = nv50_blit_get_filter(info);
934
935 nv50_blit_select_fp(blit, info);
936 nv50_blitctx_pre_blit(blit);
937
938 nv50_blit_set_dst(blit, dst, info->dst.level, 0, info->dst.format);
939 nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
940 blit->filter);
941
942 nv50_blitctx_prepare_state(blit);
943
944 nv50_state_validate(nv50, ~0, 36);
945
946 x_range = (float)info->src.box.width / (float)info->dst.box.width;
947 y_range = (float)info->src.box.height / (float)info->dst.box.height;
948
949 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
950 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
951
952 x1 = x0 + 16384.0f * x_range;
953 y1 = y0 + 16384.0f * y_range;
954
955 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
956 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
957 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
958 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
959
960 if (src->last_level > 0) {
961 /* If there are mip maps, GPU always assumes normalized coordinates. */
962 const unsigned l = info->src.level;
963 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
964 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
965 x0 /= fh;
966 x1 /= fh;
967 y0 /= fv;
968 y1 /= fv;
969 }
970
971 /* XXX: multiply by 6 for cube arrays ? */
972 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
973 z = (float)info->src.box.z;
974 if (nv50_miptree(src)->layout_3d)
975 z += 0.5f * dz;
976
977 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
978 PUSH_DATA (push, 0);
979
980 /* Draw a large triangle in screen coordinates covering the whole
981 * render target, with scissors defining the destination region.
982 * The vertex is supplied with non-normalized texture coordinates
983 * arranged in a way to yield the desired offset and scale.
984 */
985
986 minx = info->dst.box.x;
987 maxx = info->dst.box.x + info->dst.box.width;
988 miny = info->dst.box.y;
989 maxy = info->dst.box.y + info->dst.box.height;
990 if (info->scissor_enable) {
991 minx = MAX2(minx, info->scissor.minx);
992 maxx = MIN2(maxx, info->scissor.maxx);
993 miny = MAX2(miny, info->scissor.miny);
994 maxy = MIN2(maxy, info->scissor.maxy);
995 }
996 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
997 PUSH_DATA (push, (maxx << 16) | minx);
998 PUSH_DATA (push, (maxy << 16) | miny);
999
1000 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1001 if (info->dst.box.z + i) {
1002 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1003 PUSH_DATA (push, info->dst.box.z + i);
1004 }
1005 PUSH_SPACE(push, 32);
1006 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1007 PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1008 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1009 PUSH_DATAf(push, x0);
1010 PUSH_DATAf(push, y0);
1011 PUSH_DATAf(push, z);
1012 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1013 PUSH_DATAf(push, 0.0f);
1014 PUSH_DATAf(push, 0.0f);
1015 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1016 PUSH_DATAf(push, x1);
1017 PUSH_DATAf(push, y0);
1018 PUSH_DATAf(push, z);
1019 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1020 PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_x);
1021 PUSH_DATAf(push, 0.0f);
1022 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1023 PUSH_DATAf(push, x0);
1024 PUSH_DATAf(push, y1);
1025 PUSH_DATAf(push, z);
1026 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1027 PUSH_DATAf(push, 0.0f);
1028 PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_y);
1029 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1030 PUSH_DATA (push, 0);
1031 }
1032 if (info->dst.box.z + info->dst.box.depth - 1) {
1033 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1034 PUSH_DATA (push, 0);
1035 }
1036
1037 /* re-enable normally constant state */
1038
1039 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1040 PUSH_DATA (push, 1);
1041
1042 nv50_blitctx_post_blit(blit);
1043 }
1044
1045 static void
1046 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1047 {
1048 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1049 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1050 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1051 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1052 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1053 const int32_t dz = info->dst.box.z;
1054 const int32_t sz = info->src.box.z;
1055 uint32_t dstw, dsth;
1056 int32_t dstx, dsty;
1057 int64_t srcx, srcy;
1058 int64_t du_dx, dv_dy;
1059 int i;
1060 uint32_t mode;
1061 const uint32_t mask = nv50_blit_eng2d_get_mask(info);
1062
1063 mode = nv50_blit_get_filter(info) ?
1064 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1065 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1066 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1067 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1068
1069 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1070 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1071
1072 nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format);
1073 nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format);
1074
1075 if (info->scissor_enable) {
1076 BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1077 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1078 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1079 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1080 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1081 PUSH_DATA (push, 1); /* enable */
1082 }
1083
1084 if (mask != 0xffffffff) {
1085 BEGIN_NV04(push, NV50_2D(ROP), 1);
1086 PUSH_DATA (push, 0xca); /* DPSDxax */
1087 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1088 PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_32BPP);
1089 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR(0)), 4);
1090 PUSH_DATA (push, 0x00000000);
1091 PUSH_DATA (push, mask);
1092 PUSH_DATA (push, 0xffffffff);
1093 PUSH_DATA (push, 0xffffffff);
1094 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1095 PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1096 }
1097
1098 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1099 /* ms_x is always >= ms_y */
1100 du_dx <<= src->ms_x - dst->ms_x;
1101 dv_dy <<= src->ms_y - dst->ms_y;
1102 } else {
1103 du_dx >>= dst->ms_x - src->ms_x;
1104 dv_dy >>= dst->ms_y - src->ms_y;
1105 }
1106
1107 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1108 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1109
1110 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1111 /* center src coorinates for proper MS resolve filtering */
1112 srcx += (int64_t)src->ms_x << 32;
1113 srcy += (int64_t)src->ms_y << 32;
1114 }
1115
1116 dstx = info->dst.box.x << dst->ms_x;
1117 dsty = info->dst.box.y << dst->ms_y;
1118
1119 dstw = info->dst.box.width << dst->ms_x;
1120 dsth = info->dst.box.height << dst->ms_y;
1121
1122 if (dstx < 0) {
1123 dstw += dstx;
1124 srcx -= du_dx * dstx;
1125 dstx = 0;
1126 }
1127 if (dsty < 0) {
1128 dsth += dsty;
1129 srcy -= dv_dy * dsty;
1130 dsty = 0;
1131 }
1132
1133 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1134 PUSH_DATA (push, mode);
1135 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1136 PUSH_DATA (push, dstx);
1137 PUSH_DATA (push, dsty);
1138 PUSH_DATA (push, dstw);
1139 PUSH_DATA (push, dsth);
1140 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1141 PUSH_DATA (push, du_dx);
1142 PUSH_DATA (push, du_dx >> 32);
1143 PUSH_DATA (push, dv_dy);
1144 PUSH_DATA (push, dv_dy >> 32);
1145
1146 BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1147 BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1148 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1149 if (nouveau_pushbuf_validate(nv50->base.pushbuf))
1150 return;
1151
1152 for (i = 0; i < info->dst.box.depth; ++i) {
1153 if (i > 0) {
1154 /* no scaling in z-direction possible for eng2d blits */
1155 if (dst->layout_3d) {
1156 BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1157 PUSH_DATA (push, info->dst.box.z + i);
1158 } else {
1159 const unsigned z = info->dst.box.z + i;
1160 BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1161 PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
1162 PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
1163 }
1164 if (src->layout_3d) {
1165 /* not possible because of depth tiling */
1166 assert(0);
1167 } else {
1168 const unsigned z = info->src.box.z + i;
1169 BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1170 PUSH_DATAh(push, src->base.address + z * src->layer_stride);
1171 PUSH_DATA (push, src->base.address + z * src->layer_stride);
1172 }
1173 BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1174 PUSH_DATA (push, srcy >> 32);
1175 } else {
1176 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1177 PUSH_DATA (push, srcx);
1178 PUSH_DATA (push, srcx >> 32);
1179 PUSH_DATA (push, srcy);
1180 PUSH_DATA (push, srcy >> 32);
1181 }
1182 }
1183 nv50_bufctx_fence(nv50->bufctx, FALSE);
1184
1185 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1186
1187 if (info->scissor_enable) {
1188 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1189 PUSH_DATA (push, 0);
1190 }
1191 if (mask != 0xffffffff) {
1192 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1193 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1194 }
1195 }
1196
1197 static void
1198 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1199 {
1200 struct nv50_context *nv50 = nv50_context(pipe);
1201 boolean eng3d = FALSE;
1202
1203 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1204 if (!(info->mask & PIPE_MASK_ZS))
1205 return;
1206 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1207 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1208 eng3d = TRUE;
1209 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1210 eng3d = TRUE;
1211 } else {
1212 if (!(info->mask & PIPE_MASK_RGBA))
1213 return;
1214 if (info->mask != PIPE_MASK_RGBA)
1215 eng3d = TRUE;
1216 }
1217
1218 if (nv50_miptree(info->src.resource)->layout_3d) {
1219 eng3d = TRUE;
1220 } else
1221 if (info->src.box.depth != info->dst.box.depth) {
1222 eng3d = TRUE;
1223 debug_printf("blit: cannot filter array or cube textures in z direction");
1224 }
1225
1226 if (!eng3d && info->dst.format != info->src.format)
1227 if (!nv50_2d_format_faithful(info->dst.format) ||
1228 !nv50_2d_format_faithful(info->src.format))
1229 eng3d = TRUE;
1230
1231 if (info->src.resource->nr_samples == 8 &&
1232 info->dst.resource->nr_samples <= 1)
1233 eng3d = TRUE;
1234
1235 /* FIXME: can't make this work with eng2d anymore */
1236 if (info->src.resource->nr_samples > 1 ||
1237 info->dst.resource->nr_samples > 1)
1238 eng3d = TRUE;
1239
1240 /* FIXME: find correct src coordinate adjustments */
1241 if ((info->src.box.width != info->dst.box.width &&
1242 info->src.box.width != -info->dst.box.width) ||
1243 (info->src.box.height != info->dst.box.height &&
1244 info->src.box.height != -info->dst.box.height))
1245 eng3d = TRUE;
1246
1247 if (!eng3d)
1248 nv50_blit_eng2d(nv50, info);
1249 else
1250 nv50_blit_3d(nv50, info);
1251 }
1252
1253 boolean
1254 nv50_blitter_create(struct nv50_screen *screen)
1255 {
1256 screen->blitter = CALLOC_STRUCT(nv50_blitter);
1257 if (!screen->blitter) {
1258 NOUVEAU_ERR("failed to allocate blitter struct\n");
1259 return FALSE;
1260 }
1261
1262 pipe_mutex_init(screen->blitter->mutex);
1263
1264 nv50_blitter_make_vp(screen->blitter);
1265 nv50_blitter_make_sampler(screen->blitter);
1266
1267 return TRUE;
1268 }
1269
1270 void
1271 nv50_blitter_destroy(struct nv50_screen *screen)
1272 {
1273 struct nv50_blitter *blitter = screen->blitter;
1274 unsigned i, m;
1275
1276 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1277 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1278 struct nv50_program *prog = blitter->fp[i][m];
1279 if (prog) {
1280 nv50_program_destroy(NULL, prog);
1281 FREE((void *)prog->pipe.tokens);
1282 FREE(prog);
1283 }
1284 }
1285 }
1286
1287 FREE(blitter);
1288 }
1289
1290 boolean
1291 nv50_blitctx_create(struct nv50_context *nv50)
1292 {
1293 nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1294 if (!nv50->blit) {
1295 NOUVEAU_ERR("failed to allocate blit context\n");
1296 return FALSE;
1297 }
1298
1299 nv50->blit->nv50 = nv50;
1300
1301 return TRUE;
1302 }
1303
1304 void
1305 nv50_init_surface_functions(struct nv50_context *nv50)
1306 {
1307 struct pipe_context *pipe = &nv50->base.pipe;
1308
1309 pipe->resource_copy_region = nv50_resource_copy_region;
1310 pipe->blit = nv50_blit;
1311 pipe->clear_render_target = nv50_clear_render_target;
1312 pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1313 }
1314
1315