src/gallium/drivers/nv50/nv50_surface.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include <stdint.h>
  24
  25 #include "pipe/p_defines.h"
  26
  27 #include "util/u_inlines.h"
  28 #include "util/u_pack_color.h"
  29 #include "util/u_format.h"
  30 #include "util/u_surface.h"
  31
  32 #include "nv50_context.h"
  33 #include "nv50_resource.h"
  34
  35 #include "nv50_defs.xml.h"
  36
  37 /* return TRUE for formats that can be converted among each other by NV50_2D */
  38 static INLINE boolean
  39 nv50_2d_format_faithful(enum pipe_format format)
  40 {
  41    switch (format) {
  42    case PIPE_FORMAT_B8G8R8A8_UNORM:
  43    case PIPE_FORMAT_B8G8R8X8_UNORM:
  44    case PIPE_FORMAT_B8G8R8A8_SRGB:
  45    case PIPE_FORMAT_B8G8R8X8_SRGB:
  46    case PIPE_FORMAT_B5G6R5_UNORM:
  47    case PIPE_FORMAT_B5G5R5A1_UNORM:
  48    case PIPE_FORMAT_B10G10R10A2_UNORM:
  49    case PIPE_FORMAT_R8_UNORM:
  50    case PIPE_FORMAT_R32G32B32A32_FLOAT:
  51    case PIPE_FORMAT_R32G32B32_FLOAT:
  52       return TRUE;
  53    default:
  54       return FALSE;
  55    }
  56 }
  57
  58 static INLINE uint8_t
  59 nv50_2d_format(enum pipe_format format)
  60 {
  61    uint8_t id = nv50_format_table[format].rt;
  62
  63    /* Hardware values for color formats range from 0xc0 to 0xff,
  64     * but the 2D engine doesn't support all of them.
  65     */
  66    if ((id >= 0xc0) && (0xff0843e080608409ULL & (1ULL << (id - 0xc0))))
  67       return id;
  68
  69    switch (util_format_get_blocksize(format)) {
  70    case 1:
  71       return NV50_SURFACE_FORMAT_R8_UNORM;
  72    case 2:
  73       return NV50_SURFACE_FORMAT_R16_UNORM;
  74    case 4:
  75       return NV50_SURFACE_FORMAT_A8R8G8B8_UNORM;
  76    default:
  77       return 0;
  78    }
  79 }
  80
  81 static int
  82 nv50_2d_texture_set(struct nouveau_channel *chan, int dst,
  83                     struct nv50_miptree *mt, unsigned level, unsigned layer)
  84 {
  85    struct nouveau_bo *bo = mt->base.bo;
  86    uint32_t width, height, depth;
  87    uint32_t format;
  88    uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
  89    uint32_t flags = mt->base.domain | (dst ? NOUVEAU_BO_WR : NOUVEAU_BO_RD);
  90    uint32_t offset = mt->level[level].offset;
  91
  92    format = nv50_2d_format(mt->base.base.format);
  93    if (!format) {
  94       NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
  95                   util_format_name(mt->base.base.format));
  96       return 1;
  97    }
  98
  99    width = u_minify(mt->base.base.width0, level);
 100    height = u_minify(mt->base.base.height0, level);
 101
 102    offset = mt->level[level].offset;
 103    if (!mt->layout_3d) {
 104       offset += mt->layer_stride * layer;
 105       depth = 1;
 106       layer = 0;
 107    } else {
 108       depth = u_minify(mt->base.base.depth0, level);
 109    }
 110
 111    if (!(bo->tile_flags & NOUVEAU_BO_TILE_LAYOUT_MASK)) {
 112       BEGIN_RING(chan, RING_2D_(mthd), 2);
 113       OUT_RING  (chan, format);
 114       OUT_RING  (chan, 1);
 115       BEGIN_RING(chan, RING_2D_(mthd + 0x14), 5);
 116       OUT_RING  (chan, mt->level[level].pitch);
 117       OUT_RING  (chan, width);
 118       OUT_RING  (chan, height);
 119       OUT_RELOCh(chan, bo, offset, flags);
 120       OUT_RELOCl(chan, bo, offset, flags);
 121    } else {
 122       BEGIN_RING(chan, RING_2D_(mthd), 5);
 123       OUT_RING  (chan, format);
 124       OUT_RING  (chan, 0);
 125       OUT_RING  (chan, mt->level[level].tile_mode << 4);
 126       OUT_RING  (chan, depth);
 127       OUT_RING  (chan, layer);
 128       BEGIN_RING(chan, RING_2D_(mthd + 0x18), 4);
 129       OUT_RING  (chan, width);
 130       OUT_RING  (chan, height);
 131       OUT_RELOCh(chan, bo, offset, flags);
 132       OUT_RELOCl(chan, bo, offset, flags);
 133    }
 134
 135 #if 0
 136    if (dst) {
 137       BEGIN_RING(chan, RING_2D_(NV50_2D_CLIP_X), 4);
 138       OUT_RING  (chan, 0);
 139       OUT_RING  (chan, 0);
 140       OUT_RING  (chan, width);
 141       OUT_RING  (chan, height);
 142    }
 143 #endif
 144    return 0;
 145 }
 146
 147 static int
 148 nv50_2d_texture_do_copy(struct nouveau_channel *chan,
 149                         struct nv50_miptree *dst, unsigned dst_level,
 150                         unsigned dx, unsigned dy, unsigned dz,
 151                         struct nv50_miptree *src, unsigned src_level,
 152                         unsigned sx, unsigned sy, unsigned sz,
 153                         unsigned w, unsigned h)
 154 {
 155    int ret;
 156
 157    ret = MARK_RING(chan, 2 * 16 + 32, 4);
 158    if (ret)
 159       return ret;
 160
 161    ret = nv50_2d_texture_set(chan, 1, dst, dst_level, dz);
 162    if (ret)
 163       return ret;
 164
 165    ret = nv50_2d_texture_set(chan, 0, src, src_level, sz);
 166    if (ret)
 167       return ret;
 168
 169    /* 0/1 = CENTER/CORNER, 10/00 = POINT/BILINEAR */
 170    BEGIN_RING(chan, RING_2D(BLIT_CONTROL), 1);
 171    OUT_RING  (chan, 0);
 172    BEGIN_RING(chan, RING_2D(BLIT_DST_X), 4);
 173    OUT_RING  (chan, dx);
 174    OUT_RING  (chan, dy);
 175    OUT_RING  (chan, w);
 176    OUT_RING  (chan, h);
 177    BEGIN_RING(chan, RING_2D(BLIT_DU_DX_FRACT), 4);
 178    OUT_RING  (chan, 0);
 179    OUT_RING  (chan, 1);
 180    OUT_RING  (chan, 0);
 181    OUT_RING  (chan, 1);
 182    BEGIN_RING(chan, RING_2D(BLIT_SRC_X_FRACT), 4);
 183    OUT_RING  (chan, 0);
 184    OUT_RING  (chan, sx);
 185    OUT_RING  (chan, 0);
 186    OUT_RING  (chan, sy);
 187
 188    return 0;
 189 }
 190
 191 static void
 192 nv50_resource_copy_region(struct pipe_context *pipe,
 193                           struct pipe_resource *dst, unsigned dst_level,
 194                           unsigned dstx, unsigned dsty, unsigned dstz,
 195                           struct pipe_resource *src, unsigned src_level,
 196                           const struct pipe_box *src_box)
 197 {
 198    struct nv50_screen *screen = nv50_context(pipe)->screen;
 199    int ret;
 200    unsigned dst_layer = dstz, src_layer = src_box->z;
 201
 202    /* Fallback for buffers. */
 203    if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 204       util_resource_copy_region(pipe, dst, dst_level, dstx, dsty, dstz,
 205                                 src, src_level, src_box);
 206       return;
 207    }
 208
 209    assert((src->format == dst->format) ||
 210           (nv50_2d_format_faithful(src->format) &&
 211            nv50_2d_format_faithful(dst->format)));
 212
 213    for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
 214       ret = nv50_2d_texture_do_copy(screen->base.channel,
 215                                     nv50_miptree(dst), dst_level,
 216                                     dstx, dsty, dst_layer,
 217                                     nv50_miptree(src), src_level,
 218                                     src_box->x, src_box->y, src_layer,
 219                                     src_box->width, src_box->height);
 220       if (ret)
 221          return;
 222    }
 223 }
 224
 225 static void
 226 nv50_clear_render_target(struct pipe_context *pipe,
 227                          struct pipe_surface *dst,
 228                          const float *rgba,
 229                          unsigned dstx, unsigned dsty,
 230                          unsigned width, unsigned height)
 231 {
 232    struct nv50_context *nv50 = nv50_context(pipe);
 233    struct nv50_screen *screen = nv50->screen;
 234    struct nouveau_channel *chan = screen->base.channel;
 235    struct nv50_miptree *mt = nv50_miptree(dst->texture);
 236    struct nv50_surface *sf = nv50_surface(dst);
 237    struct nouveau_bo *bo = mt->base.bo;
 238
 239    BEGIN_RING(chan, RING_3D(CLEAR_COLOR(0)), 4);
 240    OUT_RINGf (chan, rgba[0]);
 241    OUT_RINGf (chan, rgba[1]);
 242    OUT_RINGf (chan, rgba[2]);
 243    OUT_RINGf (chan, rgba[3]);
 244
 245    if (MARK_RING(chan, 18, 2))
 246       return;
 247
 248    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 249    OUT_RING  (chan, 1);
 250    BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(0)), 5);
 251    OUT_RELOCh(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 252    OUT_RELOCl(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 253    OUT_RING  (chan, nv50_format_table[dst->format].rt);
 254    OUT_RING  (chan, mt->level[sf->base.u.tex.level].tile_mode << 4);
 255    OUT_RING  (chan, 0);
 256    BEGIN_RING(chan, RING_3D(RT_HORIZ(0)), 2);
 257    OUT_RING  (chan, sf->width);
 258    OUT_RING  (chan, sf->height);
 259    BEGIN_RING(chan, RING_3D(RT_ARRAY_MODE), 1);
 260    OUT_RING  (chan, 1);
 261
 262    /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
 263
 264    BEGIN_RING(chan, RING_3D(VIEWPORT_HORIZ(0)), 2);
 265    OUT_RING  (chan, (width << 16) | dstx);
 266    OUT_RING  (chan, (height << 16) | dsty);
 267
 268    BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
 269    OUT_RING  (chan, 0x3c);
 270
 271    nv50->dirty |= NV50_NEW_FRAMEBUFFER;
 272 }
 273
 274 static void
 275 nv50_clear_depth_stencil(struct pipe_context *pipe,
 276                          struct pipe_surface *dst,
 277                          unsigned clear_flags,
 278                          double depth,
 279                          unsigned stencil,
 280                          unsigned dstx, unsigned dsty,
 281                          unsigned width, unsigned height)
 282 {
 283    struct nv50_context *nv50 = nv50_context(pipe);
 284    struct nv50_screen *screen = nv50->screen;
 285    struct nouveau_channel *chan = screen->base.channel;
 286    struct nv50_miptree *mt = nv50_miptree(dst->texture);
 287    struct nv50_surface *sf = nv50_surface(dst);
 288    struct nouveau_bo *bo = mt->base.bo;
 289    uint32_t mode = 0;
 290
 291    if (clear_flags & PIPE_CLEAR_DEPTH) {
 292       BEGIN_RING(chan, RING_3D(CLEAR_DEPTH), 1);
 293       OUT_RINGf (chan, depth);
 294       mode |= NV50_3D_CLEAR_BUFFERS_Z;
 295    }
 296
 297    if (clear_flags & PIPE_CLEAR_STENCIL) {
 298       BEGIN_RING(chan, RING_3D(CLEAR_STENCIL), 1);
 299       OUT_RING  (chan, stencil & 0xff);
 300       mode |= NV50_3D_CLEAR_BUFFERS_S;
 301    }
 302
 303    if (MARK_RING(chan, 17, 2))
 304       return;
 305
 306    BEGIN_RING(chan, RING_3D(ZETA_ADDRESS_HIGH), 5);
 307    OUT_RELOCh(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 308    OUT_RELOCl(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 309    OUT_RING  (chan, nv50_format_table[dst->format].rt);
 310    OUT_RING  (chan, mt->level[sf->base.u.tex.level].tile_mode << 4);
 311    OUT_RING  (chan, 0);
 312    BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
 313    OUT_RING  (chan, 1);
 314    BEGIN_RING(chan, RING_3D(ZETA_HORIZ), 3);
 315    OUT_RING  (chan, sf->width);
 316    OUT_RING  (chan, sf->height);
 317    OUT_RING  (chan, (1 << 16) | 1);
 318
 319    BEGIN_RING(chan, RING_3D(VIEWPORT_HORIZ(0)), 2);
 320    OUT_RING  (chan, (width << 16) | dstx);
 321    OUT_RING  (chan, (height << 16) | dsty);
 322
 323    BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
 324    OUT_RING  (chan, mode);
 325
 326    nv50->dirty |= NV50_NEW_FRAMEBUFFER;
 327 }
 328
 329 void
 330 nv50_clear(struct pipe_context *pipe, unsigned buffers,
 331            const float *rgba, double depth, unsigned stencil)
 332 {
 333    struct nv50_context *nv50 = nv50_context(pipe);
 334    struct nouveau_channel *chan = nv50->screen->base.channel;
 335    struct pipe_framebuffer_state *fb = &nv50->framebuffer;
 336    unsigned i;
 337    const unsigned dirty = nv50->dirty;
 338    uint32_t mode = 0;
 339
 340    /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
 341    nv50->dirty &= NV50_NEW_FRAMEBUFFER;
 342    if (!nv50_state_validate(nv50))
 343       return;
 344
 345    if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
 346       BEGIN_RING(chan, RING_3D(CLEAR_COLOR(0)), 4);
 347       OUT_RINGf (chan, rgba[0]);
 348       OUT_RINGf (chan, rgba[1]);
 349       OUT_RINGf (chan, rgba[2]);
 350       OUT_RINGf (chan, rgba[3]);
 351       mode =
 352          NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
 353          NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
 354    }
 355
 356    if (buffers & PIPE_CLEAR_DEPTH) {
 357       BEGIN_RING(chan, RING_3D(CLEAR_DEPTH), 1);
 358       OUT_RING  (chan, fui(depth));
 359       mode |= NV50_3D_CLEAR_BUFFERS_Z;
 360    }
 361
 362    if (buffers & PIPE_CLEAR_STENCIL) {
 363       BEGIN_RING(chan, RING_3D(CLEAR_STENCIL), 1);
 364       OUT_RING  (chan, stencil & 0xff);
 365       mode |= NV50_3D_CLEAR_BUFFERS_S;
 366    }
 367
 368    BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
 369    OUT_RING  (chan, mode);
 370
 371    for (i = 1; i < fb->nr_cbufs; i++) {
 372       BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
 373       OUT_RING  (chan, (i << 6) | 0x3c);
 374    }
 375
 376    nv50->dirty = dirty & ~NV50_NEW_FRAMEBUFFER;
 377 }
 378
 379 void
 380 nv50_init_surface_functions(struct nv50_context *nv50)
 381 {
 382    struct pipe_context *pipe = &nv50->base.pipe;
 383
 384    pipe->resource_copy_region = nv50_resource_copy_region;
 385    pipe->clear_render_target = nv50_clear_render_target;
 386    pipe->clear_depth_stencil = nv50_clear_depth_stencil;
 387 }
 388
 389