src/gallium/drivers/nv50/nv50_surface.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include <stdint.h>
  24
  25 #include "pipe/p_defines.h"
  26
  27 #include "util/u_inlines.h"
  28 #include "util/u_pack_color.h"
  29 #include "util/u_format.h"
  30 #include "util/u_surface.h"
  31
  32 #include "tgsi/tgsi_ureg.h"
  33
  34 #include "os/os_thread.h"
  35
  36 #include "nv50_context.h"
  37 #include "nv50_resource.h"
  38 #include "nv50_blit.h"
  39
  40 #include "nv50_defs.xml.h"
  41 #include "nv50_texture.xml.h"
  42
  43 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
  44
  45 /* return TRUE for formats that can be converted among each other by NV50_2D */
  46 static INLINE boolean
  47 nv50_2d_format_faithful(enum pipe_format format)
  48 {
  49    uint8_t id = nv50_format_table[format].rt;
  50
  51    return (id >= 0xc0) &&
  52       (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0)));
  53 }
  54
  55 static INLINE uint8_t
  56 nv50_2d_format(enum pipe_format format)
  57 {
  58    uint8_t id = nv50_format_table[format].rt;
  59
  60    /* Hardware values for color formats range from 0xc0 to 0xff,
  61     * but the 2D engine doesn't support all of them.
  62     */
  63    if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
  64       return id;
  65
  66    switch (util_format_get_blocksize(format)) {
  67    case 1:
  68       return NV50_SURFACE_FORMAT_R8_UNORM;
  69    case 2:
  70       return NV50_SURFACE_FORMAT_R16_UNORM;
  71    case 4:
  72       return NV50_SURFACE_FORMAT_BGRA8_UNORM;
  73    default:
  74       return 0;
  75    }
  76 }
  77
  78 static int
  79 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
  80                     struct nv50_miptree *mt, unsigned level, unsigned layer,
  81                     enum pipe_format pformat)
  82 {
  83    struct nouveau_bo *bo = mt->base.bo;
  84    uint32_t width, height, depth;
  85    uint32_t format;
  86    uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
  87    uint32_t offset = mt->level[level].offset;
  88
  89    format = nv50_2d_format(pformat);
  90    if (!format) {
  91       NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
  92                   util_format_name(pformat));
  93       return 1;
  94    }
  95
  96    width = u_minify(mt->base.base.width0, level) << mt->ms_x;
  97    height = u_minify(mt->base.base.height0, level) << mt->ms_y;
  98    depth = u_minify(mt->base.base.depth0, level);
  99
 100    offset = mt->level[level].offset;
 101    if (!mt->layout_3d) {
 102       offset += mt->layer_stride * layer;
 103       depth = 1;
 104       layer = 0;
 105    } else
 106    if (!dst) {
 107       offset += nv50_mt_zslice_offset(mt, level, layer);
 108       layer = 0;
 109    }
 110
 111    if (!nouveau_bo_memtype(bo)) {
 112       BEGIN_NV04(push, SUBC_2D(mthd), 2);
 113       PUSH_DATA (push, format);
 114       PUSH_DATA (push, 1);
 115       BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
 116       PUSH_DATA (push, mt->level[level].pitch);
 117       PUSH_DATA (push, width);
 118       PUSH_DATA (push, height);
 119       PUSH_DATAh(push, bo->offset + offset);
 120       PUSH_DATA (push, bo->offset + offset);
 121    } else {
 122       BEGIN_NV04(push, SUBC_2D(mthd), 5);
 123       PUSH_DATA (push, format);
 124       PUSH_DATA (push, 0);
 125       PUSH_DATA (push, mt->level[level].tile_mode);
 126       PUSH_DATA (push, depth);
 127       PUSH_DATA (push, layer);
 128       BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
 129       PUSH_DATA (push, width);
 130       PUSH_DATA (push, height);
 131       PUSH_DATAh(push, bo->offset + offset);
 132       PUSH_DATA (push, bo->offset + offset);
 133    }
 134
 135 #if 0
 136    if (dst) {
 137       BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
 138       PUSH_DATA (push, 0);
 139       PUSH_DATA (push, 0);
 140       PUSH_DATA (push, width);
 141       PUSH_DATA (push, height);
 142    }
 143 #endif
 144    return 0;
 145 }
 146
 147 static int
 148 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
 149                         struct nv50_miptree *dst, unsigned dst_level,
 150                         unsigned dx, unsigned dy, unsigned dz,
 151                         struct nv50_miptree *src, unsigned src_level,
 152                         unsigned sx, unsigned sy, unsigned sz,
 153                         unsigned w, unsigned h)
 154 {
 155    const enum pipe_format dfmt = dst->base.base.format;
 156    const enum pipe_format sfmt = src->base.base.format;
 157    int ret;
 158
 159    if (!PUSH_SPACE(push, 2 * 16 + 32))
 160       return PIPE_ERROR;
 161
 162    ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt);
 163    if (ret)
 164       return ret;
 165
 166    ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt);
 167    if (ret)
 168       return ret;
 169
 170    BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
 171    PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
 172    BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
 173    PUSH_DATA (push, dx << dst->ms_x);
 174    PUSH_DATA (push, dy << dst->ms_y);
 175    PUSH_DATA (push, w << dst->ms_x);
 176    PUSH_DATA (push, h << dst->ms_y);
 177    BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
 178    PUSH_DATA (push, 0);
 179    PUSH_DATA (push, 1);
 180    PUSH_DATA (push, 0);
 181    PUSH_DATA (push, 1);
 182    BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
 183    PUSH_DATA (push, 0);
 184    PUSH_DATA (push, sx << src->ms_x);
 185    PUSH_DATA (push, 0);
 186    PUSH_DATA (push, sy << src->ms_y);
 187
 188    return 0;
 189 }
 190
 191 static void
 192 nv50_resource_copy_region(struct pipe_context *pipe,
 193                           struct pipe_resource *dst, unsigned dst_level,
 194                           unsigned dstx, unsigned dsty, unsigned dstz,
 195                           struct pipe_resource *src, unsigned src_level,
 196                           const struct pipe_box *src_box)
 197 {
 198    struct nv50_context *nv50 = nv50_context(pipe);
 199    int ret;
 200    boolean m2mf;
 201    unsigned dst_layer = dstz, src_layer = src_box->z;
 202
 203    /* Fallback for buffers. */
 204    if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 205       util_resource_copy_region(pipe, dst, dst_level, dstx, dsty, dstz,
 206                                 src, src_level, src_box);
 207       return;
 208    }
 209
 210    /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
 211    assert((src->nr_samples | 1) == (dst->nr_samples | 1));
 212
 213    m2mf = (src->format == dst->format) ||
 214       (util_format_get_blocksizebits(src->format) ==
 215        util_format_get_blocksizebits(dst->format));
 216
 217    nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 218
 219    if (m2mf) {
 220       struct nv50_m2mf_rect drect, srect;
 221       unsigned i;
 222       unsigned nx = util_format_get_nblocksx(src->format, src_box->width);
 223       unsigned ny = util_format_get_nblocksy(src->format, src_box->height);
 224
 225       nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
 226       nv50_m2mf_rect_setup(&srect, src, src_level,
 227                            src_box->x, src_box->y, src_box->z);
 228
 229       for (i = 0; i < src_box->depth; ++i) {
 230          nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
 231
 232          if (nv50_miptree(dst)->layout_3d)
 233             drect.z++;
 234          else
 235             drect.base += nv50_miptree(dst)->layer_stride;
 236
 237          if (nv50_miptree(src)->layout_3d)
 238             srect.z++;
 239          else
 240             srect.base += nv50_miptree(src)->layer_stride;
 241       }
 242       return;
 243    }
 244
 245    assert((src->format == dst->format) ||
 246           (nv50_2d_format_faithful(src->format) &&
 247            nv50_2d_format_faithful(dst->format)));
 248
 249    BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
 250    BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
 251    nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
 252    nouveau_pushbuf_validate(nv50->base.pushbuf);
 253
 254    for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
 255       ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
 256                                     nv50_miptree(dst), dst_level,
 257                                     dstx, dsty, dst_layer,
 258                                     nv50_miptree(src), src_level,
 259                                     src_box->x, src_box->y, src_layer,
 260                                     src_box->width, src_box->height);
 261       if (ret)
 262          break;
 263    }
 264    nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
 265 }
 266
 267 static void
 268 nv50_clear_render_target(struct pipe_context *pipe,
 269                          struct pipe_surface *dst,
 270                          const union pipe_color_union *color,
 271                          unsigned dstx, unsigned dsty,
 272                          unsigned width, unsigned height)
 273 {
 274    struct nv50_context *nv50 = nv50_context(pipe);
 275    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 276    struct nv50_miptree *mt = nv50_miptree(dst->texture);
 277    struct nv50_surface *sf = nv50_surface(dst);
 278    struct nouveau_bo *bo = mt->base.bo;
 279    unsigned z;
 280
 281    BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
 282    PUSH_DATAf(push, color->f[0]);
 283    PUSH_DATAf(push, color->f[1]);
 284    PUSH_DATAf(push, color->f[2]);
 285    PUSH_DATAf(push, color->f[3]);
 286
 287    if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
 288       return;
 289
 290    PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
 291
 292    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 293    PUSH_DATA (push, 1);
 294    BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
 295    PUSH_DATAh(push, bo->offset + sf->offset);
 296    PUSH_DATA (push, bo->offset + sf->offset);
 297    PUSH_DATA (push, nv50_format_table[dst->format].rt);
 298    PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
 299    PUSH_DATA (push, 0);
 300    BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
 301    if (nouveau_bo_memtype(bo))
 302       PUSH_DATA(push, sf->width);
 303    else
 304       PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
 305    PUSH_DATA (push, sf->height);
 306    BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
 307    PUSH_DATA (push, 1);
 308
 309    if (!nouveau_bo_memtype(bo)) {
 310       BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
 311       PUSH_DATA (push, 0);
 312    }
 313
 314    /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
 315
 316    BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
 317    PUSH_DATA (push, (width << 16) | dstx);
 318    PUSH_DATA (push, (height << 16) | dsty);
 319
 320    BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
 321    for (z = 0; z < sf->depth; ++z) {
 322       PUSH_DATA (push, 0x3c |
 323                  (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
 324    }
 325
 326    nv50->dirty |= NV50_NEW_FRAMEBUFFER;
 327 }
 328
 329 static void
 330 nv50_clear_depth_stencil(struct pipe_context *pipe,
 331                          struct pipe_surface *dst,
 332                          unsigned clear_flags,
 333                          double depth,
 334                          unsigned stencil,
 335                          unsigned dstx, unsigned dsty,
 336                          unsigned width, unsigned height)
 337 {
 338    struct nv50_context *nv50 = nv50_context(pipe);
 339    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 340    struct nv50_miptree *mt = nv50_miptree(dst->texture);
 341    struct nv50_surface *sf = nv50_surface(dst);
 342    struct nouveau_bo *bo = mt->base.bo;
 343    uint32_t mode = 0;
 344    unsigned z;
 345
 346    assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
 347
 348    if (clear_flags & PIPE_CLEAR_DEPTH) {
 349       BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
 350       PUSH_DATAf(push, depth);
 351       mode |= NV50_3D_CLEAR_BUFFERS_Z;
 352    }
 353
 354    if (clear_flags & PIPE_CLEAR_STENCIL) {
 355       BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
 356       PUSH_DATA (push, stencil & 0xff);
 357       mode |= NV50_3D_CLEAR_BUFFERS_S;
 358    }
 359
 360    if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
 361       return;
 362
 363    PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
 364
 365    BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
 366    PUSH_DATAh(push, bo->offset + sf->offset);
 367    PUSH_DATA (push, bo->offset + sf->offset);
 368    PUSH_DATA (push, nv50_format_table[dst->format].rt);
 369    PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
 370    PUSH_DATA (push, 0);
 371    BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
 372    PUSH_DATA (push, 1);
 373    BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
 374    PUSH_DATA (push, sf->width);
 375    PUSH_DATA (push, sf->height);
 376    PUSH_DATA (push, (1 << 16) | 1);
 377
 378    BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
 379    PUSH_DATA (push, (width << 16) | dstx);
 380    PUSH_DATA (push, (height << 16) | dsty);
 381
 382    BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
 383    for (z = 0; z < sf->depth; ++z) {
 384       PUSH_DATA (push, mode |
 385                  (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
 386    }
 387
 388    nv50->dirty |= NV50_NEW_FRAMEBUFFER;
 389 }
 390
 391 void
 392 nv50_clear(struct pipe_context *pipe, unsigned buffers,
 393            const union pipe_color_union *color,
 394            double depth, unsigned stencil)
 395 {
 396    struct nv50_context *nv50 = nv50_context(pipe);
 397    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 398    struct pipe_framebuffer_state *fb = &nv50->framebuffer;
 399    unsigned i;
 400    uint32_t mode = 0;
 401
 402    /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
 403    if (!nv50_state_validate(nv50, NV50_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
 404       return;
 405
 406    if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
 407       BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
 408       PUSH_DATAf(push, color->f[0]);
 409       PUSH_DATAf(push, color->f[1]);
 410       PUSH_DATAf(push, color->f[2]);
 411       PUSH_DATAf(push, color->f[3]);
 412       mode =
 413          NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
 414          NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
 415    }
 416
 417    if (buffers & PIPE_CLEAR_DEPTH) {
 418       BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
 419       PUSH_DATA (push, fui(depth));
 420       mode |= NV50_3D_CLEAR_BUFFERS_Z;
 421    }
 422
 423    if (buffers & PIPE_CLEAR_STENCIL) {
 424       BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
 425       PUSH_DATA (push, stencil & 0xff);
 426       mode |= NV50_3D_CLEAR_BUFFERS_S;
 427    }
 428
 429    BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
 430    PUSH_DATA (push, mode);
 431
 432    for (i = 1; i < fb->nr_cbufs; i++) {
 433       BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
 434       PUSH_DATA (push, (i << 6) | 0x3c);
 435    }
 436 }
 437
 438
 439 /* =============================== BLIT CODE ===================================
 440  */
 441
 442 struct nv50_blitter
 443 {
 444    struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
 445    struct nv50_program vp;
 446
 447    struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
 448
 449    pipe_mutex mutex;
 450 };
 451
 452 struct nv50_blitctx
 453 {
 454    struct nv50_context *nv50;
 455    struct nv50_program *fp;
 456    uint8_t mode;
 457    uint16_t color_mask;
 458    uint8_t filter;
 459    enum pipe_texture_target target;
 460    struct {
 461       struct pipe_framebuffer_state fb;
 462       struct nv50_program *vp;
 463       struct nv50_program *gp;
 464       struct nv50_program *fp;
 465       unsigned num_textures[3];
 466       unsigned num_samplers[3];
 467       struct pipe_sampler_view *texture[2];
 468       struct nv50_tsc_entry *sampler[2];
 469       uint32_t dirty;
 470    } saved;
 471 };
 472
 473 static void
 474 nv50_blitter_make_vp(struct nv50_blitter *blit)
 475 {
 476    static const uint32_t code[] =
 477    {
 478       0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
 479       0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
 480       0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
 481       0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
 482       0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
 483    };
 484
 485    blit->vp.type = PIPE_SHADER_VERTEX;
 486    blit->vp.translated = TRUE;
 487    blit->vp.code = (uint32_t *)code; /* const_cast */
 488    blit->vp.code_size = sizeof(code);
 489    blit->vp.max_gpr = 4;
 490    blit->vp.max_out = 5;
 491    blit->vp.out_nr = 2;
 492    blit->vp.out[0].mask = 0x3;
 493    blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
 494    blit->vp.out[1].hw = 2;
 495    blit->vp.out[1].mask = 0x7;
 496    blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
 497    blit->vp.out[1].si = 8;
 498    blit->vp.vp.attrs[0] = 0x73;
 499    blit->vp.vp.psiz = 0x40;
 500    blit->vp.vp.edgeflag = 0x40;
 501 }
 502
 503 void *
 504 nv50_blitter_make_fp(struct pipe_context *pipe,
 505                      unsigned mode,
 506                      enum pipe_texture_target ptarg)
 507 {
 508    struct ureg_program *ureg;
 509    struct ureg_src tc;
 510    struct ureg_dst out;
 511    struct ureg_dst data;
 512
 513    const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg);
 514
 515    boolean tex_rgbaz = FALSE;
 516    boolean tex_s = FALSE;
 517    boolean cvt_un8 = FALSE;
 518
 519    if (mode != NV50_BLIT_MODE_PASS &&
 520        mode != NV50_BLIT_MODE_Z24X8 &&
 521        mode != NV50_BLIT_MODE_X8Z24)
 522       tex_s = TRUE;
 523
 524    if (mode != NV50_BLIT_MODE_X24S8 &&
 525        mode != NV50_BLIT_MODE_S8X24 &&
 526        mode != NV50_BLIT_MODE_XS)
 527       tex_rgbaz = TRUE;
 528
 529    if (mode != NV50_BLIT_MODE_PASS &&
 530        mode != NV50_BLIT_MODE_ZS &&
 531        mode != NV50_BLIT_MODE_XS)
 532       cvt_un8 = TRUE;
 533
 534    ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
 535    if (!ureg)
 536       return NULL;
 537
 538    out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
 539    /* NOTE: use GENERIC[8] so we don't use the TEXCOORD slots on nvc0 */
 540    tc = ureg_DECL_fs_input(
 541       ureg, TGSI_SEMANTIC_GENERIC, 8, TGSI_INTERPOLATE_LINEAR);
 542
 543    data = ureg_DECL_temporary(ureg);
 544
 545    if (tex_s) {
 546       ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
 547                target, tc, ureg_DECL_sampler(ureg, 1));
 548       ureg_MOV(ureg, ureg_writemask(data, TGSI_WRITEMASK_Y),
 549                ureg_scalar(ureg_src(data), TGSI_SWIZZLE_X));
 550    }
 551    if (tex_rgbaz) {
 552       const unsigned mask = (mode == NV50_BLIT_MODE_PASS) ?
 553          TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
 554       ureg_TEX(ureg, ureg_writemask(data, mask),
 555                target, tc, ureg_DECL_sampler(ureg, 0));
 556    }
 557
 558    if (cvt_un8) {
 559       struct ureg_src mask;
 560       struct ureg_src scale;
 561       struct ureg_dst outz;
 562       struct ureg_dst outs;
 563       struct ureg_dst zdst3 = ureg_writemask(data, TGSI_WRITEMASK_XYZ);
 564       struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
 565       struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y);
 566       struct ureg_src zsrc3 = ureg_src(data);
 567       struct ureg_src zsrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_X);
 568       struct ureg_src ssrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_Y);
 569       struct ureg_src zshuf;
 570
 571       mask = ureg_imm3u(ureg, 0x0000ff, 0x00ff00, 0xff0000);
 572       scale = ureg_imm4f(ureg,
 573                          1.0f / 0x0000ff, 1.0f / 0x00ff00, 1.0f / 0xff0000,
 574                          (1 << 24) - 1);
 575
 576       if (mode == NV50_BLIT_MODE_Z24S8 ||
 577           mode == NV50_BLIT_MODE_X24S8 ||
 578           mode == NV50_BLIT_MODE_Z24X8) {
 579          outz = ureg_writemask(out, TGSI_WRITEMASK_XYZ);
 580          outs = ureg_writemask(out, TGSI_WRITEMASK_W);
 581          zshuf = ureg_src(data);
 582       } else {
 583          outz = ureg_writemask(out, TGSI_WRITEMASK_YZW);
 584          outs = ureg_writemask(out, TGSI_WRITEMASK_X);
 585          zshuf = ureg_swizzle(zsrc3, TGSI_SWIZZLE_W,
 586                               TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z);
 587       }
 588
 589       if (tex_s) {
 590          ureg_I2F(ureg, sdst, ssrc);
 591          ureg_MUL(ureg, outs, ssrc, ureg_scalar(scale, TGSI_SWIZZLE_X));
 592       }
 593
 594       if (tex_rgbaz) {
 595          ureg_MUL(ureg, zdst, zsrc, ureg_scalar(scale, TGSI_SWIZZLE_W));
 596          ureg_F2I(ureg, zdst, zsrc);
 597          ureg_AND(ureg, zdst3, zsrc, mask);
 598          ureg_I2F(ureg, zdst3, zsrc3);
 599          ureg_MUL(ureg, zdst3, zsrc3, scale);
 600          ureg_MOV(ureg, outz, zshuf);
 601       }
 602    } else {
 603       unsigned mask = TGSI_WRITEMASK_XYZW;
 604
 605       if (mode != NV50_BLIT_MODE_PASS) {
 606          mask &= ~TGSI_WRITEMASK_ZW;
 607          if (!tex_s)
 608             mask = TGSI_WRITEMASK_X;
 609          if (!tex_rgbaz)
 610             mask = TGSI_WRITEMASK_Y;
 611       }
 612       ureg_MOV(ureg, ureg_writemask(out, mask), ureg_src(data));
 613    }
 614    ureg_END(ureg);
 615
 616    return ureg_create_shader_and_destroy(ureg, pipe);
 617 }
 618
 619 static void
 620 nv50_blitter_make_sampler(struct nv50_blitter *blit)
 621 {
 622    /* clamp to edge, min/max lod = 0, nearest filtering */
 623
 624    blit->sampler[0].id = -1;
 625
 626    blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
 627       (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
 628       (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
 629       (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
 630    blit->sampler[0].tsc[1] =
 631       NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
 632
 633    /* clamp to edge, min/max lod = 0, bilinear filtering */
 634
 635    blit->sampler[1].id = -1;
 636
 637    blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
 638    blit->sampler[1].tsc[1] =
 639       NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
 640 }
 641
 642 unsigned
 643 nv50_blit_select_mode(const struct pipe_blit_info *info)
 644 {
 645    const unsigned mask = info->mask;
 646
 647    switch (info->dst.resource->format) {
 648    case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 649    case PIPE_FORMAT_Z24X8_UNORM:
 650       switch (mask & PIPE_MASK_ZS) {
 651       case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
 652       case PIPE_MASK_Z:  return NV50_BLIT_MODE_Z24X8;
 653       default:
 654          return NV50_BLIT_MODE_X24S8;
 655       }
 656    case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 657       switch (mask & PIPE_MASK_ZS) {
 658       case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
 659       case PIPE_MASK_Z:  return NV50_BLIT_MODE_X8Z24;
 660       default:
 661          return NV50_BLIT_MODE_S8X24;
 662       }
 663    case PIPE_FORMAT_Z32_FLOAT:
 664    case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 665       switch (mask & PIPE_MASK_ZS) {
 666       case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
 667       case PIPE_MASK_Z:  return NV50_BLIT_MODE_PASS;
 668       default:
 669          return NV50_BLIT_MODE_XS;
 670       }
 671    default:
 672       return NV50_BLIT_MODE_PASS;
 673    }
 674 }
 675
 676 static void
 677 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
 678 {
 679    struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
 680
 681    const enum pipe_texture_target ptarg =
 682       nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
 683
 684    const unsigned targ = nv50_blit_texture_type(ptarg);
 685    const unsigned mode = ctx->mode;
 686
 687    if (!blitter->fp[targ][mode]) {
 688       pipe_mutex_lock(blitter->mutex);
 689       if (!blitter->fp[targ][mode])
 690          blitter->fp[targ][mode] =
 691             nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
 692       pipe_mutex_unlock(blitter->mutex);
 693    }
 694    ctx->fp = blitter->fp[targ][mode];
 695 }
 696
 697 static void
 698 nv50_blit_set_dst(struct nv50_blitctx *ctx,
 699                   struct pipe_resource *res, unsigned level, unsigned layer,
 700                   enum pipe_format format)
 701 {
 702    struct nv50_context *nv50 = ctx->nv50;
 703    struct pipe_context *pipe = &nv50->base.pipe;
 704    struct pipe_surface templ;
 705
 706    if (util_format_is_depth_or_stencil(format))
 707       templ.format = nv50_blit_zeta_to_colour_format(format);
 708    else
 709       templ.format = format;
 710
 711    templ.u.tex.level = level;
 712    templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
 713
 714    if (layer == -1) {
 715       templ.u.tex.first_layer = 0;
 716       templ.u.tex.last_layer =
 717          (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
 718    }
 719
 720    nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
 721    nv50->framebuffer.nr_cbufs = 1;
 722    nv50->framebuffer.zsbuf = NULL;
 723    nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
 724    nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
 725 }
 726
 727 static void
 728 nv50_blit_set_src(struct nv50_blitctx *blit,
 729                   struct pipe_resource *res, unsigned level, unsigned layer,
 730                   enum pipe_format format, const uint8_t filter)
 731 {
 732    struct nv50_context *nv50 = blit->nv50;
 733    struct pipe_context *pipe = &nv50->base.pipe;
 734    struct pipe_sampler_view templ;
 735    uint32_t flags;
 736    enum pipe_texture_target target;
 737
 738    target = nv50_blit_reinterpret_pipe_texture_target(res->target);
 739
 740    templ.format = format;
 741    templ.u.tex.first_level = templ.u.tex.last_level = level;
 742    templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
 743    templ.swizzle_r = PIPE_SWIZZLE_RED;
 744    templ.swizzle_g = PIPE_SWIZZLE_GREEN;
 745    templ.swizzle_b = PIPE_SWIZZLE_BLUE;
 746    templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
 747
 748    if (layer == -1) {
 749       templ.u.tex.first_layer = 0;
 750       templ.u.tex.last_layer =
 751          (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
 752    }
 753
 754    flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
 755    if (filter && res->nr_samples == 8)
 756       flags |= NV50_TEXVIEW_FILTER_MSAA8;
 757
 758    nv50->textures[2][0] = nv50_create_texture_view(
 759       pipe, res, &templ, flags, target);
 760    nv50->textures[2][1] = NULL;
 761
 762    nv50->num_textures[0] = nv50->num_textures[1] = 0;
 763    nv50->num_textures[2] = 1;
 764
 765    templ.format = nv50_zs_to_s_format(format);
 766    if (templ.format != res->format) {
 767       nv50->textures[2][1] = nv50_create_texture_view(
 768          pipe, res, &templ, flags, target);
 769       nv50->num_textures[2] = 2;
 770    }
 771 }
 772
 773 static void
 774 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
 775 {
 776    struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
 777
 778    if (blit->nv50->cond_query) {
 779       BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 780       PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 781    }
 782
 783    /* blend state */
 784    BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
 785    PUSH_DATA (push, blit->color_mask);
 786    BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
 787    PUSH_DATA (push, 0);
 788    BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
 789    PUSH_DATA (push, 0);
 790
 791    /* rasterizer state */
 792 #ifndef NV50_SCISSORS_CLIPPING
 793    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
 794    PUSH_DATA (push, 1);
 795 #endif
 796    BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
 797    PUSH_DATA (push, 0);
 798    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 799    PUSH_DATA (push, 0);
 800    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 801    PUSH_DATA (push, 0);
 802    BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
 803    PUSH_DATA (push, 0xffff);
 804    PUSH_DATA (push, 0xffff);
 805    PUSH_DATA (push, 0xffff);
 806    PUSH_DATA (push, 0xffff);
 807    BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
 808    PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
 809    PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
 810    PUSH_DATA (push, 0);
 811    BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
 812    PUSH_DATA (push, 0);
 813    BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
 814    PUSH_DATA (push, 0);
 815    BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
 816    PUSH_DATA (push, 0);
 817
 818    /* zsa state */
 819    BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
 820    PUSH_DATA (push, 0);
 821    BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
 822    PUSH_DATA (push, 0);
 823    BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
 824    PUSH_DATA (push, 0);
 825 }
 826
 827 static void
 828 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx)
 829 {
 830    struct nv50_context *nv50 = ctx->nv50;
 831    struct nv50_blitter *blitter = nv50->screen->blitter;
 832    int s;
 833
 834    ctx->saved.fb.width = nv50->framebuffer.width;
 835    ctx->saved.fb.height = nv50->framebuffer.height;
 836    ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
 837    ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
 838    ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
 839
 840    ctx->saved.vp = nv50->vertprog;
 841    ctx->saved.gp = nv50->gmtyprog;
 842    ctx->saved.fp = nv50->fragprog;
 843
 844    nv50->vertprog = &blitter->vp;
 845    nv50->gmtyprog = NULL;
 846    nv50->fragprog = ctx->fp;
 847
 848    for (s = 0; s < 3; ++s) {
 849       ctx->saved.num_textures[s] = nv50->num_textures[s];
 850       ctx->saved.num_samplers[s] = nv50->num_samplers[s];
 851    }
 852    ctx->saved.texture[0] = nv50->textures[2][0];
 853    ctx->saved.texture[1] = nv50->textures[2][1];
 854    ctx->saved.sampler[0] = nv50->samplers[2][0];
 855    ctx->saved.sampler[1] = nv50->samplers[2][1];
 856
 857    nv50->samplers[2][0] = &blitter->sampler[ctx->filter];
 858    nv50->samplers[2][1] = &blitter->sampler[ctx->filter];
 859
 860    nv50->num_samplers[0] = nv50->num_samplers[1] = 0;
 861    nv50->num_samplers[2] = 2;
 862
 863    ctx->saved.dirty = nv50->dirty;
 864
 865    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
 866    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
 867
 868    nv50->dirty =
 869       NV50_NEW_FRAMEBUFFER |
 870       NV50_NEW_VERTPROG | NV50_NEW_FRAGPROG | NV50_NEW_GMTYPROG |
 871       NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS;
 872 }
 873
 874 static void
 875 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
 876 {
 877    struct nv50_context *nv50 = blit->nv50;
 878    int s;
 879
 880    pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
 881
 882    nv50->framebuffer.width = blit->saved.fb.width;
 883    nv50->framebuffer.height = blit->saved.fb.height;
 884    nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
 885    nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
 886    nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
 887
 888    nv50->vertprog = blit->saved.vp;
 889    nv50->gmtyprog = blit->saved.gp;
 890    nv50->fragprog = blit->saved.fp;
 891
 892    pipe_sampler_view_reference(&nv50->textures[2][0], NULL);
 893    pipe_sampler_view_reference(&nv50->textures[2][1], NULL);
 894
 895    for (s = 0; s < 3; ++s) {
 896       nv50->num_textures[s] = blit->saved.num_textures[s];
 897       nv50->num_samplers[s] = blit->saved.num_samplers[s];
 898    }
 899    nv50->textures[2][0] = blit->saved.texture[0];
 900    nv50->textures[2][1] = blit->saved.texture[1];
 901    nv50->samplers[2][0] = blit->saved.sampler[0];
 902    nv50->samplers[2][1] = blit->saved.sampler[1];
 903
 904    if (nv50->cond_query)
 905       nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
 906                                        nv50->cond_mode);
 907
 908    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
 909    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
 910
 911    nv50->dirty = blit->saved.dirty |
 912       (NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR | NV50_NEW_SAMPLE_MASK |
 913        NV50_NEW_RASTERIZER | NV50_NEW_ZSA | NV50_NEW_BLEND |
 914        NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS |
 915        NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG | NV50_NEW_FRAGPROG);
 916 }
 917
 918
 919 static void
 920 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
 921 {
 922    struct nv50_blitctx *blit = nv50->blit;
 923    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 924    struct pipe_resource *src = info->src.resource;
 925    struct pipe_resource *dst = info->dst.resource;
 926    int32_t minx, maxx, miny, maxy;
 927    int32_t i;
 928    float x0, x1, y0, y1, z;
 929    float dz;
 930    float x_range, y_range;
 931
 932    blit->mode = nv50_blit_select_mode(info);
 933    blit->color_mask = nv50_blit_derive_color_mask(info);
 934    blit->filter = nv50_blit_get_filter(info);
 935
 936    nv50_blit_select_fp(blit, info);
 937    nv50_blitctx_pre_blit(blit);
 938
 939    nv50_blit_set_dst(blit, dst, info->dst.level,  0, info->dst.format);
 940    nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
 941                      blit->filter);
 942
 943    nv50_blitctx_prepare_state(blit);
 944
 945    nv50_state_validate(nv50, ~0, 36);
 946
 947    x_range = (float)info->src.box.width / (float)info->dst.box.width;
 948    y_range = (float)info->src.box.height / (float)info->dst.box.height;
 949
 950    x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
 951    y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
 952
 953    x1 = x0 + 16384.0f * x_range;
 954    y1 = y0 + 16384.0f * y_range;
 955
 956    x0 *= (float)(1 << nv50_miptree(src)->ms_x);
 957    x1 *= (float)(1 << nv50_miptree(src)->ms_x);
 958    y0 *= (float)(1 << nv50_miptree(src)->ms_y);
 959    y1 *= (float)(1 << nv50_miptree(src)->ms_y);
 960
 961    if (src->last_level > 0) {
 962       /* If there are mip maps, GPU always assumes normalized coordinates. */
 963       const unsigned l = info->src.level;
 964       const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
 965       const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
 966       x0 /= fh;
 967       x1 /= fh;
 968       y0 /= fv;
 969       y1 /= fv;
 970    }
 971
 972    /* XXX: multiply by 6 for cube arrays ? */
 973    dz = (float)info->src.box.depth / (float)info->dst.box.depth;
 974    z = (float)info->src.box.z;
 975    if (nv50_miptree(src)->layout_3d)
 976       z += 0.5f * dz;
 977
 978    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 979    PUSH_DATA (push, 0);
 980
 981    /* Draw a large triangle in screen coordinates covering the whole
 982     * render target, with scissors defining the destination region.
 983     * The vertex is supplied with non-normalized texture coordinates
 984     * arranged in a way to yield the desired offset and scale.
 985     */
 986
 987    minx = info->dst.box.x;
 988    maxx = info->dst.box.x + info->dst.box.width;
 989    miny = info->dst.box.y;
 990    maxy = info->dst.box.y + info->dst.box.height;
 991    if (info->scissor_enable) {
 992       minx = MAX2(minx, info->scissor.minx);
 993       maxx = MIN2(maxx, info->scissor.maxx);
 994       miny = MAX2(miny, info->scissor.miny);
 995       maxy = MIN2(maxy, info->scissor.maxy);
 996    }
 997    BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
 998    PUSH_DATA (push, (maxx << 16) | minx);
 999    PUSH_DATA (push, (maxy << 16) | miny);
1000
1001    for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1002       if (info->dst.box.z + i) {
1003          BEGIN_NV04(push, NV50_3D(LAYER), 1);
1004          PUSH_DATA (push, info->dst.box.z + i);
1005       }
1006       PUSH_SPACE(push, 32);
1007       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1008       PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1009       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1010       PUSH_DATAf(push, x0);
1011       PUSH_DATAf(push, y0);
1012       PUSH_DATAf(push, z);
1013       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1014       PUSH_DATAf(push, 0.0f);
1015       PUSH_DATAf(push, 0.0f);
1016       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1017       PUSH_DATAf(push, x1);
1018       PUSH_DATAf(push, y0);
1019       PUSH_DATAf(push, z);
1020       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1021       PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_x);
1022       PUSH_DATAf(push, 0.0f);
1023       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1024       PUSH_DATAf(push, x0);
1025       PUSH_DATAf(push, y1);
1026       PUSH_DATAf(push, z);
1027       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1028       PUSH_DATAf(push, 0.0f);
1029       PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_y);
1030       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1031       PUSH_DATA (push, 0);
1032    }
1033    if (info->dst.box.z + info->dst.box.depth - 1) {
1034       BEGIN_NV04(push, NV50_3D(LAYER), 1);
1035       PUSH_DATA (push, 0);
1036    }
1037
1038    /* re-enable normally constant state */
1039
1040    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1041    PUSH_DATA (push, 1);
1042
1043    nv50_blitctx_post_blit(blit);
1044 }
1045
1046 static void
1047 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1048 {
1049    struct nouveau_pushbuf *push = nv50->base.pushbuf;
1050    struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1051    struct nv50_miptree *src = nv50_miptree(info->src.resource);
1052    const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1053    const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1054    const int32_t dz = info->dst.box.z;
1055    const int32_t sz = info->src.box.z;
1056    uint32_t dstw, dsth;
1057    int32_t dstx, dsty;
1058    int64_t srcx, srcy;
1059    int64_t du_dx, dv_dy;
1060    int i;
1061    uint32_t mode;
1062    const uint32_t mask = nv50_blit_eng2d_get_mask(info);
1063
1064    mode = nv50_blit_get_filter(info) ?
1065       NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1066       NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1067    mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1068       NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1069
1070    du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1071    dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1072
1073    nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format);
1074    nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format);
1075
1076    if (info->scissor_enable) {
1077       BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1078       PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1079       PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1080       PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1081       PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1082       PUSH_DATA (push, 1); /* enable */
1083    }
1084
1085    if (mask != 0xffffffff) {
1086       BEGIN_NV04(push, NV50_2D(ROP), 1);
1087       PUSH_DATA (push, 0xca); /* DPSDxax */
1088       BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1089       PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_32BPP);
1090       BEGIN_NV04(push, NV50_2D(PATTERN_COLOR(0)), 4);
1091       PUSH_DATA (push, 0x00000000);
1092       PUSH_DATA (push, mask);
1093       PUSH_DATA (push, 0xffffffff);
1094       PUSH_DATA (push, 0xffffffff);
1095       BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1096       PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1097    }
1098
1099    if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1100       /* ms_x is always >= ms_y */
1101       du_dx <<= src->ms_x - dst->ms_x;
1102       dv_dy <<= src->ms_y - dst->ms_y;
1103    } else {
1104       du_dx >>= dst->ms_x - src->ms_x;
1105       dv_dy >>= dst->ms_y - src->ms_y;
1106    }
1107
1108    srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1109    srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1110
1111    if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1112       /* center src coorinates for proper MS resolve filtering */
1113       srcx += (int64_t)src->ms_x << 32;
1114       srcy += (int64_t)src->ms_y << 32;
1115    }
1116
1117    dstx = info->dst.box.x << dst->ms_x;
1118    dsty = info->dst.box.y << dst->ms_y;
1119
1120    dstw = info->dst.box.width << dst->ms_x;
1121    dsth = info->dst.box.height << dst->ms_y;
1122
1123    if (dstx < 0) {
1124       dstw += dstx;
1125       srcx -= du_dx * dstx;
1126       dstx = 0;
1127    }
1128    if (dsty < 0) {
1129       dsth += dsty;
1130       srcy -= dv_dy * dsty;
1131       dsty = 0;
1132    }
1133
1134    BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1135    PUSH_DATA (push, mode);
1136    BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1137    PUSH_DATA (push, dstx);
1138    PUSH_DATA (push, dsty);
1139    PUSH_DATA (push, dstw);
1140    PUSH_DATA (push, dsth);
1141    BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1142    PUSH_DATA (push, du_dx);
1143    PUSH_DATA (push, du_dx >> 32);
1144    PUSH_DATA (push, dv_dy);
1145    PUSH_DATA (push, dv_dy >> 32);
1146
1147    BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1148    BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1149    nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1150    if (nouveau_pushbuf_validate(nv50->base.pushbuf))
1151       return;
1152
1153    for (i = 0; i < info->dst.box.depth; ++i) {
1154       if (i > 0) {
1155          /* no scaling in z-direction possible for eng2d blits */
1156          if (dst->layout_3d) {
1157             BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1158             PUSH_DATA (push, info->dst.box.z + i);
1159          } else {
1160             const unsigned z = info->dst.box.z + i;
1161             BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1162             PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
1163             PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
1164          }
1165          if (src->layout_3d) {
1166             /* not possible because of depth tiling */
1167             assert(0);
1168          } else {
1169             const unsigned z = info->src.box.z + i;
1170             BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1171             PUSH_DATAh(push, src->base.address + z * src->layer_stride);
1172             PUSH_DATA (push, src->base.address + z * src->layer_stride);
1173          }
1174          BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1175          PUSH_DATA (push, srcy >> 32);
1176       } else {
1177          BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1178          PUSH_DATA (push, srcx);
1179          PUSH_DATA (push, srcx >> 32);
1180          PUSH_DATA (push, srcy);
1181          PUSH_DATA (push, srcy >> 32);
1182       }
1183    }
1184    nv50_bufctx_fence(nv50->bufctx, FALSE);
1185
1186    nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1187
1188    if (info->scissor_enable) {
1189       BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1190       PUSH_DATA (push, 0);
1191    }
1192    if (mask != 0xffffffff) {
1193       BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1194       PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1195    }
1196 }
1197
1198 static void
1199 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1200 {
1201    struct nv50_context *nv50 = nv50_context(pipe);
1202    boolean eng3d = FALSE;
1203
1204    if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1205       if (!(info->mask & PIPE_MASK_ZS))
1206          return;
1207       if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1208           info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1209          eng3d = TRUE;
1210       if (info->filter != PIPE_TEX_FILTER_NEAREST)
1211          eng3d = TRUE;
1212    } else {
1213       if (!(info->mask & PIPE_MASK_RGBA))
1214          return;
1215       if (info->mask != PIPE_MASK_RGBA)
1216          eng3d = TRUE;
1217    }
1218
1219    if (nv50_miptree(info->src.resource)->layout_3d) {
1220       eng3d = TRUE;
1221    } else
1222    if (info->src.box.depth != info->dst.box.depth) {
1223       eng3d = TRUE;
1224       debug_printf("blit: cannot filter array or cube textures in z direction");
1225    }
1226
1227    if (!eng3d && info->dst.format != info->src.format)
1228       if (!nv50_2d_format_faithful(info->dst.format) ||
1229           !nv50_2d_format_faithful(info->src.format))
1230          eng3d = TRUE;
1231
1232    if (info->src.resource->nr_samples == 8 &&
1233        info->dst.resource->nr_samples <= 1)
1234       eng3d = TRUE;
1235
1236    /* FIXME: can't make this work with eng2d anymore */
1237    if (info->src.resource->nr_samples > 1 ||
1238        info->dst.resource->nr_samples > 1)
1239       eng3d = TRUE;
1240
1241    /* FIXME: find correct src coordinate adjustments */
1242    if ((info->src.box.width !=  info->dst.box.width &&
1243         info->src.box.width != -info->dst.box.width) ||
1244        (info->src.box.height !=  info->dst.box.height &&
1245         info->src.box.height != -info->dst.box.height))
1246       eng3d = TRUE;
1247
1248    if (!eng3d)
1249       nv50_blit_eng2d(nv50, info);
1250    else
1251       nv50_blit_3d(nv50, info);
1252 }
1253
1254 boolean
1255 nv50_blitter_create(struct nv50_screen *screen)
1256 {
1257    screen->blitter = CALLOC_STRUCT(nv50_blitter);
1258    if (!screen->blitter) {
1259       NOUVEAU_ERR("failed to allocate blitter struct\n");
1260       return FALSE;
1261    }
1262
1263    pipe_mutex_init(screen->blitter->mutex);
1264
1265    nv50_blitter_make_vp(screen->blitter);
1266    nv50_blitter_make_sampler(screen->blitter);
1267
1268    return TRUE;
1269 }
1270
1271 void
1272 nv50_blitter_destroy(struct nv50_screen *screen)
1273 {
1274    struct nv50_blitter *blitter = screen->blitter;
1275    unsigned i, m;
1276
1277    for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1278       for (m = 0; m < NV50_BLIT_MODES; ++m) {
1279          struct nv50_program *prog = blitter->fp[i][m];
1280          if (prog) {
1281             nv50_program_destroy(NULL, prog);
1282             FREE((void *)prog->pipe.tokens);
1283             FREE(prog);
1284          }
1285       }
1286    }
1287
1288    FREE(blitter);
1289 }
1290
1291 boolean
1292 nv50_blitctx_create(struct nv50_context *nv50)
1293 {
1294    nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1295    if (!nv50->blit) {
1296       NOUVEAU_ERR("failed to allocate blit context\n");
1297       return FALSE;
1298    }
1299
1300    nv50->blit->nv50 = nv50;
1301
1302    return TRUE;
1303 }
1304
1305 void
1306 nv50_init_surface_functions(struct nv50_context *nv50)
1307 {
1308    struct pipe_context *pipe = &nv50->base.pipe;
1309
1310    pipe->resource_copy_region = nv50_resource_copy_region;
1311    pipe->blit = nv50_blit;
1312    pipe->clear_render_target = nv50_clear_render_target;
1313    pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1314 }
1315
1316