src/gallium/drivers/nv50/nv50_surface.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #define __NOUVEAU_PUSH_H__
  24 #include <stdint.h>
  25 #include "nouveau/nouveau_pushbuf.h"
  26 #include "nv50_context.h"
  27 #include "nv50_resource.h"
  28 #include "pipe/p_defines.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_pack_color.h"
  31
  32 #include "util/u_format.h"
  33
  34 /* return TRUE for formats that can be converted among each other by NV50_2D */
  35 static INLINE boolean
  36 nv50_2d_format_faithful(enum pipe_format format)
  37 {
  38         switch (format) {
  39         case PIPE_FORMAT_B8G8R8A8_UNORM:
  40         case PIPE_FORMAT_B8G8R8X8_UNORM:
  41         case PIPE_FORMAT_B8G8R8A8_SRGB:
  42         case PIPE_FORMAT_B8G8R8X8_SRGB:
  43         case PIPE_FORMAT_B5G6R5_UNORM:
  44         case PIPE_FORMAT_B5G5R5A1_UNORM:
  45         case PIPE_FORMAT_B10G10R10A2_UNORM:
  46         case PIPE_FORMAT_R8_UNORM:
  47         case PIPE_FORMAT_R32G32B32A32_FLOAT:
  48         case PIPE_FORMAT_R32G32B32_FLOAT:
  49                 return TRUE;
  50         default:
  51                 return FALSE;
  52         }
  53 }
  54
  55 static INLINE uint8_t
  56 nv50_2d_format(enum pipe_format format)
  57 {
  58         uint8_t id = nv50_format_table[format].rt;
  59
  60         /* Hardware values for color formats range from 0xc0 to 0xff,
  61          * but the 2D engine doesn't support all of them.
  62          */
  63         if ((id >= 0xc0) && (0xff0843e080608409ULL & (1ULL << (id - 0xc0))))
  64                 return id;
  65
  66         switch (util_format_get_blocksize(format)) {
  67         case 1:
  68                 return NV50_2D_DST_FORMAT_R8_UNORM;
  69         case 2:
  70                 return NV50_2D_DST_FORMAT_R16_UNORM;
  71         case 4:
  72                 return NV50_2D_DST_FORMAT_A8R8G8B8_UNORM;
  73         default:
  74                 return 0;
  75         }
  76 }
  77
  78 static int
  79 nv50_surface_set(struct nv50_screen *screen, struct pipe_surface *ps, int dst)
  80 {
  81         struct nv50_miptree *mt = nv50_miptree(ps->texture);
  82         struct nouveau_channel *chan = screen->eng2d->channel;
  83         struct nouveau_grobj *eng2d = screen->eng2d;
  84         struct nouveau_bo *bo = nv50_miptree(ps->texture)->base.bo;
  85         int format, mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
  86         int flags = NOUVEAU_BO_VRAM | (dst ? NOUVEAU_BO_WR : NOUVEAU_BO_RD);
  87
  88         format = nv50_2d_format(ps->format);
  89         if (!format) {
  90                 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
  91                             util_format_name(ps->format));
  92                 return 1;
  93         }
  94
  95         if (!nouveau_bo_tile_layout(bo)) {
  96                 BEGIN_RING(chan, eng2d, mthd, 2);
  97                 OUT_RING  (chan, format);
  98                 OUT_RING  (chan, 1);
  99                 BEGIN_RING(chan, eng2d, mthd + 0x14, 5);
 100                 OUT_RING  (chan, mt->level[ps->u.tex.level].pitch);
 101                 OUT_RING  (chan, ps->width);
 102                 OUT_RING  (chan, ps->height);
 103                 OUT_RELOCh(chan, bo, ((struct nv50_surface *)ps)->offset, flags);
 104                 OUT_RELOCl(chan, bo, ((struct nv50_surface *)ps)->offset, flags);
 105         } else {
 106                 BEGIN_RING(chan, eng2d, mthd, 5);
 107                 OUT_RING  (chan, format);
 108                 OUT_RING  (chan, 0);
 109                 OUT_RING  (chan, mt->level[ps->u.tex.level].tile_mode << 4);
 110                 OUT_RING  (chan, 1);
 111                 OUT_RING  (chan, 0);
 112                 BEGIN_RING(chan, eng2d, mthd + 0x18, 4);
 113                 OUT_RING  (chan, ps->width);
 114                 OUT_RING  (chan, ps->height);
 115                 OUT_RELOCh(chan, bo, ((struct nv50_surface *)ps)->offset, flags);
 116                 OUT_RELOCl(chan, bo, ((struct nv50_surface *)ps)->offset, flags);
 117         }
 118
 119 #if 0
 120         if (dst) {
 121                 BEGIN_RING(chan, eng2d, NV50_2D_CLIP_X, 4);
 122                 OUT_RING  (chan, 0);
 123                 OUT_RING  (chan, 0);
 124                 OUT_RING  (chan, surf->width);
 125                 OUT_RING  (chan, surf->height);
 126         }
 127 #endif
 128
 129         return 0;
 130 }
 131
 132 int
 133 nv50_surface_do_copy(struct nv50_screen *screen, struct pipe_surface *dst,
 134                      int dx, int dy, struct pipe_surface *src, int sx, int sy,
 135                      int w, int h)
 136 {
 137         struct nouveau_channel *chan = screen->eng2d->channel;
 138         struct nouveau_grobj *eng2d = screen->eng2d;
 139         int ret;
 140
 141         ret = MARK_RING(chan, 2*16 + 32, 4);
 142         if (ret)
 143                 return ret;
 144
 145         ret = nv50_surface_set(screen, dst, 1);
 146         if (ret)
 147                 return ret;
 148
 149         ret = nv50_surface_set(screen, src, 0);
 150         if (ret)
 151                 return ret;
 152
 153         BEGIN_RING(chan, eng2d, 0x088c, 1);
 154         OUT_RING  (chan, 0);
 155         BEGIN_RING(chan, eng2d, NV50_2D_BLIT_DST_X, 4);
 156         OUT_RING  (chan, dx);
 157         OUT_RING  (chan, dy);
 158         OUT_RING  (chan, w);
 159         OUT_RING  (chan, h);
 160         BEGIN_RING(chan, eng2d, 0x08c0, 4);
 161         OUT_RING  (chan, 0);
 162         OUT_RING  (chan, 1);
 163         OUT_RING  (chan, 0);
 164         OUT_RING  (chan, 1);
 165         BEGIN_RING(chan, eng2d, 0x08d0, 4);
 166         OUT_RING  (chan, 0);
 167         OUT_RING  (chan, sx);
 168         OUT_RING  (chan, 0);
 169         OUT_RING  (chan, sy);
 170
 171         return 0;
 172 }
 173
 174 static void
 175 nv50_surface_copy(struct pipe_context *pipe,
 176                   struct pipe_resource *dest, unsigned dst_level,
 177                   unsigned destx, unsigned desty, unsigned destz,
 178                   struct pipe_resource *src, unsigned src_level,
 179                   const struct pipe_box *src_box)
 180 {
 181         struct nv50_context *nv50 = nv50_context(pipe);
 182         struct nv50_screen *screen = nv50->screen;
 183         struct pipe_surface *ps_dst, *ps_src, surf_tmpl;
 184
 185
 186         assert((src->format == dest->format) ||
 187                (nv50_2d_format_faithful(src->format) &&
 188                 nv50_2d_format_faithful(dest->format)));
 189         assert(src_box->depth == 1);
 190
 191         memset(&surf_tmpl, 0, sizeof(surf_tmpl));
 192         surf_tmpl.format = src->format;
 193         surf_tmpl.usage = 0; /* no bind flag - not a surface */
 194         surf_tmpl.u.tex.level = src_level;
 195         surf_tmpl.u.tex.first_layer = src_box->z;
 196         surf_tmpl.u.tex.last_layer = src_box->z;
 197         /* XXX really need surfaces here? */
 198         ps_src = nv50_miptree_surface_new(pipe, src, &surf_tmpl);
 199         surf_tmpl.format = dest->format;
 200         surf_tmpl.usage = 0; /* no bind flag - not a surface */
 201         surf_tmpl.u.tex.level = dst_level;
 202         surf_tmpl.u.tex.first_layer = destz;
 203         surf_tmpl.u.tex.last_layer = destz;
 204         ps_dst = nv50_miptree_surface_new(pipe, dest, &surf_tmpl);
 205
 206         nv50_surface_do_copy(screen, ps_dst, destx, desty, ps_src, src_box->x,
 207                              src_box->y, src_box->width, src_box->height);
 208
 209         nv50_miptree_surface_del(pipe, ps_src);
 210         nv50_miptree_surface_del(pipe, ps_dst);
 211 }
 212
 213 static void
 214 nv50_clear_render_target(struct pipe_context *pipe,
 215                          struct pipe_surface *dst,
 216                          const float *rgba,
 217                          unsigned dstx, unsigned dsty,
 218                          unsigned width, unsigned height)
 219 {
 220         struct nv50_context *nv50 = nv50_context(pipe);
 221         struct nv50_screen *screen = nv50->screen;
 222         struct nouveau_channel *chan = screen->base.channel;
 223         struct nouveau_grobj *tesla = screen->tesla;
 224         struct nv50_miptree *mt = nv50_miptree(dst->texture);
 225         struct nouveau_bo *bo = mt->base.bo;
 226
 227         BEGIN_RING(chan, tesla, NV50TCL_CLEAR_COLOR(0), 4);
 228         OUT_RINGf (chan, rgba[0]);
 229         OUT_RINGf (chan, rgba[1]);
 230         OUT_RINGf (chan, rgba[2]);
 231         OUT_RINGf (chan, rgba[3]);
 232
 233         if (MARK_RING(chan, 18, 2))
 234                 return;
 235
 236         BEGIN_RING(chan, tesla, NV50TCL_RT_CONTROL, 1);
 237         OUT_RING  (chan, 1);
 238         BEGIN_RING(chan, tesla, NV50TCL_RT_ADDRESS_HIGH(0), 5);
 239         OUT_RELOCh(chan, bo, ((struct nv50_surface *)dst)->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 240         OUT_RELOCl(chan, bo, ((struct nv50_surface *)dst)->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 241         OUT_RING  (chan, nv50_format_table[dst->format].rt);
 242         OUT_RING  (chan, mt->level[dst->u.tex.level].tile_mode << 4);
 243         OUT_RING  (chan, 0);
 244         BEGIN_RING(chan, tesla, NV50TCL_RT_HORIZ(0), 2);
 245         OUT_RING  (chan, dst->width);
 246         OUT_RING  (chan, dst->height);
 247         BEGIN_RING(chan, tesla, NV50TCL_RT_ARRAY_MODE, 1);
 248         OUT_RING  (chan, 1);
 249
 250         /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
 251
 252         BEGIN_RING(chan, tesla, NV50TCL_VIEWPORT_HORIZ(0), 2);
 253         OUT_RING  (chan, (width << 16) | dstx);
 254         OUT_RING  (chan, (height << 16) | dsty);
 255
 256         BEGIN_RING(chan, tesla, NV50TCL_CLEAR_BUFFERS, 1);
 257         OUT_RING  (chan, 0x3c);
 258
 259         nv50->dirty |= NV50_NEW_FRAMEBUFFER;
 260 }
 261
 262 static void
 263 nv50_clear_depth_stencil(struct pipe_context *pipe,
 264                          struct pipe_surface *dst,
 265                          unsigned clear_flags,
 266                          double depth,
 267                          unsigned stencil,
 268                          unsigned dstx, unsigned dsty,
 269                          unsigned width, unsigned height)
 270 {
 271         struct nv50_context *nv50 = nv50_context(pipe);
 272         struct nv50_screen *screen = nv50->screen;
 273         struct nouveau_channel *chan = screen->base.channel;
 274         struct nouveau_grobj *tesla = screen->tesla;
 275         struct nv50_miptree *mt = nv50_miptree(dst->texture);
 276         struct nouveau_bo *bo = mt->base.bo;
 277         uint32_t mode = 0;
 278
 279         if (clear_flags & PIPE_CLEAR_DEPTH) {
 280                 BEGIN_RING(chan, tesla, NV50TCL_CLEAR_DEPTH, 1);
 281                 OUT_RINGf (chan, depth);
 282                 mode |= NV50TCL_CLEAR_BUFFERS_Z;
 283         }
 284
 285         if (clear_flags & PIPE_CLEAR_STENCIL) {
 286                 BEGIN_RING(chan, tesla, NV50TCL_CLEAR_STENCIL, 1);
 287                 OUT_RING  (chan, stencil & 0xff);
 288                 mode |= NV50TCL_CLEAR_BUFFERS_S;
 289         }
 290
 291         if (MARK_RING(chan, 17, 2))
 292                 return;
 293
 294         BEGIN_RING(chan, tesla, NV50TCL_ZETA_ADDRESS_HIGH, 5);
 295         OUT_RELOCh(chan, bo, ((struct nv50_surface *)dst)->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 296         OUT_RELOCl(chan, bo, ((struct nv50_surface *)dst)->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 297         OUT_RING  (chan, nv50_format_table[dst->format].rt);
 298         OUT_RING  (chan, mt->level[dst->u.tex.level].tile_mode << 4);
 299         OUT_RING  (chan, 0);
 300         BEGIN_RING(chan, tesla, NV50TCL_ZETA_ENABLE, 1);
 301         OUT_RING  (chan, 1);
 302         BEGIN_RING(chan, tesla, NV50TCL_ZETA_HORIZ, 3);
 303         OUT_RING  (chan, dst->width);
 304         OUT_RING  (chan, dst->height);
 305         OUT_RING  (chan, (1 << 16) | 1);
 306
 307         BEGIN_RING(chan, tesla, NV50TCL_VIEWPORT_HORIZ(0), 2);
 308         OUT_RING  (chan, (width << 16) | dstx);
 309         OUT_RING  (chan, (height << 16) | dsty);
 310
 311         BEGIN_RING(chan, tesla, NV50TCL_CLEAR_BUFFERS, 1);
 312         OUT_RING  (chan, mode);
 313
 314         nv50->dirty |= NV50_NEW_FRAMEBUFFER;
 315 }
 316
 317 void
 318 nv50_init_surface_functions(struct nv50_context *nv50)
 319 {
 320         nv50->pipe.resource_copy_region = nv50_surface_copy;
 321         nv50->pipe.clear_render_target = nv50_clear_render_target;
 322         nv50->pipe.clear_depth_stencil = nv50_clear_depth_stencil;
 323 }
 324
 325