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gallium: add condition parameter to render_condition
[mesa.git] / src / gallium / drivers / nv50 / nv50_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "tgsi/tgsi_ureg.h"
33
34 #include "os/os_thread.h"
35
36 #include "nv50_context.h"
37 #include "nv50_resource.h"
38
39 #include "nv50_defs.xml.h"
40 #include "nv50_texture.xml.h"
41
42 /* these are used in nv50_blit.h */
43 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
44 #define NV50_ENG2D_NOCONVERT_FORMATS 0x0008402000000000ULL
45 #define NV50_ENG2D_LUMINANCE_FORMATS 0x0008402000000000ULL
46 #define NV50_ENG2D_INTENSITY_FORMATS 0x0000000000000000ULL
47 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
48
49 #define NOUVEAU_DRIVER 0x50
50 #include "nv50_blit.h"
51
52 static INLINE uint8_t
53 nv50_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal)
54 {
55 uint8_t id = nv50_format_table[format].rt;
56
57 /* Hardware values for color formats range from 0xc0 to 0xff,
58 * but the 2D engine doesn't support all of them.
59 */
60 if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
61 return id;
62 assert(dst_src_equal);
63
64 switch (util_format_get_blocksize(format)) {
65 case 1:
66 return NV50_SURFACE_FORMAT_R8_UNORM;
67 case 2:
68 return NV50_SURFACE_FORMAT_R16_UNORM;
69 case 4:
70 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
71 default:
72 return 0;
73 }
74 }
75
76 static int
77 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
78 struct nv50_miptree *mt, unsigned level, unsigned layer,
79 enum pipe_format pformat, boolean dst_src_pformat_equal)
80 {
81 struct nouveau_bo *bo = mt->base.bo;
82 uint32_t width, height, depth;
83 uint32_t format;
84 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
85 uint32_t offset = mt->level[level].offset;
86
87 format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
88 if (!format) {
89 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
90 util_format_name(pformat));
91 return 1;
92 }
93
94 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
95 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
96 depth = u_minify(mt->base.base.depth0, level);
97
98 offset = mt->level[level].offset;
99 if (!mt->layout_3d) {
100 offset += mt->layer_stride * layer;
101 depth = 1;
102 layer = 0;
103 } else
104 if (!dst) {
105 offset += nv50_mt_zslice_offset(mt, level, layer);
106 layer = 0;
107 }
108
109 if (!nouveau_bo_memtype(bo)) {
110 BEGIN_NV04(push, SUBC_2D(mthd), 2);
111 PUSH_DATA (push, format);
112 PUSH_DATA (push, 1);
113 BEGIN_NV04(push, SUBC_2D(mthd + 0x14), 5);
114 PUSH_DATA (push, mt->level[level].pitch);
115 PUSH_DATA (push, width);
116 PUSH_DATA (push, height);
117 PUSH_DATAh(push, bo->offset + offset);
118 PUSH_DATA (push, bo->offset + offset);
119 } else {
120 BEGIN_NV04(push, SUBC_2D(mthd), 5);
121 PUSH_DATA (push, format);
122 PUSH_DATA (push, 0);
123 PUSH_DATA (push, mt->level[level].tile_mode);
124 PUSH_DATA (push, depth);
125 PUSH_DATA (push, layer);
126 BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4);
127 PUSH_DATA (push, width);
128 PUSH_DATA (push, height);
129 PUSH_DATAh(push, bo->offset + offset);
130 PUSH_DATA (push, bo->offset + offset);
131 }
132
133 #if 0
134 if (dst) {
135 BEGIN_NV04(push, SUBC_2D(NV50_2D_CLIP_X), 4);
136 PUSH_DATA (push, 0);
137 PUSH_DATA (push, 0);
138 PUSH_DATA (push, width);
139 PUSH_DATA (push, height);
140 }
141 #endif
142 return 0;
143 }
144
145 static int
146 nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
147 struct nv50_miptree *dst, unsigned dst_level,
148 unsigned dx, unsigned dy, unsigned dz,
149 struct nv50_miptree *src, unsigned src_level,
150 unsigned sx, unsigned sy, unsigned sz,
151 unsigned w, unsigned h)
152 {
153 const enum pipe_format dfmt = dst->base.base.format;
154 const enum pipe_format sfmt = src->base.base.format;
155 int ret;
156 boolean eqfmt = dfmt == sfmt;
157
158 if (!PUSH_SPACE(push, 2 * 16 + 32))
159 return PIPE_ERROR;
160
161 ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
162 if (ret)
163 return ret;
164
165 ret = nv50_2d_texture_set(push, 0, src, src_level, sz, sfmt, eqfmt);
166 if (ret)
167 return ret;
168
169 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
170 PUSH_DATA (push, NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE);
171 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
172 PUSH_DATA (push, dx << dst->ms_x);
173 PUSH_DATA (push, dy << dst->ms_y);
174 PUSH_DATA (push, w << dst->ms_x);
175 PUSH_DATA (push, h << dst->ms_y);
176 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
177 PUSH_DATA (push, 0);
178 PUSH_DATA (push, 1);
179 PUSH_DATA (push, 0);
180 PUSH_DATA (push, 1);
181 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
182 PUSH_DATA (push, 0);
183 PUSH_DATA (push, sx << src->ms_x);
184 PUSH_DATA (push, 0);
185 PUSH_DATA (push, sy << src->ms_y);
186
187 return 0;
188 }
189
190 static void
191 nv50_resource_copy_region(struct pipe_context *pipe,
192 struct pipe_resource *dst, unsigned dst_level,
193 unsigned dstx, unsigned dsty, unsigned dstz,
194 struct pipe_resource *src, unsigned src_level,
195 const struct pipe_box *src_box)
196 {
197 struct nv50_context *nv50 = nv50_context(pipe);
198 int ret;
199 boolean m2mf;
200 unsigned dst_layer = dstz, src_layer = src_box->z;
201
202 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
203 nouveau_copy_buffer(&nv50->base,
204 nv04_resource(dst), dstx,
205 nv04_resource(src), src_box->x, src_box->width);
206 return;
207 }
208
209 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
210 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
211
212 m2mf = (src->format == dst->format) ||
213 (util_format_get_blocksizebits(src->format) ==
214 util_format_get_blocksizebits(dst->format));
215
216 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
217
218 if (m2mf) {
219 struct nv50_m2mf_rect drect, srect;
220 unsigned i;
221 unsigned nx = util_format_get_nblocksx(src->format, src_box->width);
222 unsigned ny = util_format_get_nblocksy(src->format, src_box->height);
223
224 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
225 nv50_m2mf_rect_setup(&srect, src, src_level,
226 src_box->x, src_box->y, src_box->z);
227
228 for (i = 0; i < src_box->depth; ++i) {
229 nv50_m2mf_transfer_rect(nv50, &drect, &srect, nx, ny);
230
231 if (nv50_miptree(dst)->layout_3d)
232 drect.z++;
233 else
234 drect.base += nv50_miptree(dst)->layer_stride;
235
236 if (nv50_miptree(src)->layout_3d)
237 srect.z++;
238 else
239 srect.base += nv50_miptree(src)->layer_stride;
240 }
241 return;
242 }
243
244 assert((src->format == dst->format) ||
245 (nv50_2d_src_format_faithful(src->format) &&
246 nv50_2d_dst_format_faithful(dst->format)));
247
248 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(src), RD);
249 BCTX_REFN(nv50->bufctx, 2D, nv04_resource(dst), WR);
250 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
251 nouveau_pushbuf_validate(nv50->base.pushbuf);
252
253 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
254 ret = nv50_2d_texture_do_copy(nv50->base.pushbuf,
255 nv50_miptree(dst), dst_level,
256 dstx, dsty, dst_layer,
257 nv50_miptree(src), src_level,
258 src_box->x, src_box->y, src_layer,
259 src_box->width, src_box->height);
260 if (ret)
261 break;
262 }
263 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
264 }
265
266 static void
267 nv50_clear_render_target(struct pipe_context *pipe,
268 struct pipe_surface *dst,
269 const union pipe_color_union *color,
270 unsigned dstx, unsigned dsty,
271 unsigned width, unsigned height)
272 {
273 struct nv50_context *nv50 = nv50_context(pipe);
274 struct nouveau_pushbuf *push = nv50->base.pushbuf;
275 struct nv50_miptree *mt = nv50_miptree(dst->texture);
276 struct nv50_surface *sf = nv50_surface(dst);
277 struct nouveau_bo *bo = mt->base.bo;
278 unsigned z;
279
280 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
281 PUSH_DATAf(push, color->f[0]);
282 PUSH_DATAf(push, color->f[1]);
283 PUSH_DATAf(push, color->f[2]);
284 PUSH_DATAf(push, color->f[3]);
285
286 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
287 return;
288
289 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
290
291 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
292 PUSH_DATA (push, 1);
293 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
294 PUSH_DATAh(push, bo->offset + sf->offset);
295 PUSH_DATA (push, bo->offset + sf->offset);
296 PUSH_DATA (push, nv50_format_table[dst->format].rt);
297 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
298 PUSH_DATA (push, 0);
299 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
300 if (nouveau_bo_memtype(bo))
301 PUSH_DATA(push, sf->width);
302 else
303 PUSH_DATA(push, NV50_3D_RT_HORIZ_LINEAR | mt->level[0].pitch);
304 PUSH_DATA (push, sf->height);
305 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
306 PUSH_DATA (push, 1);
307
308 if (!nouveau_bo_memtype(bo)) {
309 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
310 PUSH_DATA (push, 0);
311 }
312
313 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
314
315 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
316 PUSH_DATA (push, (width << 16) | dstx);
317 PUSH_DATA (push, (height << 16) | dsty);
318
319 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
320 for (z = 0; z < sf->depth; ++z) {
321 PUSH_DATA (push, 0x3c |
322 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
323 }
324
325 nv50->dirty |= NV50_NEW_FRAMEBUFFER;
326 }
327
328 static void
329 nv50_clear_depth_stencil(struct pipe_context *pipe,
330 struct pipe_surface *dst,
331 unsigned clear_flags,
332 double depth,
333 unsigned stencil,
334 unsigned dstx, unsigned dsty,
335 unsigned width, unsigned height)
336 {
337 struct nv50_context *nv50 = nv50_context(pipe);
338 struct nouveau_pushbuf *push = nv50->base.pushbuf;
339 struct nv50_miptree *mt = nv50_miptree(dst->texture);
340 struct nv50_surface *sf = nv50_surface(dst);
341 struct nouveau_bo *bo = mt->base.bo;
342 uint32_t mode = 0;
343 unsigned z;
344
345 assert(nouveau_bo_memtype(bo)); /* ZETA cannot be linear */
346
347 if (clear_flags & PIPE_CLEAR_DEPTH) {
348 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
349 PUSH_DATAf(push, depth);
350 mode |= NV50_3D_CLEAR_BUFFERS_Z;
351 }
352
353 if (clear_flags & PIPE_CLEAR_STENCIL) {
354 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
355 PUSH_DATA (push, stencil & 0xff);
356 mode |= NV50_3D_CLEAR_BUFFERS_S;
357 }
358
359 if (nouveau_pushbuf_space(push, 32 + sf->depth, 1, 0))
360 return;
361
362 PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
363
364 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
365 PUSH_DATAh(push, bo->offset + sf->offset);
366 PUSH_DATA (push, bo->offset + sf->offset);
367 PUSH_DATA (push, nv50_format_table[dst->format].rt);
368 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
369 PUSH_DATA (push, 0);
370 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
371 PUSH_DATA (push, 1);
372 BEGIN_NV04(push, NV50_3D(ZETA_HORIZ), 3);
373 PUSH_DATA (push, sf->width);
374 PUSH_DATA (push, sf->height);
375 PUSH_DATA (push, (1 << 16) | 1);
376
377 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
378 PUSH_DATA (push, (width << 16) | dstx);
379 PUSH_DATA (push, (height << 16) | dsty);
380
381 BEGIN_NI04(push, NV50_3D(CLEAR_BUFFERS), sf->depth);
382 for (z = 0; z < sf->depth; ++z) {
383 PUSH_DATA (push, mode |
384 (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
385 }
386
387 nv50->dirty |= NV50_NEW_FRAMEBUFFER;
388 }
389
390 void
391 nv50_clear(struct pipe_context *pipe, unsigned buffers,
392 const union pipe_color_union *color,
393 double depth, unsigned stencil)
394 {
395 struct nv50_context *nv50 = nv50_context(pipe);
396 struct nouveau_pushbuf *push = nv50->base.pushbuf;
397 struct pipe_framebuffer_state *fb = &nv50->framebuffer;
398 unsigned i;
399 uint32_t mode = 0;
400
401 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
402 if (!nv50_state_validate(nv50, NV50_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
403 return;
404
405 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
406 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
407 PUSH_DATAf(push, color->f[0]);
408 PUSH_DATAf(push, color->f[1]);
409 PUSH_DATAf(push, color->f[2]);
410 PUSH_DATAf(push, color->f[3]);
411 mode =
412 NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
413 NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
414 }
415
416 if (buffers & PIPE_CLEAR_DEPTH) {
417 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
418 PUSH_DATA (push, fui(depth));
419 mode |= NV50_3D_CLEAR_BUFFERS_Z;
420 }
421
422 if (buffers & PIPE_CLEAR_STENCIL) {
423 BEGIN_NV04(push, NV50_3D(CLEAR_STENCIL), 1);
424 PUSH_DATA (push, stencil & 0xff);
425 mode |= NV50_3D_CLEAR_BUFFERS_S;
426 }
427
428 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
429 PUSH_DATA (push, mode);
430
431 for (i = 1; i < fb->nr_cbufs; i++) {
432 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
433 PUSH_DATA (push, (i << 6) | 0x3c);
434 }
435 }
436
437
438 /* =============================== BLIT CODE ===================================
439 */
440
441 struct nv50_blitter
442 {
443 struct nv50_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
444 struct nv50_program vp;
445
446 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
447
448 pipe_mutex mutex;
449 };
450
451 struct nv50_blitctx
452 {
453 struct nv50_context *nv50;
454 struct nv50_program *fp;
455 uint8_t mode;
456 uint16_t color_mask;
457 uint8_t filter;
458 enum pipe_texture_target target;
459 struct {
460 struct pipe_framebuffer_state fb;
461 struct nv50_program *vp;
462 struct nv50_program *gp;
463 struct nv50_program *fp;
464 unsigned num_textures[3];
465 unsigned num_samplers[3];
466 struct pipe_sampler_view *texture[2];
467 struct nv50_tsc_entry *sampler[2];
468 uint32_t dirty;
469 } saved;
470 };
471
472 static void
473 nv50_blitter_make_vp(struct nv50_blitter *blit)
474 {
475 static const uint32_t code[] =
476 {
477 0x10000001, 0x0423c788, /* mov b32 o[0x00] s[0x00] */ /* HPOS.x */
478 0x10000205, 0x0423c788, /* mov b32 o[0x04] s[0x04] */ /* HPOS.y */
479 0x10000409, 0x0423c788, /* mov b32 o[0x08] s[0x08] */ /* TEXC.x */
480 0x1000060d, 0x0423c788, /* mov b32 o[0x0c] s[0x0c] */ /* TEXC.y */
481 0x10000811, 0x0423c789, /* mov b32 o[0x10] s[0x10] */ /* TEXC.z */
482 };
483
484 blit->vp.type = PIPE_SHADER_VERTEX;
485 blit->vp.translated = TRUE;
486 blit->vp.code = (uint32_t *)code; /* const_cast */
487 blit->vp.code_size = sizeof(code);
488 blit->vp.max_gpr = 4;
489 blit->vp.max_out = 5;
490 blit->vp.out_nr = 2;
491 blit->vp.out[0].mask = 0x3;
492 blit->vp.out[0].sn = TGSI_SEMANTIC_POSITION;
493 blit->vp.out[1].hw = 2;
494 blit->vp.out[1].mask = 0x7;
495 blit->vp.out[1].sn = TGSI_SEMANTIC_GENERIC;
496 blit->vp.out[1].si = 0;
497 blit->vp.vp.attrs[0] = 0x73;
498 blit->vp.vp.psiz = 0x40;
499 blit->vp.vp.edgeflag = 0x40;
500 }
501
502 void *
503 nv50_blitter_make_fp(struct pipe_context *pipe,
504 unsigned mode,
505 enum pipe_texture_target ptarg)
506 {
507 struct ureg_program *ureg;
508 struct ureg_src tc;
509 struct ureg_dst out;
510 struct ureg_dst data;
511
512 const unsigned target = nv50_blit_get_tgsi_texture_target(ptarg);
513
514 boolean tex_rgbaz = FALSE;
515 boolean tex_s = FALSE;
516 boolean cvt_un8 = FALSE;
517
518 if (mode != NV50_BLIT_MODE_PASS &&
519 mode != NV50_BLIT_MODE_Z24X8 &&
520 mode != NV50_BLIT_MODE_X8Z24)
521 tex_s = TRUE;
522
523 if (mode != NV50_BLIT_MODE_X24S8 &&
524 mode != NV50_BLIT_MODE_S8X24 &&
525 mode != NV50_BLIT_MODE_XS)
526 tex_rgbaz = TRUE;
527
528 if (mode != NV50_BLIT_MODE_PASS &&
529 mode != NV50_BLIT_MODE_ZS &&
530 mode != NV50_BLIT_MODE_XS)
531 cvt_un8 = TRUE;
532
533 ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
534 if (!ureg)
535 return NULL;
536
537 out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
538 tc = ureg_DECL_fs_input(
539 ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
540
541 data = ureg_DECL_temporary(ureg);
542
543 if (tex_s) {
544 ureg_TEX(ureg, ureg_writemask(data, TGSI_WRITEMASK_X),
545 target, tc, ureg_DECL_sampler(ureg, 1));
546 ureg_MOV(ureg, ureg_writemask(data, TGSI_WRITEMASK_Y),
547 ureg_scalar(ureg_src(data), TGSI_SWIZZLE_X));
548 }
549 if (tex_rgbaz) {
550 const unsigned mask = (mode == NV50_BLIT_MODE_PASS) ?
551 TGSI_WRITEMASK_XYZW : TGSI_WRITEMASK_X;
552 ureg_TEX(ureg, ureg_writemask(data, mask),
553 target, tc, ureg_DECL_sampler(ureg, 0));
554 }
555
556 if (cvt_un8) {
557 struct ureg_src mask;
558 struct ureg_src scale;
559 struct ureg_dst outz;
560 struct ureg_dst outs;
561 struct ureg_dst zdst3 = ureg_writemask(data, TGSI_WRITEMASK_XYZ);
562 struct ureg_dst zdst = ureg_writemask(data, TGSI_WRITEMASK_X);
563 struct ureg_dst sdst = ureg_writemask(data, TGSI_WRITEMASK_Y);
564 struct ureg_src zsrc3 = ureg_src(data);
565 struct ureg_src zsrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_X);
566 struct ureg_src ssrc = ureg_scalar(zsrc3, TGSI_SWIZZLE_Y);
567 struct ureg_src zshuf;
568
569 mask = ureg_imm3u(ureg, 0x0000ff, 0x00ff00, 0xff0000);
570 scale = ureg_imm4f(ureg,
571 1.0f / 0x0000ff, 1.0f / 0x00ff00, 1.0f / 0xff0000,
572 (1 << 24) - 1);
573
574 if (mode == NV50_BLIT_MODE_Z24S8 ||
575 mode == NV50_BLIT_MODE_X24S8 ||
576 mode == NV50_BLIT_MODE_Z24X8) {
577 outz = ureg_writemask(out, TGSI_WRITEMASK_XYZ);
578 outs = ureg_writemask(out, TGSI_WRITEMASK_W);
579 zshuf = ureg_src(data);
580 } else {
581 outz = ureg_writemask(out, TGSI_WRITEMASK_YZW);
582 outs = ureg_writemask(out, TGSI_WRITEMASK_X);
583 zshuf = ureg_swizzle(zsrc3, TGSI_SWIZZLE_W,
584 TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z);
585 }
586
587 if (tex_s) {
588 ureg_I2F(ureg, sdst, ssrc);
589 ureg_MUL(ureg, outs, ssrc, ureg_scalar(scale, TGSI_SWIZZLE_X));
590 }
591
592 if (tex_rgbaz) {
593 ureg_MUL(ureg, zdst, zsrc, ureg_scalar(scale, TGSI_SWIZZLE_W));
594 ureg_F2I(ureg, zdst, zsrc);
595 ureg_AND(ureg, zdst3, zsrc, mask);
596 ureg_I2F(ureg, zdst3, zsrc3);
597 ureg_MUL(ureg, zdst3, zsrc3, scale);
598 ureg_MOV(ureg, outz, zshuf);
599 }
600 } else {
601 unsigned mask = TGSI_WRITEMASK_XYZW;
602
603 if (mode != NV50_BLIT_MODE_PASS) {
604 mask &= ~TGSI_WRITEMASK_ZW;
605 if (!tex_s)
606 mask = TGSI_WRITEMASK_X;
607 if (!tex_rgbaz)
608 mask = TGSI_WRITEMASK_Y;
609 }
610 ureg_MOV(ureg, ureg_writemask(out, mask), ureg_src(data));
611 }
612 ureg_END(ureg);
613
614 return ureg_create_shader_and_destroy(ureg, pipe);
615 }
616
617 static void
618 nv50_blitter_make_sampler(struct nv50_blitter *blit)
619 {
620 /* clamp to edge, min/max lod = 0, nearest filtering */
621
622 blit->sampler[0].id = -1;
623
624 blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
625 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
626 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
627 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
628 blit->sampler[0].tsc[1] =
629 NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
630
631 /* clamp to edge, min/max lod = 0, bilinear filtering */
632
633 blit->sampler[1].id = -1;
634
635 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
636 blit->sampler[1].tsc[1] =
637 NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
638 }
639
640 unsigned
641 nv50_blit_select_mode(const struct pipe_blit_info *info)
642 {
643 const unsigned mask = info->mask;
644
645 switch (info->dst.resource->format) {
646 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
647 case PIPE_FORMAT_Z24X8_UNORM:
648 switch (mask & PIPE_MASK_ZS) {
649 case PIPE_MASK_ZS: return NV50_BLIT_MODE_Z24S8;
650 case PIPE_MASK_Z: return NV50_BLIT_MODE_Z24X8;
651 default:
652 return NV50_BLIT_MODE_X24S8;
653 }
654 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
655 switch (mask & PIPE_MASK_ZS) {
656 case PIPE_MASK_ZS: return NV50_BLIT_MODE_S8Z24;
657 case PIPE_MASK_Z: return NV50_BLIT_MODE_X8Z24;
658 default:
659 return NV50_BLIT_MODE_S8X24;
660 }
661 case PIPE_FORMAT_Z32_FLOAT:
662 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
663 switch (mask & PIPE_MASK_ZS) {
664 case PIPE_MASK_ZS: return NV50_BLIT_MODE_ZS;
665 case PIPE_MASK_Z: return NV50_BLIT_MODE_PASS;
666 default:
667 return NV50_BLIT_MODE_XS;
668 }
669 default:
670 return NV50_BLIT_MODE_PASS;
671 }
672 }
673
674 static void
675 nv50_blit_select_fp(struct nv50_blitctx *ctx, const struct pipe_blit_info *info)
676 {
677 struct nv50_blitter *blitter = ctx->nv50->screen->blitter;
678
679 const enum pipe_texture_target ptarg =
680 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
681
682 const unsigned targ = nv50_blit_texture_type(ptarg);
683 const unsigned mode = ctx->mode;
684
685 if (!blitter->fp[targ][mode]) {
686 pipe_mutex_lock(blitter->mutex);
687 if (!blitter->fp[targ][mode])
688 blitter->fp[targ][mode] =
689 nv50_blitter_make_fp(&ctx->nv50->base.pipe, mode, ptarg);
690 pipe_mutex_unlock(blitter->mutex);
691 }
692 ctx->fp = blitter->fp[targ][mode];
693 }
694
695 static void
696 nv50_blit_set_dst(struct nv50_blitctx *ctx,
697 struct pipe_resource *res, unsigned level, unsigned layer,
698 enum pipe_format format)
699 {
700 struct nv50_context *nv50 = ctx->nv50;
701 struct pipe_context *pipe = &nv50->base.pipe;
702 struct pipe_surface templ;
703
704 if (util_format_is_depth_or_stencil(format))
705 templ.format = nv50_blit_zeta_to_colour_format(format);
706 else
707 templ.format = format;
708
709 templ.u.tex.level = level;
710 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
711
712 if (layer == -1) {
713 templ.u.tex.first_layer = 0;
714 templ.u.tex.last_layer =
715 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
716 }
717
718 nv50->framebuffer.cbufs[0] = nv50_miptree_surface_new(pipe, res, &templ);
719 nv50->framebuffer.nr_cbufs = 1;
720 nv50->framebuffer.zsbuf = NULL;
721 nv50->framebuffer.width = nv50->framebuffer.cbufs[0]->width;
722 nv50->framebuffer.height = nv50->framebuffer.cbufs[0]->height;
723 }
724
725 static void
726 nv50_blit_set_src(struct nv50_blitctx *blit,
727 struct pipe_resource *res, unsigned level, unsigned layer,
728 enum pipe_format format, const uint8_t filter)
729 {
730 struct nv50_context *nv50 = blit->nv50;
731 struct pipe_context *pipe = &nv50->base.pipe;
732 struct pipe_sampler_view templ;
733 uint32_t flags;
734 enum pipe_texture_target target;
735
736 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
737
738 templ.format = format;
739 templ.u.tex.first_level = templ.u.tex.last_level = level;
740 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
741 templ.swizzle_r = PIPE_SWIZZLE_RED;
742 templ.swizzle_g = PIPE_SWIZZLE_GREEN;
743 templ.swizzle_b = PIPE_SWIZZLE_BLUE;
744 templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
745
746 if (layer == -1) {
747 templ.u.tex.first_layer = 0;
748 templ.u.tex.last_layer =
749 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
750 }
751
752 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
753 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
754 if (filter && res->nr_samples == 8)
755 flags |= NV50_TEXVIEW_FILTER_MSAA8;
756
757 nv50->textures[2][0] = nv50_create_texture_view(
758 pipe, res, &templ, flags, target);
759 nv50->textures[2][1] = NULL;
760
761 nv50->num_textures[0] = nv50->num_textures[1] = 0;
762 nv50->num_textures[2] = 1;
763
764 templ.format = nv50_zs_to_s_format(format);
765 if (templ.format != res->format) {
766 nv50->textures[2][1] = nv50_create_texture_view(
767 pipe, res, &templ, flags, target);
768 nv50->num_textures[2] = 2;
769 }
770 }
771
772 static void
773 nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
774 {
775 struct nouveau_pushbuf *push = blit->nv50->base.pushbuf;
776
777 if (blit->nv50->cond_query) {
778 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
779 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
780 }
781
782 /* blend state */
783 BEGIN_NV04(push, NV50_3D(COLOR_MASK(0)), 1);
784 PUSH_DATA (push, blit->color_mask);
785 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
786 PUSH_DATA (push, 0);
787 BEGIN_NV04(push, NV50_3D(LOGIC_OP_ENABLE), 1);
788 PUSH_DATA (push, 0);
789
790 /* rasterizer state */
791 #ifndef NV50_SCISSORS_CLIPPING
792 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 1);
793 PUSH_DATA (push, 1);
794 #endif
795 BEGIN_NV04(push, NV50_3D(VERTEX_TWO_SIDE_ENABLE), 1);
796 PUSH_DATA (push, 0);
797 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
798 PUSH_DATA (push, 0);
799 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
800 PUSH_DATA (push, 0);
801 BEGIN_NV04(push, NV50_3D(MSAA_MASK(0)), 4);
802 PUSH_DATA (push, 0xffff);
803 PUSH_DATA (push, 0xffff);
804 PUSH_DATA (push, 0xffff);
805 PUSH_DATA (push, 0xffff);
806 BEGIN_NV04(push, NV50_3D(POLYGON_MODE_FRONT), 3);
807 PUSH_DATA (push, NV50_3D_POLYGON_MODE_FRONT_FILL);
808 PUSH_DATA (push, NV50_3D_POLYGON_MODE_BACK_FILL);
809 PUSH_DATA (push, 0);
810 BEGIN_NV04(push, NV50_3D(CULL_FACE_ENABLE), 1);
811 PUSH_DATA (push, 0);
812 BEGIN_NV04(push, NV50_3D(POLYGON_STIPPLE_ENABLE), 1);
813 PUSH_DATA (push, 0);
814 BEGIN_NV04(push, NV50_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
815 PUSH_DATA (push, 0);
816
817 /* zsa state */
818 BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
819 PUSH_DATA (push, 0);
820 BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
821 PUSH_DATA (push, 0);
822 BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
823 PUSH_DATA (push, 0);
824 }
825
826 static void
827 nv50_blitctx_pre_blit(struct nv50_blitctx *ctx)
828 {
829 struct nv50_context *nv50 = ctx->nv50;
830 struct nv50_blitter *blitter = nv50->screen->blitter;
831 int s;
832
833 ctx->saved.fb.width = nv50->framebuffer.width;
834 ctx->saved.fb.height = nv50->framebuffer.height;
835 ctx->saved.fb.nr_cbufs = nv50->framebuffer.nr_cbufs;
836 ctx->saved.fb.cbufs[0] = nv50->framebuffer.cbufs[0];
837 ctx->saved.fb.zsbuf = nv50->framebuffer.zsbuf;
838
839 ctx->saved.vp = nv50->vertprog;
840 ctx->saved.gp = nv50->gmtyprog;
841 ctx->saved.fp = nv50->fragprog;
842
843 nv50->vertprog = &blitter->vp;
844 nv50->gmtyprog = NULL;
845 nv50->fragprog = ctx->fp;
846
847 for (s = 0; s < 3; ++s) {
848 ctx->saved.num_textures[s] = nv50->num_textures[s];
849 ctx->saved.num_samplers[s] = nv50->num_samplers[s];
850 }
851 ctx->saved.texture[0] = nv50->textures[2][0];
852 ctx->saved.texture[1] = nv50->textures[2][1];
853 ctx->saved.sampler[0] = nv50->samplers[2][0];
854 ctx->saved.sampler[1] = nv50->samplers[2][1];
855
856 nv50->samplers[2][0] = &blitter->sampler[ctx->filter];
857 nv50->samplers[2][1] = &blitter->sampler[ctx->filter];
858
859 nv50->num_samplers[0] = nv50->num_samplers[1] = 0;
860 nv50->num_samplers[2] = 2;
861
862 ctx->saved.dirty = nv50->dirty;
863
864 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
865 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
866
867 nv50->dirty =
868 NV50_NEW_FRAMEBUFFER |
869 NV50_NEW_VERTPROG | NV50_NEW_FRAGPROG | NV50_NEW_GMTYPROG |
870 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS;
871 }
872
873 static void
874 nv50_blitctx_post_blit(struct nv50_blitctx *blit)
875 {
876 struct nv50_context *nv50 = blit->nv50;
877 int s;
878
879 pipe_surface_reference(&nv50->framebuffer.cbufs[0], NULL);
880
881 nv50->framebuffer.width = blit->saved.fb.width;
882 nv50->framebuffer.height = blit->saved.fb.height;
883 nv50->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
884 nv50->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
885 nv50->framebuffer.zsbuf = blit->saved.fb.zsbuf;
886
887 nv50->vertprog = blit->saved.vp;
888 nv50->gmtyprog = blit->saved.gp;
889 nv50->fragprog = blit->saved.fp;
890
891 pipe_sampler_view_reference(&nv50->textures[2][0], NULL);
892 pipe_sampler_view_reference(&nv50->textures[2][1], NULL);
893
894 for (s = 0; s < 3; ++s) {
895 nv50->num_textures[s] = blit->saved.num_textures[s];
896 nv50->num_samplers[s] = blit->saved.num_samplers[s];
897 }
898 nv50->textures[2][0] = blit->saved.texture[0];
899 nv50->textures[2][1] = blit->saved.texture[1];
900 nv50->samplers[2][0] = blit->saved.sampler[0];
901 nv50->samplers[2][1] = blit->saved.sampler[1];
902
903 if (nv50->cond_query)
904 nv50->base.pipe.render_condition(&nv50->base.pipe, nv50->cond_query,
905 nv50->cond_cond, nv50->cond_mode);
906
907 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_FB);
908 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_TEXTURES);
909
910 nv50->dirty = blit->saved.dirty |
911 (NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR | NV50_NEW_SAMPLE_MASK |
912 NV50_NEW_RASTERIZER | NV50_NEW_ZSA | NV50_NEW_BLEND |
913 NV50_NEW_TEXTURES | NV50_NEW_SAMPLERS |
914 NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG | NV50_NEW_FRAGPROG);
915 }
916
917
918 static void
919 nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
920 {
921 struct nv50_blitctx *blit = nv50->blit;
922 struct nouveau_pushbuf *push = nv50->base.pushbuf;
923 struct pipe_resource *src = info->src.resource;
924 struct pipe_resource *dst = info->dst.resource;
925 int32_t minx, maxx, miny, maxy;
926 int32_t i;
927 float x0, x1, y0, y1, z;
928 float dz;
929 float x_range, y_range;
930
931 blit->mode = nv50_blit_select_mode(info);
932 blit->color_mask = nv50_blit_derive_color_mask(info);
933 blit->filter = nv50_blit_get_filter(info);
934
935 nv50_blit_select_fp(blit, info);
936 nv50_blitctx_pre_blit(blit);
937
938 nv50_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
939 nv50_blit_set_src(blit, src, info->src.level, -1, info->src.format,
940 blit->filter);
941
942 nv50_blitctx_prepare_state(blit);
943
944 nv50_state_validate(nv50, ~0, 36);
945
946 x_range = (float)info->src.box.width / (float)info->dst.box.width;
947 y_range = (float)info->src.box.height / (float)info->dst.box.height;
948
949 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
950 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
951
952 x1 = x0 + 16384.0f * x_range;
953 y1 = y0 + 16384.0f * y_range;
954
955 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
956 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
957 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
958 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
959
960 if (src->last_level > 0) {
961 /* If there are mip maps, GPU always assumes normalized coordinates. */
962 const unsigned l = info->src.level;
963 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
964 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
965 x0 /= fh;
966 x1 /= fh;
967 y0 /= fv;
968 y1 /= fv;
969 }
970
971 /* XXX: multiply by 6 for cube arrays ? */
972 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
973 z = (float)info->src.box.z;
974 if (nv50_miptree(src)->layout_3d)
975 z += 0.5f * dz;
976
977 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
978 PUSH_DATA (push, 0);
979 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
980 PUSH_DATA (push, 0x1);
981
982 /* Draw a large triangle in screen coordinates covering the whole
983 * render target, with scissors defining the destination region.
984 * The vertex is supplied with non-normalized texture coordinates
985 * arranged in a way to yield the desired offset and scale.
986 */
987
988 minx = info->dst.box.x;
989 maxx = info->dst.box.x + info->dst.box.width;
990 miny = info->dst.box.y;
991 maxy = info->dst.box.y + info->dst.box.height;
992 if (info->scissor_enable) {
993 minx = MAX2(minx, info->scissor.minx);
994 maxx = MIN2(maxx, info->scissor.maxx);
995 miny = MAX2(miny, info->scissor.miny);
996 maxy = MIN2(maxy, info->scissor.maxy);
997 }
998 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
999 PUSH_DATA (push, (maxx << 16) | minx);
1000 PUSH_DATA (push, (maxy << 16) | miny);
1001
1002 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
1003 if (info->dst.box.z + i) {
1004 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1005 PUSH_DATA (push, info->dst.box.z + i);
1006 }
1007 PUSH_SPACE(push, 32);
1008 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
1009 PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
1010 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1011 PUSH_DATAf(push, x0);
1012 PUSH_DATAf(push, y0);
1013 PUSH_DATAf(push, z);
1014 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1015 PUSH_DATAf(push, 0.0f);
1016 PUSH_DATAf(push, 0.0f);
1017 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1018 PUSH_DATAf(push, x1);
1019 PUSH_DATAf(push, y0);
1020 PUSH_DATAf(push, z);
1021 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1022 PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_x);
1023 PUSH_DATAf(push, 0.0f);
1024 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(1)), 3);
1025 PUSH_DATAf(push, x0);
1026 PUSH_DATAf(push, y1);
1027 PUSH_DATAf(push, z);
1028 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(0)), 2);
1029 PUSH_DATAf(push, 0.0f);
1030 PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_y);
1031 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
1032 PUSH_DATA (push, 0);
1033 }
1034 if (info->dst.box.z + info->dst.box.depth - 1) {
1035 BEGIN_NV04(push, NV50_3D(LAYER), 1);
1036 PUSH_DATA (push, 0);
1037 }
1038
1039 /* re-enable normally constant state */
1040
1041 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
1042 PUSH_DATA (push, 1);
1043
1044 nv50_blitctx_post_blit(blit);
1045 }
1046
1047 static void
1048 nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
1049 {
1050 struct nouveau_pushbuf *push = nv50->base.pushbuf;
1051 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
1052 struct nv50_miptree *src = nv50_miptree(info->src.resource);
1053 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
1054 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
1055 const int32_t dz = info->dst.box.z;
1056 const int32_t sz = info->src.box.z;
1057 uint32_t dstw, dsth;
1058 int32_t dstx, dsty;
1059 int64_t srcx, srcy;
1060 int64_t du_dx, dv_dy;
1061 int i;
1062 uint32_t mode;
1063 uint32_t mask = nv50_blit_eng2d_get_mask(info);
1064 boolean b;
1065
1066 mode = nv50_blit_get_filter(info) ?
1067 NV50_2D_BLIT_CONTROL_FILTER_BILINEAR :
1068 NV50_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
1069 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
1070 NV50_2D_BLIT_CONTROL_ORIGIN_CORNER : NV50_2D_BLIT_CONTROL_ORIGIN_CENTER;
1071
1072 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
1073 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
1074
1075 b = info->dst.format == info->src.format;
1076 nv50_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
1077 nv50_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
1078
1079 if (info->scissor_enable) {
1080 BEGIN_NV04(push, NV50_2D(CLIP_X), 5);
1081 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
1082 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
1083 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
1084 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
1085 PUSH_DATA (push, 1); /* enable */
1086 }
1087
1088 if (mask != 0xffffffff) {
1089 BEGIN_NV04(push, NV50_2D(ROP), 1);
1090 PUSH_DATA (push, 0xca); /* DPSDxax */
1091 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR_FORMAT), 1);
1092 PUSH_DATA (push, NV50_2D_PATTERN_COLOR_FORMAT_32BPP);
1093 BEGIN_NV04(push, NV50_2D(PATTERN_COLOR(0)), 4);
1094 PUSH_DATA (push, 0x00000000);
1095 PUSH_DATA (push, mask);
1096 PUSH_DATA (push, 0xffffffff);
1097 PUSH_DATA (push, 0xffffffff);
1098 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1099 PUSH_DATA (push, NV50_2D_OPERATION_ROP);
1100 } else
1101 if (info->src.format != info->dst.format) {
1102 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1103 info->src.format == PIPE_FORMAT_R16_UNORM ||
1104 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1105 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1106 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1107 BEGIN_NV04(push, NV50_2D(BETA4), 2);
1108 PUSH_DATA (push, mask);
1109 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY_PREMULT);
1110 }
1111 }
1112
1113 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1114 /* ms_x is always >= ms_y */
1115 du_dx <<= src->ms_x - dst->ms_x;
1116 dv_dy <<= src->ms_y - dst->ms_y;
1117 } else {
1118 du_dx >>= dst->ms_x - src->ms_x;
1119 dv_dy >>= dst->ms_y - src->ms_y;
1120 }
1121
1122 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1123 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1124
1125 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1126 /* center src coorinates for proper MS resolve filtering */
1127 srcx += (int64_t)src->ms_x << 32;
1128 srcy += (int64_t)src->ms_y << 32;
1129 }
1130
1131 dstx = info->dst.box.x << dst->ms_x;
1132 dsty = info->dst.box.y << dst->ms_y;
1133
1134 dstw = info->dst.box.width << dst->ms_x;
1135 dsth = info->dst.box.height << dst->ms_y;
1136
1137 if (dstx < 0) {
1138 dstw += dstx;
1139 srcx -= du_dx * dstx;
1140 dstx = 0;
1141 }
1142 if (dsty < 0) {
1143 dsth += dsty;
1144 srcy -= dv_dy * dsty;
1145 dsty = 0;
1146 }
1147
1148 BEGIN_NV04(push, NV50_2D(BLIT_CONTROL), 1);
1149 PUSH_DATA (push, mode);
1150 BEGIN_NV04(push, NV50_2D(BLIT_DST_X), 4);
1151 PUSH_DATA (push, dstx);
1152 PUSH_DATA (push, dsty);
1153 PUSH_DATA (push, dstw);
1154 PUSH_DATA (push, dsth);
1155 BEGIN_NV04(push, NV50_2D(BLIT_DU_DX_FRACT), 4);
1156 PUSH_DATA (push, du_dx);
1157 PUSH_DATA (push, du_dx >> 32);
1158 PUSH_DATA (push, dv_dy);
1159 PUSH_DATA (push, dv_dy >> 32);
1160
1161 BCTX_REFN(nv50->bufctx, 2D, &dst->base, WR);
1162 BCTX_REFN(nv50->bufctx, 2D, &src->base, RD);
1163 nouveau_pushbuf_bufctx(nv50->base.pushbuf, nv50->bufctx);
1164 if (nouveau_pushbuf_validate(nv50->base.pushbuf))
1165 return;
1166
1167 for (i = 0; i < info->dst.box.depth; ++i) {
1168 if (i > 0) {
1169 /* no scaling in z-direction possible for eng2d blits */
1170 if (dst->layout_3d) {
1171 BEGIN_NV04(push, NV50_2D(DST_LAYER), 1);
1172 PUSH_DATA (push, info->dst.box.z + i);
1173 } else {
1174 const unsigned z = info->dst.box.z + i;
1175 BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
1176 PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
1177 PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
1178 }
1179 if (src->layout_3d) {
1180 /* not possible because of depth tiling */
1181 assert(0);
1182 } else {
1183 const unsigned z = info->src.box.z + i;
1184 BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
1185 PUSH_DATAh(push, src->base.address + z * src->layer_stride);
1186 PUSH_DATA (push, src->base.address + z * src->layer_stride);
1187 }
1188 BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1189 PUSH_DATA (push, srcy >> 32);
1190 } else {
1191 BEGIN_NV04(push, NV50_2D(BLIT_SRC_X_FRACT), 4);
1192 PUSH_DATA (push, srcx);
1193 PUSH_DATA (push, srcx >> 32);
1194 PUSH_DATA (push, srcy);
1195 PUSH_DATA (push, srcy >> 32);
1196 }
1197 }
1198 nv50_bufctx_fence(nv50->bufctx, FALSE);
1199
1200 nouveau_bufctx_reset(nv50->bufctx, NV50_BIND_2D);
1201
1202 if (info->scissor_enable) {
1203 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
1204 PUSH_DATA (push, 0);
1205 }
1206 if (mask != 0xffffffff) {
1207 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
1208 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1209 }
1210 }
1211
1212 static void
1213 nv50_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1214 {
1215 struct nv50_context *nv50 = nv50_context(pipe);
1216 boolean eng3d = FALSE;
1217
1218 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1219 if (!(info->mask & PIPE_MASK_ZS))
1220 return;
1221 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1222 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1223 eng3d = TRUE;
1224 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1225 eng3d = TRUE;
1226 } else {
1227 if (!(info->mask & PIPE_MASK_RGBA))
1228 return;
1229 if (info->mask != PIPE_MASK_RGBA)
1230 eng3d = TRUE;
1231 }
1232
1233 if (nv50_miptree(info->src.resource)->layout_3d) {
1234 eng3d = TRUE;
1235 } else
1236 if (info->src.box.depth != info->dst.box.depth) {
1237 eng3d = TRUE;
1238 debug_printf("blit: cannot filter array or cube textures in z direction");
1239 }
1240
1241 if (!eng3d && info->dst.format != info->src.format) {
1242 if (!nv50_2d_dst_format_faithful(info->dst.format) ||
1243 !nv50_2d_src_format_faithful(info->src.format)) {
1244 eng3d = TRUE;
1245 } else
1246 if (!nv50_2d_src_format_faithful(info->src.format)) {
1247 if (!util_format_is_luminance(info->src.format)) {
1248 if (util_format_is_intensity(info->src.format))
1249 eng3d = TRUE;
1250 else
1251 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1252 eng3d = TRUE;
1253 else
1254 eng3d = !nv50_2d_format_supported(info->src.format);
1255 }
1256 } else
1257 if (util_format_is_luminance_alpha(info->src.format))
1258 eng3d = TRUE;
1259 }
1260
1261 if (info->src.resource->nr_samples == 8 &&
1262 info->dst.resource->nr_samples <= 1)
1263 eng3d = TRUE;
1264
1265 /* FIXME: can't make this work with eng2d anymore */
1266 if (info->src.resource->nr_samples > 1 ||
1267 info->dst.resource->nr_samples > 1)
1268 eng3d = TRUE;
1269
1270 /* FIXME: find correct src coordinate adjustments */
1271 if ((info->src.box.width != info->dst.box.width &&
1272 info->src.box.width != -info->dst.box.width) ||
1273 (info->src.box.height != info->dst.box.height &&
1274 info->src.box.height != -info->dst.box.height))
1275 eng3d = TRUE;
1276
1277 if (!eng3d)
1278 nv50_blit_eng2d(nv50, info);
1279 else
1280 nv50_blit_3d(nv50, info);
1281 }
1282
1283 boolean
1284 nv50_blitter_create(struct nv50_screen *screen)
1285 {
1286 screen->blitter = CALLOC_STRUCT(nv50_blitter);
1287 if (!screen->blitter) {
1288 NOUVEAU_ERR("failed to allocate blitter struct\n");
1289 return FALSE;
1290 }
1291
1292 pipe_mutex_init(screen->blitter->mutex);
1293
1294 nv50_blitter_make_vp(screen->blitter);
1295 nv50_blitter_make_sampler(screen->blitter);
1296
1297 return TRUE;
1298 }
1299
1300 void
1301 nv50_blitter_destroy(struct nv50_screen *screen)
1302 {
1303 struct nv50_blitter *blitter = screen->blitter;
1304 unsigned i, m;
1305
1306 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1307 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1308 struct nv50_program *prog = blitter->fp[i][m];
1309 if (prog) {
1310 nv50_program_destroy(NULL, prog);
1311 FREE((void *)prog->pipe.tokens);
1312 FREE(prog);
1313 }
1314 }
1315 }
1316
1317 FREE(blitter);
1318 }
1319
1320 boolean
1321 nv50_blitctx_create(struct nv50_context *nv50)
1322 {
1323 nv50->blit = CALLOC_STRUCT(nv50_blitctx);
1324 if (!nv50->blit) {
1325 NOUVEAU_ERR("failed to allocate blit context\n");
1326 return FALSE;
1327 }
1328
1329 nv50->blit->nv50 = nv50;
1330
1331 return TRUE;
1332 }
1333
1334 void
1335 nv50_init_surface_functions(struct nv50_context *nv50)
1336 {
1337 struct pipe_context *pipe = &nv50->base.pipe;
1338
1339 pipe->resource_copy_region = nv50_resource_copy_region;
1340 pipe->blit = nv50_blit;
1341 pipe->clear_render_target = nv50_clear_render_target;
1342 pipe->clear_depth_stencil = nv50_clear_depth_stencil;
1343 }
1344
1345