projects / mesa.git / blob
? search:


dc9e2880f0fd80eaf92c672b50dc896c2c5f6408
[mesa.git] / src / gallium / drivers / nv50 / nv50_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30
31 #include "nv50_context.h"
32 #include "nv50_resource.h"
33
34 #include "nv50_defs.xml.h"
35
36 /* return TRUE for formats that can be converted among each other by NV50_2D */
37 static INLINE boolean
38 nv50_2d_format_faithful(enum pipe_format format)
39 {
40 switch (format) {
41 case PIPE_FORMAT_B8G8R8A8_UNORM:
42 case PIPE_FORMAT_B8G8R8X8_UNORM:
43 case PIPE_FORMAT_B8G8R8A8_SRGB:
44 case PIPE_FORMAT_B8G8R8X8_SRGB:
45 case PIPE_FORMAT_B5G6R5_UNORM:
46 case PIPE_FORMAT_B5G5R5A1_UNORM:
47 case PIPE_FORMAT_B10G10R10A2_UNORM:
48 case PIPE_FORMAT_R8_UNORM:
49 case PIPE_FORMAT_R32G32B32A32_FLOAT:
50 case PIPE_FORMAT_R32G32B32_FLOAT:
51 return TRUE;
52 default:
53 return FALSE;
54 }
55 }
56
57 static INLINE uint8_t
58 nv50_2d_format(enum pipe_format format)
59 {
60 uint8_t id = nv50_format_table[format].rt;
61
62 /* Hardware values for color formats range from 0xc0 to 0xff,
63 * but the 2D engine doesn't support all of them.
64 */
65 if ((id >= 0xc0) && (0xff0843e080608409ULL & (1ULL << (id - 0xc0))))
66 return id;
67
68 switch (util_format_get_blocksize(format)) {
69 case 1:
70 return NV50_SURFACE_FORMAT_R8_UNORM;
71 case 2:
72 return NV50_SURFACE_FORMAT_R16_UNORM;
73 case 4:
74 return NV50_SURFACE_FORMAT_A8R8G8B8_UNORM;
75 default:
76 return 0;
77 }
78 }
79
80 static int
81 nv50_2d_texture_set(struct nouveau_channel *chan, int dst,
82 struct nv50_miptree *mt, unsigned level, unsigned layer)
83 {
84 struct nouveau_bo *bo = mt->base.bo;
85 uint32_t width, height, depth;
86 uint32_t format;
87 uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
88 uint32_t flags = mt->base.domain | (dst ? NOUVEAU_BO_WR : NOUVEAU_BO_RD);
89 uint32_t offset = mt->level[level].offset;
90
91 format = nv50_2d_format(mt->base.base.format);
92 if (!format) {
93 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
94 util_format_name(mt->base.base.format));
95 return 1;
96 }
97
98 width = u_minify(mt->base.base.width0, level);
99 height = u_minify(mt->base.base.height0, level);
100
101 offset = mt->level[level].offset;
102 if (!mt->layout_3d) {
103 offset += mt->layer_stride * layer;
104 depth = 1;
105 layer = 0;
106 } else {
107 depth = u_minify(mt->base.base.depth0, level);
108 }
109
110 if (!(bo->tile_flags & NOUVEAU_BO_TILE_LAYOUT_MASK)) {
111 BEGIN_RING(chan, RING_2D_(mthd), 2);
112 OUT_RING (chan, format);
113 OUT_RING (chan, 1);
114 BEGIN_RING(chan, RING_2D_(mthd + 0x14), 5);
115 OUT_RING (chan, mt->level[level].pitch);
116 OUT_RING (chan, width);
117 OUT_RING (chan, height);
118 OUT_RELOCh(chan, bo, offset, flags);
119 OUT_RELOCl(chan, bo, offset, flags);
120 } else {
121 BEGIN_RING(chan, RING_2D_(mthd), 5);
122 OUT_RING (chan, format);
123 OUT_RING (chan, 0);
124 OUT_RING (chan, mt->level[level].tile_mode << 4);
125 OUT_RING (chan, depth);
126 OUT_RING (chan, layer);
127 BEGIN_RING(chan, RING_2D_(mthd + 0x18), 4);
128 OUT_RING (chan, width);
129 OUT_RING (chan, height);
130 OUT_RELOCh(chan, bo, offset, flags);
131 OUT_RELOCl(chan, bo, offset, flags);
132 }
133
134 #if 0
135 if (dst) {
136 BEGIN_RING(chan, RING_2D_(NV50_2D_CLIP_X), 4);
137 OUT_RING (chan, 0);
138 OUT_RING (chan, 0);
139 OUT_RING (chan, width);
140 OUT_RING (chan, height);
141 }
142 #endif
143 return 0;
144 }
145
146 static int
147 nv50_2d_texture_do_copy(struct nouveau_channel *chan,
148 struct nv50_miptree *dst, unsigned dst_level,
149 unsigned dx, unsigned dy, unsigned dz,
150 struct nv50_miptree *src, unsigned src_level,
151 unsigned sx, unsigned sy, unsigned sz,
152 unsigned w, unsigned h)
153 {
154 int ret;
155
156 ret = MARK_RING(chan, 2 * 16 + 32, 4);
157 if (ret)
158 return ret;
159
160 ret = nv50_2d_texture_set(chan, 1, dst, dst_level, dz);
161 if (ret)
162 return ret;
163
164 ret = nv50_2d_texture_set(chan, 0, src, src_level, sz);
165 if (ret)
166 return ret;
167
168 /* 0/1 = CENTER/CORNER, 10/00 = POINT/BILINEAR */
169 BEGIN_RING(chan, RING_2D(BLIT_CONTROL), 1);
170 OUT_RING (chan, 0);
171 BEGIN_RING(chan, RING_2D(BLIT_DST_X), 4);
172 OUT_RING (chan, dx);
173 OUT_RING (chan, dy);
174 OUT_RING (chan, w);
175 OUT_RING (chan, h);
176 BEGIN_RING(chan, RING_2D(BLIT_DU_DX_FRACT), 4);
177 OUT_RING (chan, 0);
178 OUT_RING (chan, 1);
179 OUT_RING (chan, 0);
180 OUT_RING (chan, 1);
181 BEGIN_RING(chan, RING_2D(BLIT_SRC_X_FRACT), 4);
182 OUT_RING (chan, 0);
183 OUT_RING (chan, sx);
184 OUT_RING (chan, 0);
185 OUT_RING (chan, sy);
186
187 return 0;
188 }
189
190 static void
191 nv50_resource_copy_region(struct pipe_context *pipe,
192 struct pipe_resource *dst, unsigned dst_level,
193 unsigned dstx, unsigned dsty, unsigned dstz,
194 struct pipe_resource *src, unsigned src_level,
195 const struct pipe_box *src_box)
196 {
197 struct nv50_screen *screen = nv50_context(pipe)->screen;
198 int ret;
199 unsigned dst_layer = dstz, src_layer = src_box->z;
200
201 assert((src->format == dst->format) ||
202 (nv50_2d_format_faithful(src->format) &&
203 nv50_2d_format_faithful(dst->format)));
204
205 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
206 ret = nv50_2d_texture_do_copy(screen->base.channel,
207 nv50_miptree(dst), dst_level,
208 dstx, dsty, dst_layer,
209 nv50_miptree(src), src_level,
210 src_box->x, src_box->y, src_layer,
211 src_box->width, src_box->height);
212 if (ret)
213 return;
214 }
215 }
216
217 static void
218 nv50_clear_render_target(struct pipe_context *pipe,
219 struct pipe_surface *dst,
220 const float *rgba,
221 unsigned dstx, unsigned dsty,
222 unsigned width, unsigned height)
223 {
224 struct nv50_context *nv50 = nv50_context(pipe);
225 struct nv50_screen *screen = nv50->screen;
226 struct nouveau_channel *chan = screen->base.channel;
227 struct nv50_miptree *mt = nv50_miptree(dst->texture);
228 struct nv50_surface *sf = nv50_surface(dst);
229 struct nouveau_bo *bo = mt->base.bo;
230
231 BEGIN_RING(chan, RING_3D(CLEAR_COLOR(0)), 4);
232 OUT_RINGf (chan, rgba[0]);
233 OUT_RINGf (chan, rgba[1]);
234 OUT_RINGf (chan, rgba[2]);
235 OUT_RINGf (chan, rgba[3]);
236
237 if (MARK_RING(chan, 18, 2))
238 return;
239
240 BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
241 OUT_RING (chan, 1);
242 BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(0)), 5);
243 OUT_RELOCh(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
244 OUT_RELOCl(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
245 OUT_RING (chan, nv50_format_table[dst->format].rt);
246 OUT_RING (chan, mt->level[sf->base.u.tex.level].tile_mode << 4);
247 OUT_RING (chan, 0);
248 BEGIN_RING(chan, RING_3D(RT_HORIZ(0)), 2);
249 OUT_RING (chan, sf->width);
250 OUT_RING (chan, sf->height);
251 BEGIN_RING(chan, RING_3D(RT_ARRAY_MODE), 1);
252 OUT_RING (chan, 1);
253
254 /* NOTE: only works with D3D clear flag (5097/0x143c bit 4) */
255
256 BEGIN_RING(chan, RING_3D(VIEWPORT_HORIZ(0)), 2);
257 OUT_RING (chan, (width << 16) | dstx);
258 OUT_RING (chan, (height << 16) | dsty);
259
260 BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
261 OUT_RING (chan, 0x3c);
262
263 nv50->dirty |= NV50_NEW_FRAMEBUFFER;
264 }
265
266 static void
267 nv50_clear_depth_stencil(struct pipe_context *pipe,
268 struct pipe_surface *dst,
269 unsigned clear_flags,
270 double depth,
271 unsigned stencil,
272 unsigned dstx, unsigned dsty,
273 unsigned width, unsigned height)
274 {
275 struct nv50_context *nv50 = nv50_context(pipe);
276 struct nv50_screen *screen = nv50->screen;
277 struct nouveau_channel *chan = screen->base.channel;
278 struct nv50_miptree *mt = nv50_miptree(dst->texture);
279 struct nv50_surface *sf = nv50_surface(dst);
280 struct nouveau_bo *bo = mt->base.bo;
281 uint32_t mode = 0;
282
283 if (clear_flags & PIPE_CLEAR_DEPTH) {
284 BEGIN_RING(chan, RING_3D(CLEAR_DEPTH), 1);
285 OUT_RINGf (chan, depth);
286 mode |= NV50_3D_CLEAR_BUFFERS_Z;
287 }
288
289 if (clear_flags & PIPE_CLEAR_STENCIL) {
290 BEGIN_RING(chan, RING_3D(CLEAR_STENCIL), 1);
291 OUT_RING (chan, stencil & 0xff);
292 mode |= NV50_3D_CLEAR_BUFFERS_S;
293 }
294
295 if (MARK_RING(chan, 17, 2))
296 return;
297
298 BEGIN_RING(chan, RING_3D(ZETA_ADDRESS_HIGH), 5);
299 OUT_RELOCh(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
300 OUT_RELOCl(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
301 OUT_RING (chan, nv50_format_table[dst->format].rt);
302 OUT_RING (chan, mt->level[sf->base.u.tex.level].tile_mode << 4);
303 OUT_RING (chan, 0);
304 BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
305 OUT_RING (chan, 1);
306 BEGIN_RING(chan, RING_3D(ZETA_HORIZ), 3);
307 OUT_RING (chan, sf->width);
308 OUT_RING (chan, sf->height);
309 OUT_RING (chan, (1 << 16) | 1);
310
311 BEGIN_RING(chan, RING_3D(VIEWPORT_HORIZ(0)), 2);
312 OUT_RING (chan, (width << 16) | dstx);
313 OUT_RING (chan, (height << 16) | dsty);
314
315 BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
316 OUT_RING (chan, mode);
317
318 nv50->dirty |= NV50_NEW_FRAMEBUFFER;
319 }
320
321 void
322 nv50_clear(struct pipe_context *pipe, unsigned buffers,
323 const float *rgba, double depth, unsigned stencil)
324 {
325 struct nv50_context *nv50 = nv50_context(pipe);
326 struct nouveau_channel *chan = nv50->screen->base.channel;
327 struct pipe_framebuffer_state *fb = &nv50->framebuffer;
328 unsigned i;
329 const unsigned dirty = nv50->dirty;
330 uint32_t mode = 0;
331
332 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
333 nv50->dirty &= NV50_NEW_FRAMEBUFFER;
334 if (!nv50_state_validate(nv50))
335 return;
336
337 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
338 BEGIN_RING(chan, RING_3D(CLEAR_COLOR(0)), 4);
339 OUT_RINGf (chan, rgba[0]);
340 OUT_RINGf (chan, rgba[1]);
341 OUT_RINGf (chan, rgba[2]);
342 OUT_RINGf (chan, rgba[3]);
343 mode =
344 NV50_3D_CLEAR_BUFFERS_R | NV50_3D_CLEAR_BUFFERS_G |
345 NV50_3D_CLEAR_BUFFERS_B | NV50_3D_CLEAR_BUFFERS_A;
346 }
347
348 if (buffers & PIPE_CLEAR_DEPTH) {
349 BEGIN_RING(chan, RING_3D(CLEAR_DEPTH), 1);
350 OUT_RING (chan, fui(depth));
351 mode |= NV50_3D_CLEAR_BUFFERS_Z;
352 }
353
354 if (buffers & PIPE_CLEAR_STENCIL) {
355 BEGIN_RING(chan, RING_3D(CLEAR_STENCIL), 1);
356 OUT_RING (chan, stencil & 0xff);
357 mode |= NV50_3D_CLEAR_BUFFERS_S;
358 }
359
360 BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
361 OUT_RING (chan, mode);
362
363 for (i = 1; i < fb->nr_cbufs; i++) {
364 BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
365 OUT_RING (chan, (i << 6) | 0x3c);
366 }
367
368 nv50->dirty = dirty & ~NV50_NEW_FRAMEBUFFER;
369 }
370
371 void
372 nv50_init_surface_functions(struct nv50_context *nv50)
373 {
374 struct pipe_context *pipe = &nv50->base.pipe;
375
376 pipe->resource_copy_region = nv50_resource_copy_region;
377 pipe->clear_render_target = nv50_clear_render_target;
378 pipe->clear_depth_stencil = nv50_clear_depth_stencil;
379 }
380
381