Merge remote branch 'upstream/gallium-0.1' into nouveau-gallium-0.1
[mesa.git] / src / gallium / drivers / nv50 / nv50_tex.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "nv50_context.h"
24 #include "nv50_texture.h"
25
26 #include "nouveau/nouveau_stateobj.h"
27
28 static int
29 nv50_tex_construct(struct nouveau_stateobj *so, struct nv50_miptree *mt)
30 {
31 switch (mt->base.format) {
32 case PIPE_FORMAT_A8R8G8B8_UNORM:
33 so_data(so, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
34 NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
35 NV50TIC_0_0_MAPG_C1 | NV50TIC_0_0_TYPEG_UNORM |
36 NV50TIC_0_0_MAPB_C2 | NV50TIC_0_0_TYPEB_UNORM |
37 NV50TIC_0_0_FMT_8_8_8_8);
38 break;
39 case PIPE_FORMAT_A1R5G5B5_UNORM:
40 so_data(so, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
41 NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
42 NV50TIC_0_0_MAPG_C1 | NV50TIC_0_0_TYPEG_UNORM |
43 NV50TIC_0_0_MAPB_C2 | NV50TIC_0_0_TYPEB_UNORM |
44 NV50TIC_0_0_FMT_1_5_5_5);
45 break;
46 case PIPE_FORMAT_A4R4G4B4_UNORM:
47 so_data(so, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
48 NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
49 NV50TIC_0_0_MAPG_C1 | NV50TIC_0_0_TYPEG_UNORM |
50 NV50TIC_0_0_MAPB_C2 | NV50TIC_0_0_TYPEB_UNORM |
51 NV50TIC_0_0_FMT_4_4_4_4);
52 break;
53 case PIPE_FORMAT_R5G6B5_UNORM:
54 so_data(so, NV50TIC_0_0_MAPA_ONE | NV50TIC_0_0_TYPEA_UNORM |
55 NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
56 NV50TIC_0_0_MAPG_C1 | NV50TIC_0_0_TYPEG_UNORM |
57 NV50TIC_0_0_MAPB_C2 | NV50TIC_0_0_TYPEB_UNORM |
58 NV50TIC_0_0_FMT_5_6_5);
59 break;
60 case PIPE_FORMAT_L8_UNORM:
61 so_data(so, NV50TIC_0_0_MAPA_ONE | NV50TIC_0_0_TYPEA_UNORM |
62 NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
63 NV50TIC_0_0_MAPG_C0 | NV50TIC_0_0_TYPEG_UNORM |
64 NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
65 NV50TIC_0_0_FMT_8);
66 break;
67 case PIPE_FORMAT_A8_UNORM:
68 so_data(so, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
69 NV50TIC_0_0_MAPR_ZERO | NV50TIC_0_0_TYPER_UNORM |
70 NV50TIC_0_0_MAPG_ZERO | NV50TIC_0_0_TYPEG_UNORM |
71 NV50TIC_0_0_MAPB_ZERO | NV50TIC_0_0_TYPEB_UNORM |
72 NV50TIC_0_0_FMT_8);
73 break;
74 case PIPE_FORMAT_I8_UNORM:
75 so_data(so, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
76 NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
77 NV50TIC_0_0_MAPG_C0 | NV50TIC_0_0_TYPEG_UNORM |
78 NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
79 NV50TIC_0_0_FMT_8);
80 break;
81 case PIPE_FORMAT_A8L8_UNORM:
82 so_data(so, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
83 NV50TIC_0_0_MAPR_C0 | NV50TIC_0_0_TYPER_UNORM |
84 NV50TIC_0_0_MAPG_C0 | NV50TIC_0_0_TYPEG_UNORM |
85 NV50TIC_0_0_MAPB_C0 | NV50TIC_0_0_TYPEB_UNORM |
86 NV50TIC_0_0_FMT_8_8);
87 break;
88 default:
89 return 1;
90 }
91
92 so_reloc(so, mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_LOW, 0, 0);
93 so_data (so, 0xd0005000);
94 so_data (so, 0x00300000);
95 so_data (so, mt->base.width[0]);
96 so_data (so, (mt->base.depth[0] << 16) | mt->base.height[0]);
97 so_data (so, 0x03000000);
98 so_reloc(so, mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_HIGH, 0, 0);
99
100 return 0;
101 }
102
103 void
104 nv50_tex_validate(struct nv50_context *nv50)
105 {
106 struct nouveau_grobj *tesla = nv50->screen->tesla;
107 struct nouveau_stateobj *so;
108 int i;
109
110 so = so_new(nv50->miptree_nr * 8 + 3, nv50->miptree_nr * 2);
111 so_method(so, tesla, 0x0f00, 1);
112 so_data (so, NV50_CB_TIC);
113 so_method(so, tesla, 0x40000f04, nv50->miptree_nr * 8);
114 for (i = 0; i < nv50->miptree_nr; i++) {
115 if (nv50_tex_construct(so, nv50->miptree[i])) {
116 NOUVEAU_ERR("failed tex validate\n");
117 so_ref(NULL, &so);
118 return;
119 }
120 }
121
122 so_ref(so, &nv50->state.tic_upload);
123 }
124