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[mesa.git] / src / gallium / drivers / nv50 / nv50_tgsi_to_nc.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 /* XXX: need to clean this up so we get the typecasting right more naturally */
24
25 #include <unistd.h>
26
27 #include "nv50_context.h"
28 #include "nv50_pc.h"
29
30 #include "pipe/p_shader_tokens.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_util.h"
33
34 #include "util/u_simple_list.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #define BLD_MAX_TEMPS 64
38 #define BLD_MAX_ADDRS 4
39 #define BLD_MAX_PREDS 4
40 #define BLD_MAX_IMMDS 128
41
42 #define BLD_MAX_COND_NESTING 4
43 #define BLD_MAX_LOOP_NESTING 4
44 #define BLD_MAX_CALL_NESTING 2
45
46 /* collects all values assigned to the same TGSI register */
47 struct bld_value_stack {
48 struct nv_value *top;
49 struct nv_value **body;
50 unsigned size;
51 uint16_t loop_use; /* 1 bit per loop level, indicates if used/defd */
52 uint16_t loop_def;
53 };
54
55 static INLINE void
56 bld_vals_push_val(struct bld_value_stack *stk, struct nv_value *val)
57 {
58 assert(!stk->size || (stk->body[stk->size - 1] != val));
59
60 if (!(stk->size % 8)) {
61 unsigned old_sz = (stk->size + 0) * sizeof(struct nv_value *);
62 unsigned new_sz = (stk->size + 8) * sizeof(struct nv_value *);
63 stk->body = (struct nv_value **)REALLOC(stk->body, old_sz, new_sz);
64 }
65 stk->body[stk->size++] = val;
66 }
67
68 static INLINE boolean
69 bld_vals_del_val(struct bld_value_stack *stk, struct nv_value *val)
70 {
71 unsigned i;
72
73 for (i = stk->size - 1; i >= 0; --i)
74 if (stk->body[i] == val)
75 break;
76 if (i < 0)
77 return FALSE;
78
79 if (i != stk->size - 1)
80 stk->body[i] = stk->body[stk->size - 1];
81
82 --stk->size; /* XXX: old size in REALLOC */
83 return TRUE;
84 }
85
86 static INLINE void
87 bld_vals_push(struct bld_value_stack *stk)
88 {
89 bld_vals_push_val(stk, stk->top);
90 stk->top = NULL;
91 }
92
93 static INLINE void
94 bld_push_values(struct bld_value_stack *stacks, int n)
95 {
96 int i, c;
97
98 for (i = 0; i < n; ++i)
99 for (c = 0; c < 4; ++c)
100 if (stacks[i * 4 + c].top)
101 bld_vals_push(&stacks[i * 4 + c]);
102 }
103
104 struct bld_context {
105 struct nv50_translation_info *ti;
106
107 struct nv_pc *pc;
108 struct nv_basic_block *b;
109
110 struct tgsi_parse_context parse[BLD_MAX_CALL_NESTING];
111 int call_lvl;
112
113 struct nv_basic_block *cond_bb[BLD_MAX_COND_NESTING];
114 struct nv_basic_block *join_bb[BLD_MAX_COND_NESTING];
115 struct nv_basic_block *else_bb[BLD_MAX_COND_NESTING];
116 int cond_lvl;
117 struct nv_basic_block *loop_bb[BLD_MAX_LOOP_NESTING];
118 struct nv_basic_block *brkt_bb[BLD_MAX_LOOP_NESTING];
119 int loop_lvl;
120
121 struct bld_value_stack tvs[BLD_MAX_TEMPS][4]; /* TGSI_FILE_TEMPORARY */
122 struct bld_value_stack avs[BLD_MAX_ADDRS][4]; /* TGSI_FILE_ADDRESS */
123 struct bld_value_stack pvs[BLD_MAX_PREDS][4]; /* TGSI_FILE_PREDICATE */
124 struct bld_value_stack ovs[PIPE_MAX_SHADER_OUTPUTS][4];
125
126 uint32_t outputs_written[(PIPE_MAX_SHADER_OUTPUTS + 31) / 32];
127
128 struct nv_value *frgcrd[4];
129 struct nv_value *sysval[4];
130
131 /* wipe on new BB */
132 struct nv_value *saved_addr[4][2];
133 struct nv_value *saved_inputs[128];
134 struct nv_value *saved_immd[BLD_MAX_IMMDS];
135 uint num_immds;
136 };
137
138 static INLINE ubyte
139 bld_stack_file(struct bld_context *bld, struct bld_value_stack *stk)
140 {
141 if (stk < &bld->avs[0][0])
142 return NV_FILE_GPR;
143 else
144 if (stk < &bld->pvs[0][0])
145 return NV_FILE_ADDR;
146 else
147 if (stk < &bld->ovs[0][0])
148 return NV_FILE_FLAGS;
149 else
150 return NV_FILE_OUT;
151 }
152
153 static INLINE struct nv_value *
154 bld_fetch(struct bld_context *bld, struct bld_value_stack *stk, int i, int c)
155 {
156 stk[i * 4 + c].loop_use |= 1 << bld->loop_lvl;
157
158 return stk[i * 4 + c].top;
159 }
160
161 static struct nv_value *
162 bld_loop_phi(struct bld_context *, struct bld_value_stack *, struct nv_value *);
163
164 /* If a variable is defined in a loop without prior use, we don't need
165 * a phi in the loop header to account for backwards flow.
166 *
167 * However, if this variable is then also used outside the loop, we do
168 * need a phi after all. But we must not use this phi's def inside the
169 * loop, so we can eliminate the phi if it is unused later.
170 */
171 static INLINE void
172 bld_store(struct bld_context *bld, struct bld_value_stack *stk, int i, int c,
173 struct nv_value *val)
174 {
175 const uint16_t m = 1 << bld->loop_lvl;
176
177 stk = &stk[i * 4 + c];
178
179 if (bld->loop_lvl && !(m & (stk->loop_def | stk->loop_use)))
180 bld_loop_phi(bld, stk, val);
181
182 stk->top = val;
183 stk->loop_def |= 1 << bld->loop_lvl;
184 }
185
186 static INLINE void
187 bld_clear_def_use(struct bld_value_stack *stk, int n, int lvl)
188 {
189 int i;
190 const uint16_t mask = ~(1 << lvl);
191
192 for (i = 0; i < n * 4; ++i) {
193 stk[i].loop_def &= mask;
194 stk[i].loop_use &= mask;
195 }
196 }
197
198 #define FETCH_TEMP(i, c) bld_fetch(bld, &bld->tvs[0][0], i, c)
199 #define STORE_TEMP(i, c, v) bld_store(bld, &bld->tvs[0][0], i, c, (v))
200 #define FETCH_ADDR(i, c) bld_fetch(bld, &bld->avs[0][0], i, c)
201 #define STORE_ADDR(i, c, v) bld_store(bld, &bld->avs[0][0], i, c, (v))
202 #define FETCH_PRED(i, c) bld_fetch(bld, &bld->pvs[0][0], i, c)
203 #define STORE_PRED(i, c, v) bld_store(bld, &bld->pvs[0][0], i, c, (v))
204
205 #define STORE_OUTR(i, c, v) \
206 do { \
207 bld->ovs[i][c].top = (v); \
208 bld->outputs_written[(i) / 8] |= 1 << (((i) * 4 + (c)) % 32); \
209 } while (0)
210
211 static INLINE void
212 bld_warn_uninitialized(struct bld_context *bld, int kind,
213 struct bld_value_stack *stk, struct nv_basic_block *b)
214 {
215 long i = (stk - &bld->tvs[0][0]) / 4;
216 long c = (stk - &bld->tvs[0][0]) & 3;
217
218 if (c == 3)
219 c = -1;
220
221 debug_printf("WARNING: TEMP[%li].%c %s used uninitialized in BB:%i\n",
222 i, (int)('x' + c), kind ? "may be" : "is", b->id);
223 }
224
225 static INLINE struct nv_value *
226 bld_def(struct nv_instruction *i, int c, struct nv_value *value)
227 {
228 i->def[c] = value;
229 value->insn = i;
230 return value;
231 }
232
233 static INLINE struct nv_value *
234 find_by_bb(struct bld_value_stack *stack, struct nv_basic_block *b)
235 {
236 int i;
237
238 if (stack->top && stack->top->insn->bb == b)
239 return stack->top;
240
241 for (i = stack->size - 1; i >= 0; --i)
242 if (stack->body[i]->insn->bb == b)
243 return stack->body[i];
244 return NULL;
245 }
246
247 /* fetch value from stack that was defined in the specified basic block,
248 * or search for first definitions in all of its predecessors
249 */
250 static void
251 fetch_by_bb(struct bld_value_stack *stack,
252 struct nv_value **vals, int *n,
253 struct nv_basic_block *b)
254 {
255 int i;
256 struct nv_value *val;
257
258 assert(*n < 16); /* MAX_COND_NESTING */
259
260 val = find_by_bb(stack, b);
261 if (val) {
262 for (i = 0; i < *n; ++i)
263 if (vals[i] == val)
264 return;
265 vals[(*n)++] = val;
266 return;
267 }
268 for (i = 0; i < b->num_in; ++i)
269 if (b->in_kind[i] != CFG_EDGE_BACK)
270 fetch_by_bb(stack, vals, n, b->in[i]);
271 }
272
273 static INLINE struct nv_value *
274 bld_load_imm_u32(struct bld_context *bld, uint32_t u);
275
276 static INLINE struct nv_value *
277 bld_undef(struct bld_context *bld, ubyte file)
278 {
279 struct nv_instruction *nvi = new_instruction(bld->pc, NV_OP_UNDEF);
280
281 return bld_def(nvi, 0, new_value(bld->pc, file, NV_TYPE_U32));
282 }
283
284 static struct nv_value *
285 bld_phi(struct bld_context *bld, struct nv_basic_block *b,
286 struct bld_value_stack *stack)
287 {
288 struct nv_basic_block *in;
289 struct nv_value *vals[16], *val;
290 struct nv_instruction *phi;
291 int i, j, n;
292
293 do {
294 i = n = 0;
295 fetch_by_bb(stack, vals, &n, b);
296
297 if (!n) {
298 bld_warn_uninitialized(bld, 0, stack, b);
299 return NULL;
300 }
301
302 if (n == 1) {
303 if (nvbb_dominated_by(b, vals[0]->insn->bb))
304 break;
305
306 bld_warn_uninitialized(bld, 1, stack, b);
307
308 /* back-tracking to insert missing value of other path */
309 in = b;
310 while (in->in[0]) {
311 if (in->num_in == 1) {
312 in = in->in[0];
313 } else {
314 if (!nvbb_reachable_by(in->in[0], vals[0]->insn->bb, b))
315 in = in->in[0];
316 else
317 if (!nvbb_reachable_by(in->in[1], vals[0]->insn->bb, b))
318 in = in->in[1];
319 else
320 in = in->in[0];
321 }
322 }
323 bld->pc->current_block = in;
324
325 /* should make this a no-op */
326 bld_vals_push_val(stack, bld_undef(bld, vals[0]->reg.file));
327 continue;
328 }
329
330 for (i = 0; i < n; ++i) {
331 /* if value dominates b, continue to the redefinitions */
332 if (nvbb_dominated_by(b, vals[i]->insn->bb))
333 continue;
334
335 /* if value dominates any in-block, b should be the dom frontier */
336 for (j = 0; j < b->num_in; ++j)
337 if (nvbb_dominated_by(b->in[j], vals[i]->insn->bb))
338 break;
339 /* otherwise, find the dominance frontier and put the phi there */
340 if (j == b->num_in) {
341 in = nvbb_dom_frontier(vals[i]->insn->bb);
342 val = bld_phi(bld, in, stack);
343 bld_vals_push_val(stack, val);
344 break;
345 }
346 }
347 } while(i < n);
348
349 bld->pc->current_block = b;
350
351 if (n == 1)
352 return vals[0];
353
354 phi = new_instruction(bld->pc, NV_OP_PHI);
355
356 bld_def(phi, 0, new_value(bld->pc, vals[0]->reg.file, vals[0]->reg.type));
357 for (i = 0; i < n; ++i)
358 phi->src[i] = new_ref(bld->pc, vals[i]);
359
360 return phi->def[0];
361 }
362
363 static struct nv_value *
364 bld_loop_phi(struct bld_context *bld, struct bld_value_stack *stack,
365 struct nv_value *def)
366 {
367 struct nv_basic_block *bb = bld->pc->current_block;
368 struct nv_instruction *phi;
369 struct nv_value *val;
370
371 val = bld_phi(bld, bld->pc->current_block, stack);
372 if (!val) {
373 bld->pc->current_block = bld->loop_bb[bld->loop_lvl - 1]->in[0];
374
375 val = bld_undef(bld, bld_stack_file(bld, stack));
376 }
377
378 bld->pc->current_block = bld->loop_bb[bld->loop_lvl - 1];
379
380 phi = new_instruction(bld->pc, NV_OP_PHI);
381
382 bld_def(phi, 0, new_value_like(bld->pc, val));
383 if (!def)
384 def = phi->def[0];
385
386 bld_vals_push_val(stack, phi->def[0]);
387
388 phi->target = (struct nv_basic_block *)stack; /* cheat */
389
390 nv_reference(bld->pc, &phi->src[0], val);
391 nv_reference(bld->pc, &phi->src[1], def);
392
393 bld->pc->current_block = bb;
394
395 return phi->def[0];
396 }
397
398 static INLINE struct nv_value *
399 bld_fetch_global(struct bld_context *bld, struct bld_value_stack *stack)
400 {
401 const uint16_t m = 1 << bld->loop_lvl;
402 const uint16_t use = stack->loop_use;
403
404 stack->loop_use |= m;
405
406 /* If neither used nor def'd inside the loop, build a phi in foresight,
407 * so we don't have to replace stuff later on, which requires tracking.
408 */
409 if (bld->loop_lvl && !((use | stack->loop_def) & m))
410 return bld_loop_phi(bld, stack, NULL);
411
412 return bld_phi(bld, bld->pc->current_block, stack);
413 }
414
415 static INLINE struct nv_value *
416 bld_imm_u32(struct bld_context *bld, uint32_t u)
417 {
418 int i;
419 unsigned n = bld->num_immds;
420
421 for (i = 0; i < n; ++i)
422 if (bld->saved_immd[i]->reg.imm.u32 == u)
423 return bld->saved_immd[i];
424 assert(n < BLD_MAX_IMMDS);
425
426 bld->num_immds++;
427
428 bld->saved_immd[n] = new_value(bld->pc, NV_FILE_IMM, NV_TYPE_U32);
429 bld->saved_immd[n]->reg.imm.u32 = u;
430 return bld->saved_immd[n];
431 }
432
433 static void
434 bld_replace_value(struct nv_pc *, struct nv_basic_block *, struct nv_value *,
435 struct nv_value *);
436
437 /* Replace the source of the phi in the loop header by the last assignment,
438 * or eliminate the phi function if there is no assignment inside the loop.
439 *
440 * Redundancy situation 1 - (used) but (not redefined) value:
441 * %3 = phi %0, %3 = %3 is used
442 * %3 = phi %0, %4 = is new definition
443 *
444 * Redundancy situation 2 - (not used) but (redefined) value:
445 * %3 = phi %0, %2 = %2 is used, %3 could be used outside, deleted by DCE
446 */
447 static void
448 bld_loop_end(struct bld_context *bld, struct nv_basic_block *bb)
449 {
450 struct nv_instruction *phi, *next;
451 struct nv_value *val;
452 struct bld_value_stack *stk;
453 int s;
454
455 for (phi = bb->phi; phi && phi->opcode == NV_OP_PHI; phi = next) {
456 next = phi->next;
457
458 stk = (struct bld_value_stack *)phi->target;
459 phi->target = NULL;
460
461 val = bld_fetch_global(bld, stk);
462
463 nv_reference(bld->pc, &phi->src[1], val);
464
465 s = -1;
466 if (phi->src[0]->value == phi->def[0] ||
467 phi->src[0]->value == phi->src[1]->value)
468 s = 1;
469 else
470 if (phi->src[1]->value == phi->def[0])
471 s = 0;
472
473 if (s >= 0) {
474 bld_vals_del_val(stk, phi->def[0]);
475
476 ++bld->pc->pass_seq;
477 bld_replace_value(bld->pc, bb, phi->def[0], phi->src[s]->value);
478
479 nv_nvi_delete(phi);
480 }
481 }
482 }
483
484 static INLINE struct nv_value *
485 bld_imm_f32(struct bld_context *bld, float f)
486 {
487 return bld_imm_u32(bld, fui(f));
488 }
489
490 #define SET_TYPE(v, t) ((v)->reg.type = NV_TYPE_##t)
491
492 static struct nv_value *
493 bld_insn_1(struct bld_context *bld, uint opcode, struct nv_value *src0)
494 {
495 struct nv_instruction *insn = new_instruction(bld->pc, opcode);
496 assert(insn);
497
498 nv_reference(bld->pc, &insn->src[0], src0); /* NOTE: new_ref would suffice */
499
500 return bld_def(insn, 0, new_value(bld->pc, NV_FILE_GPR, src0->reg.type));
501 }
502
503 static struct nv_value *
504 bld_insn_2(struct bld_context *bld, uint opcode,
505 struct nv_value *src0, struct nv_value *src1)
506 {
507 struct nv_instruction *insn = new_instruction(bld->pc, opcode);
508
509 nv_reference(bld->pc, &insn->src[0], src0);
510 nv_reference(bld->pc, &insn->src[1], src1);
511
512 return bld_def(insn, 0, new_value(bld->pc, NV_FILE_GPR, src0->reg.type));
513 }
514
515 static struct nv_value *
516 bld_insn_3(struct bld_context *bld, uint opcode,
517 struct nv_value *src0, struct nv_value *src1,
518 struct nv_value *src2)
519 {
520 struct nv_instruction *insn = new_instruction(bld->pc, opcode);
521
522 nv_reference(bld->pc, &insn->src[0], src0);
523 nv_reference(bld->pc, &insn->src[1], src1);
524 nv_reference(bld->pc, &insn->src[2], src2);
525
526 return bld_def(insn, 0, new_value(bld->pc, NV_FILE_GPR, src0->reg.type));
527 }
528
529 #define BLD_INSN_1_EX(d, op, dt, s0, s0t) \
530 do { \
531 (d) = bld_insn_1(bld, (NV_OP_##op), (s0)); \
532 (d)->reg.type = NV_TYPE_##dt; \
533 (d)->insn->src[0]->typecast = NV_TYPE_##s0t; \
534 } while(0)
535
536 #define BLD_INSN_2_EX(d, op, dt, s0, s0t, s1, s1t) \
537 do { \
538 (d) = bld_insn_2(bld, (NV_OP_##op), (s0), (s1)); \
539 (d)->reg.type = NV_TYPE_##dt; \
540 (d)->insn->src[0]->typecast = NV_TYPE_##s0t; \
541 (d)->insn->src[1]->typecast = NV_TYPE_##s1t; \
542 } while(0)
543
544 static struct nv_value *
545 bld_pow(struct bld_context *bld, struct nv_value *x, struct nv_value *e)
546 {
547 struct nv_value *val;
548
549 BLD_INSN_1_EX(val, LG2, F32, x, F32);
550 BLD_INSN_2_EX(val, MUL, F32, e, F32, val, F32);
551 val = bld_insn_1(bld, NV_OP_PREEX2, val);
552 val = bld_insn_1(bld, NV_OP_EX2, val);
553
554 return val;
555 }
556
557 static INLINE struct nv_value *
558 bld_load_imm_f32(struct bld_context *bld, float f)
559 {
560 return bld_insn_1(bld, NV_OP_MOV, bld_imm_f32(bld, f));
561 }
562
563 static INLINE struct nv_value *
564 bld_load_imm_u32(struct bld_context *bld, uint32_t u)
565 {
566 return bld_insn_1(bld, NV_OP_MOV, bld_imm_u32(bld, u));
567 }
568
569 static struct nv_value *
570 bld_get_address(struct bld_context *bld, int id, struct nv_value *indirect)
571 {
572 int i;
573 struct nv_instruction *nvi;
574
575 for (i = 0; i < 4; ++i) {
576 if (!bld->saved_addr[i][0])
577 break;
578 if (bld->saved_addr[i][1] == indirect) {
579 nvi = bld->saved_addr[i][0]->insn;
580 if (nvi->src[0]->value->reg.imm.u32 == id)
581 return bld->saved_addr[i][0];
582 }
583 }
584 i &= 3;
585
586 bld->saved_addr[i][0] = bld_load_imm_u32(bld, id);
587 bld->saved_addr[i][0]->reg.file = NV_FILE_ADDR;
588 bld->saved_addr[i][1] = indirect;
589 return bld->saved_addr[i][0];
590 }
591
592
593 static struct nv_value *
594 bld_predicate(struct bld_context *bld, struct nv_value *src, boolean bool_only)
595 {
596 struct nv_instruction *nvi = src->insn;
597
598 if (nvi->opcode == NV_OP_LDA ||
599 nvi->opcode == NV_OP_PHI ||
600 nvi->bb != bld->pc->current_block) {
601 nvi = new_instruction(bld->pc, NV_OP_CVT);
602 nv_reference(bld->pc, &nvi->src[0], src);
603 } else
604 if (bool_only) {
605 while (nvi->opcode == NV_OP_ABS || nvi->opcode == NV_OP_CVT ||
606 nvi->opcode == NV_OP_NEG) {
607 /* TGSI SET gets conversion to f32, we only need source 0/~0 */
608 if (!nvi->def[0]->insn->flags_src)
609 nvi = nvi->src[0]->value->insn;
610 }
611 }
612
613 if (!nvi->flags_def) {
614 nvi->flags_def = new_value(bld->pc, NV_FILE_FLAGS, NV_TYPE_U16);
615 nvi->flags_def->insn = nvi;
616 }
617 return nvi->flags_def;
618 }
619
620 static void
621 bld_kil(struct bld_context *bld, struct nv_value *src)
622 {
623 struct nv_instruction *nvi;
624
625 src = bld_predicate(bld, src, FALSE);
626 nvi = new_instruction(bld->pc, NV_OP_KIL);
627 nvi->fixed = 1;
628 nvi->flags_src = new_ref(bld->pc, src);
629 nvi->cc = NV_CC_LT;
630 }
631
632 static void
633 bld_flow(struct bld_context *bld, uint opcode, ubyte cc,
634 struct nv_value *src, struct nv_basic_block *target,
635 boolean plan_reconverge)
636 {
637 struct nv_instruction *nvi;
638
639 if (plan_reconverge)
640 new_instruction(bld->pc, NV_OP_JOINAT)->fixed = 1;
641
642 nvi = new_instruction(bld->pc, opcode);
643 nvi->is_terminator = 1;
644 nvi->cc = cc;
645 nvi->target = target;
646 if (src)
647 nvi->flags_src = new_ref(bld->pc, src);
648 }
649
650 static ubyte
651 translate_setcc(unsigned opcode)
652 {
653 switch (opcode) {
654 case TGSI_OPCODE_SLT: return NV_CC_LT;
655 case TGSI_OPCODE_SGE: return NV_CC_GE;
656 case TGSI_OPCODE_SEQ: return NV_CC_EQ;
657 case TGSI_OPCODE_SGT: return NV_CC_GT;
658 case TGSI_OPCODE_SLE: return NV_CC_LE;
659 case TGSI_OPCODE_SNE: return NV_CC_NE | NV_CC_U;
660 case TGSI_OPCODE_STR: return NV_CC_TR;
661 case TGSI_OPCODE_SFL: return NV_CC_FL;
662
663 case TGSI_OPCODE_ISLT: return NV_CC_LT;
664 case TGSI_OPCODE_ISGE: return NV_CC_GE;
665 case TGSI_OPCODE_USEQ: return NV_CC_EQ;
666 case TGSI_OPCODE_USGE: return NV_CC_GE;
667 case TGSI_OPCODE_USLT: return NV_CC_LT;
668 case TGSI_OPCODE_USNE: return NV_CC_NE;
669 default:
670 assert(0);
671 return NV_CC_FL;
672 }
673 }
674
675 static uint
676 translate_opcode(uint opcode)
677 {
678 switch (opcode) {
679 case TGSI_OPCODE_ABS: return NV_OP_ABS;
680 case TGSI_OPCODE_ADD:
681 case TGSI_OPCODE_SUB:
682 case TGSI_OPCODE_UADD: return NV_OP_ADD;
683 case TGSI_OPCODE_AND: return NV_OP_AND;
684 case TGSI_OPCODE_EX2: return NV_OP_EX2;
685 case TGSI_OPCODE_CEIL: return NV_OP_CEIL;
686 case TGSI_OPCODE_FLR: return NV_OP_FLOOR;
687 case TGSI_OPCODE_TRUNC: return NV_OP_TRUNC;
688 case TGSI_OPCODE_DDX: return NV_OP_DFDX;
689 case TGSI_OPCODE_DDY: return NV_OP_DFDY;
690 case TGSI_OPCODE_F2I:
691 case TGSI_OPCODE_F2U:
692 case TGSI_OPCODE_I2F:
693 case TGSI_OPCODE_U2F: return NV_OP_CVT;
694 case TGSI_OPCODE_INEG: return NV_OP_NEG;
695 case TGSI_OPCODE_LG2: return NV_OP_LG2;
696 case TGSI_OPCODE_ISHR:
697 case TGSI_OPCODE_USHR: return NV_OP_SHR;
698 case TGSI_OPCODE_MAD:
699 case TGSI_OPCODE_UMAD: return NV_OP_MAD;
700 case TGSI_OPCODE_MAX:
701 case TGSI_OPCODE_IMAX:
702 case TGSI_OPCODE_UMAX: return NV_OP_MAX;
703 case TGSI_OPCODE_MIN:
704 case TGSI_OPCODE_IMIN:
705 case TGSI_OPCODE_UMIN: return NV_OP_MIN;
706 case TGSI_OPCODE_MUL:
707 case TGSI_OPCODE_UMUL: return NV_OP_MUL;
708 case TGSI_OPCODE_OR: return NV_OP_OR;
709 case TGSI_OPCODE_RCP: return NV_OP_RCP;
710 case TGSI_OPCODE_RSQ: return NV_OP_RSQ;
711 case TGSI_OPCODE_SAD: return NV_OP_SAD;
712 case TGSI_OPCODE_SHL: return NV_OP_SHL;
713 case TGSI_OPCODE_SLT:
714 case TGSI_OPCODE_SGE:
715 case TGSI_OPCODE_SEQ:
716 case TGSI_OPCODE_SGT:
717 case TGSI_OPCODE_SLE:
718 case TGSI_OPCODE_SNE:
719 case TGSI_OPCODE_ISLT:
720 case TGSI_OPCODE_ISGE:
721 case TGSI_OPCODE_USEQ:
722 case TGSI_OPCODE_USGE:
723 case TGSI_OPCODE_USLT:
724 case TGSI_OPCODE_USNE: return NV_OP_SET;
725 case TGSI_OPCODE_TEX: return NV_OP_TEX;
726 case TGSI_OPCODE_TXP: return NV_OP_TEX;
727 case TGSI_OPCODE_TXB: return NV_OP_TXB;
728 case TGSI_OPCODE_TXL: return NV_OP_TXL;
729 case TGSI_OPCODE_XOR: return NV_OP_XOR;
730 default:
731 return NV_OP_NOP;
732 }
733 }
734
735 static ubyte
736 infer_src_type(unsigned opcode)
737 {
738 switch (opcode) {
739 case TGSI_OPCODE_MOV:
740 case TGSI_OPCODE_AND:
741 case TGSI_OPCODE_OR:
742 case TGSI_OPCODE_XOR:
743 case TGSI_OPCODE_SAD:
744 case TGSI_OPCODE_U2F:
745 case TGSI_OPCODE_UADD:
746 case TGSI_OPCODE_UDIV:
747 case TGSI_OPCODE_UMOD:
748 case TGSI_OPCODE_UMAD:
749 case TGSI_OPCODE_UMUL:
750 case TGSI_OPCODE_UMAX:
751 case TGSI_OPCODE_UMIN:
752 case TGSI_OPCODE_USEQ:
753 case TGSI_OPCODE_USGE:
754 case TGSI_OPCODE_USLT:
755 case TGSI_OPCODE_USNE:
756 case TGSI_OPCODE_USHR:
757 return NV_TYPE_U32;
758 case TGSI_OPCODE_I2F:
759 case TGSI_OPCODE_IDIV:
760 case TGSI_OPCODE_IMAX:
761 case TGSI_OPCODE_IMIN:
762 case TGSI_OPCODE_INEG:
763 case TGSI_OPCODE_ISGE:
764 case TGSI_OPCODE_ISHR:
765 case TGSI_OPCODE_ISLT:
766 return NV_TYPE_S32;
767 default:
768 return NV_TYPE_F32;
769 }
770 }
771
772 static ubyte
773 infer_dst_type(unsigned opcode)
774 {
775 switch (opcode) {
776 case TGSI_OPCODE_MOV:
777 case TGSI_OPCODE_F2U:
778 case TGSI_OPCODE_AND:
779 case TGSI_OPCODE_OR:
780 case TGSI_OPCODE_XOR:
781 case TGSI_OPCODE_SAD:
782 case TGSI_OPCODE_UADD:
783 case TGSI_OPCODE_UDIV:
784 case TGSI_OPCODE_UMOD:
785 case TGSI_OPCODE_UMAD:
786 case TGSI_OPCODE_UMUL:
787 case TGSI_OPCODE_UMAX:
788 case TGSI_OPCODE_UMIN:
789 case TGSI_OPCODE_USEQ:
790 case TGSI_OPCODE_USGE:
791 case TGSI_OPCODE_USLT:
792 case TGSI_OPCODE_USNE:
793 case TGSI_OPCODE_USHR:
794 return NV_TYPE_U32;
795 case TGSI_OPCODE_F2I:
796 case TGSI_OPCODE_IDIV:
797 case TGSI_OPCODE_IMAX:
798 case TGSI_OPCODE_IMIN:
799 case TGSI_OPCODE_INEG:
800 case TGSI_OPCODE_ISGE:
801 case TGSI_OPCODE_ISHR:
802 case TGSI_OPCODE_ISLT:
803 return NV_TYPE_S32;
804 default:
805 return NV_TYPE_F32;
806 }
807 }
808
809 static void
810 emit_store(struct bld_context *bld, const struct tgsi_full_instruction *inst,
811 unsigned chan, struct nv_value *value)
812 {
813 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
814
815 assert(chan < 4);
816
817 if (inst->Instruction.Opcode != TGSI_OPCODE_MOV)
818 value->reg.type = infer_dst_type(inst->Instruction.Opcode);
819
820 switch (inst->Instruction.Saturate) {
821 case TGSI_SAT_NONE:
822 break;
823 case TGSI_SAT_ZERO_ONE:
824 BLD_INSN_1_EX(value, SAT, F32, value, F32);
825 break;
826 case TGSI_SAT_MINUS_PLUS_ONE:
827 value = bld_insn_2(bld, NV_OP_MAX, value, bld_load_imm_f32(bld, -1.0f));
828 value = bld_insn_2(bld, NV_OP_MIN, value, bld_load_imm_f32(bld, 1.0f));
829 value->reg.type = NV_TYPE_F32;
830 break;
831 }
832
833 switch (reg->Register.File) {
834 case TGSI_FILE_OUTPUT:
835 value = bld_insn_1(bld, NV_OP_MOV, value);
836 value->reg.file = bld->ti->output_file;
837
838 if (bld->ti->p->type == PIPE_SHADER_FRAGMENT) {
839 STORE_OUTR(reg->Register.Index, chan, value);
840 } else {
841 value->insn->fixed = 1;
842 value->reg.id = bld->ti->output_map[reg->Register.Index][chan];
843 }
844 break;
845 case TGSI_FILE_TEMPORARY:
846 assert(reg->Register.Index < BLD_MAX_TEMPS);
847 value->reg.file = NV_FILE_GPR;
848 if (value->insn->bb != bld->pc->current_block)
849 value = bld_insn_1(bld, NV_OP_MOV, value);
850 STORE_TEMP(reg->Register.Index, chan, value);
851 break;
852 case TGSI_FILE_ADDRESS:
853 assert(reg->Register.Index < BLD_MAX_ADDRS);
854 value->reg.file = NV_FILE_ADDR;
855 STORE_ADDR(reg->Register.Index, chan, value);
856 break;
857 }
858 }
859
860 static INLINE uint32_t
861 bld_is_output_written(struct bld_context *bld, int i, int c)
862 {
863 if (c < 0)
864 return bld->outputs_written[i / 8] & (0xf << ((i * 4) % 32));
865 return bld->outputs_written[i / 8] & (1 << ((i * 4 + c) % 32));
866 }
867
868 static void
869 bld_export_outputs(struct bld_context *bld)
870 {
871 struct nv_value *vals[4];
872 struct nv_instruction *nvi;
873 int i, c, n;
874
875 bld_push_values(&bld->ovs[0][0], PIPE_MAX_SHADER_OUTPUTS);
876
877 for (i = 0; i < PIPE_MAX_SHADER_OUTPUTS; ++i) {
878 if (!bld_is_output_written(bld, i, -1))
879 continue;
880 for (n = 0, c = 0; c < 4; ++c) {
881 if (!bld_is_output_written(bld, i, c))
882 continue;
883 vals[n] = bld_fetch_global(bld, &bld->ovs[i][c]);
884 assert(vals[n]);
885 vals[n] = bld_insn_1(bld, NV_OP_MOV, vals[n]);
886 vals[n++]->reg.id = bld->ti->output_map[i][c];
887 }
888 assert(n);
889
890 (nvi = new_instruction(bld->pc, NV_OP_EXPORT))->fixed = 1;
891
892 for (c = 0; c < n; ++c)
893 nvi->src[c] = new_ref(bld->pc, vals[c]);
894 }
895 }
896
897 static void
898 bld_new_block(struct bld_context *bld, struct nv_basic_block *b)
899 {
900 int i;
901
902 bld_push_values(&bld->tvs[0][0], BLD_MAX_TEMPS);
903 bld_push_values(&bld->avs[0][0], BLD_MAX_ADDRS);
904 bld_push_values(&bld->pvs[0][0], BLD_MAX_PREDS);
905 bld_push_values(&bld->ovs[0][0], PIPE_MAX_SHADER_OUTPUTS);
906
907 bld->pc->current_block = b;
908
909 for (i = 0; i < 4; ++i)
910 bld->saved_addr[i][0] = NULL;
911
912 for (i = 0; i < 128; ++i)
913 bld->saved_inputs[i] = NULL;
914 }
915
916 static struct nv_value *
917 bld_saved_input(struct bld_context *bld, unsigned i, unsigned c)
918 {
919 unsigned idx = bld->ti->input_map[i][c];
920
921 if (bld->ti->p->type != PIPE_SHADER_FRAGMENT)
922 return NULL;
923 if (bld->saved_inputs[idx])
924 return bld->saved_inputs[idx];
925 return NULL;
926 }
927
928 static struct nv_value *
929 bld_interpolate(struct bld_context *bld, unsigned mode, struct nv_value *val)
930 {
931 if (mode & (NV50_INTERP_LINEAR | NV50_INTERP_FLAT))
932 val = bld_insn_1(bld, NV_OP_LINTERP, val);
933 else
934 val = bld_insn_2(bld, NV_OP_PINTERP, val, bld->frgcrd[3]);
935
936 val->insn->flat = (mode & NV50_INTERP_FLAT) ? 1 : 0;
937 val->insn->centroid = (mode & NV50_INTERP_CENTROID) ? 1 : 0;
938 return val;
939 }
940
941 static struct nv_value *
942 emit_fetch(struct bld_context *bld, const struct tgsi_full_instruction *insn,
943 const unsigned s, const unsigned chan)
944 {
945 const struct tgsi_full_src_register *src = &insn->Src[s];
946 struct nv_value *res;
947 unsigned idx, swz, dim_idx, ind_idx, ind_swz;
948 ubyte type = infer_src_type(insn->Instruction.Opcode);
949
950 idx = src->Register.Index;
951 swz = tgsi_util_get_full_src_register_swizzle(src, chan);
952 dim_idx = -1;
953 ind_idx = -1;
954 ind_swz = 0;
955
956 if (src->Register.Indirect) {
957 ind_idx = src->Indirect.Index;
958 ind_swz = tgsi_util_get_src_register_swizzle(&src->Indirect, 0);
959 }
960
961 switch (src->Register.File) {
962 case TGSI_FILE_CONSTANT:
963 dim_idx = src->Dimension.Index ? src->Dimension.Index + 2 : 1;
964 assert(dim_idx < 14);
965 assert(dim_idx == 1); /* for now */
966
967 res = new_value(bld->pc, NV_FILE_MEM_C(dim_idx), type);
968 res->reg.type = type;
969 res->reg.id = (idx * 4 + swz) & 127;
970 res = bld_insn_1(bld, NV_OP_LDA, res);
971
972 if (src->Register.Indirect)
973 res->insn->src[4] = new_ref(bld->pc, FETCH_ADDR(ind_idx, ind_swz));
974 if (idx >= (128 / 4))
975 res->insn->src[4] =
976 new_ref(bld->pc, bld_get_address(bld, (idx * 16) & ~0x1ff, NULL));
977 break;
978 case TGSI_FILE_IMMEDIATE:
979 assert(idx < bld->ti->immd32_nr);
980 res = bld_load_imm_u32(bld, bld->ti->immd32[idx * 4 + swz]);
981 res->reg.type = type;
982 break;
983 case TGSI_FILE_INPUT:
984 res = bld_saved_input(bld, idx, swz);
985 if (res && (insn->Instruction.Opcode != TGSI_OPCODE_TXP))
986 return res;
987
988 res = new_value(bld->pc, bld->ti->input_file, type);
989 res->reg.id = bld->ti->input_map[idx][swz];
990
991 if (res->reg.file == NV_FILE_MEM_V) {
992 res = bld_interpolate(bld, bld->ti->interp_mode[idx], res);
993 } else {
994 assert(src->Dimension.Dimension == 0);
995 res = bld_insn_1(bld, NV_OP_LDA, res);
996 }
997 assert(res->reg.type == type);
998
999 bld->saved_inputs[bld->ti->input_map[idx][swz]] = res;
1000 break;
1001 case TGSI_FILE_TEMPORARY:
1002 /* this should be load from l[], with reload elimination later on */
1003 res = bld_fetch_global(bld, &bld->tvs[idx][swz]);
1004 break;
1005 case TGSI_FILE_ADDRESS:
1006 res = bld_fetch_global(bld, &bld->avs[idx][swz]);
1007 break;
1008 case TGSI_FILE_PREDICATE:
1009 res = bld_fetch_global(bld, &bld->pvs[idx][swz]);
1010 break;
1011 default:
1012 NOUVEAU_ERR("illegal/unhandled src reg file: %d\n", src->Register.File);
1013 abort();
1014 break;
1015 }
1016 if (!res) {
1017 debug_printf("WARNING: undefined source value in TGSI instruction\n");
1018 return bld_load_imm_u32(bld, 0);
1019 }
1020
1021 switch (tgsi_util_get_full_src_register_sign_mode(src, chan)) {
1022 case TGSI_UTIL_SIGN_KEEP:
1023 break;
1024 case TGSI_UTIL_SIGN_CLEAR:
1025 res = bld_insn_1(bld, NV_OP_ABS, res);
1026 break;
1027 case TGSI_UTIL_SIGN_TOGGLE:
1028 res = bld_insn_1(bld, NV_OP_NEG, res);
1029 break;
1030 case TGSI_UTIL_SIGN_SET:
1031 res = bld_insn_1(bld, NV_OP_ABS, res);
1032 res = bld_insn_1(bld, NV_OP_NEG, res);
1033 break;
1034 default:
1035 NOUVEAU_ERR("illegal/unhandled src reg sign mode\n");
1036 abort();
1037 break;
1038 }
1039
1040 return res;
1041 }
1042
1043 static void
1044 bld_lit(struct bld_context *bld, struct nv_value *dst0[4],
1045 const struct tgsi_full_instruction *insn)
1046 {
1047 struct nv_value *val0, *zero;
1048 unsigned mask = insn->Dst[0].Register.WriteMask;
1049
1050 if (mask & ((1 << 0) | (1 << 3)))
1051 dst0[3] = dst0[0] = bld_load_imm_f32(bld, 1.0f);
1052
1053 if (mask & (3 << 1)) {
1054 zero = bld_load_imm_f32(bld, 0.0f);
1055 val0 = bld_insn_2(bld, NV_OP_MAX, emit_fetch(bld, insn, 0, 0), zero);
1056
1057 if (mask & (1 << 1))
1058 dst0[1] = val0;
1059 }
1060
1061 if (mask & (1 << 2)) {
1062 struct nv_value *val1, *val3, *src1, *src3;
1063 struct nv_value *pos128 = bld_load_imm_f32(bld, 127.999999f);
1064 struct nv_value *neg128 = bld_load_imm_f32(bld, -127.999999f);
1065
1066 src1 = emit_fetch(bld, insn, 0, 1);
1067 src3 = emit_fetch(bld, insn, 0, 3);
1068
1069 val0->insn->flags_def = new_value(bld->pc, NV_FILE_FLAGS, NV_TYPE_U16);
1070 val0->insn->flags_def->insn = val0->insn;
1071
1072 val1 = bld_insn_2(bld, NV_OP_MAX, src1, zero);
1073 val3 = bld_insn_2(bld, NV_OP_MAX, src3, neg128);
1074 val3 = bld_insn_2(bld, NV_OP_MIN, val3, pos128);
1075 val3 = bld_pow(bld, val1, val3);
1076
1077 dst0[2] = bld_insn_1(bld, NV_OP_MOV, zero);
1078 dst0[2]->insn->cc = NV_CC_LE;
1079 dst0[2]->insn->flags_src = new_ref(bld->pc, val0->insn->flags_def);
1080
1081 dst0[2] = bld_insn_2(bld, NV_OP_SELECT, val3, dst0[2]);
1082 }
1083 }
1084
1085 static INLINE void
1086 get_tex_dim(const struct tgsi_full_instruction *insn, int *dim, int *arg)
1087 {
1088 switch (insn->Texture.Texture) {
1089 case TGSI_TEXTURE_1D:
1090 *arg = *dim = 1;
1091 break;
1092 case TGSI_TEXTURE_SHADOW1D:
1093 *dim = 1;
1094 *arg = 2;
1095 break;
1096 case TGSI_TEXTURE_UNKNOWN:
1097 case TGSI_TEXTURE_2D:
1098 case TGSI_TEXTURE_RECT:
1099 *arg = *dim = 2;
1100 break;
1101 case TGSI_TEXTURE_SHADOW2D:
1102 case TGSI_TEXTURE_SHADOWRECT:
1103 *dim = 2;
1104 *arg = 3;
1105 break;
1106 case TGSI_TEXTURE_3D:
1107 case TGSI_TEXTURE_CUBE:
1108 *dim = *arg = 3;
1109 break;
1110 default:
1111 assert(0);
1112 break;
1113 }
1114 }
1115
1116 static void
1117 load_proj_tex_coords(struct bld_context *bld,
1118 struct nv_value *t[4], int dim,
1119 const struct tgsi_full_instruction *insn)
1120 {
1121 int c, mask = 0;
1122
1123 t[3] = emit_fetch(bld, insn, 0, 3);
1124
1125 if (t[3]->insn->opcode == NV_OP_PINTERP) {
1126 t[3]->insn->opcode = NV_OP_LINTERP;
1127 nv_reference(bld->pc, &t[3]->insn->src[1], NULL);
1128 }
1129
1130 t[3] = bld_insn_1(bld, NV_OP_RCP, t[3]);
1131
1132 for (c = 0; c < dim; ++c) {
1133 t[c] = emit_fetch(bld, insn, 0, c);
1134 if (t[c]->insn->opcode == NV_OP_LINTERP)
1135 t[c]->insn->opcode = NV_OP_PINTERP;
1136
1137 if (t[c]->insn->opcode == NV_OP_PINTERP)
1138 nv_reference(bld->pc, &t[c]->insn->src[1], t[3]);
1139 else
1140 mask |= 1 << c;
1141 }
1142
1143 for (c = 0; mask; ++c, mask >>= 1) {
1144 if (!(mask & 1))
1145 continue;
1146 t[c] = bld_insn_2(bld, NV_OP_MUL, t[c], t[3]);
1147 }
1148 }
1149
1150 static void
1151 bld_tex(struct bld_context *bld, struct nv_value *dst0[4],
1152 const struct tgsi_full_instruction *insn)
1153 {
1154 struct nv_value *t[4];
1155 struct nv_instruction *nvi;
1156 uint opcode = translate_opcode(insn->Instruction.Opcode);
1157 int arg, dim, c;
1158
1159 get_tex_dim(insn, &dim, &arg);
1160
1161 if (insn->Texture.Texture == TGSI_TEXTURE_CUBE) {
1162 }
1163 // else
1164 if (insn->Instruction.Opcode == TGSI_OPCODE_TXP) {
1165 load_proj_tex_coords(bld, t, dim, insn);
1166 } else
1167 for (c = 0; c < dim; ++c)
1168 t[c] = emit_fetch(bld, insn, 0, c);
1169
1170 if (arg != dim)
1171 t[dim] = emit_fetch(bld, insn, 0, 2);
1172
1173 if (insn->Instruction.Opcode == TGSI_OPCODE_TXB ||
1174 insn->Instruction.Opcode == TGSI_OPCODE_TXL) {
1175 t[arg++] = emit_fetch(bld, insn, 0, 3);
1176 }
1177
1178 for (c = 0; c < arg; ++c) {
1179 t[c] = bld_insn_1(bld, NV_OP_MOV, t[c]);
1180 t[c]->reg.type = NV_TYPE_F32;
1181 }
1182
1183 nvi = new_instruction(bld->pc, opcode);
1184
1185 for (c = 0; c < 4; ++c) {
1186 nvi->def[c] = dst0[c] = new_value(bld->pc, NV_FILE_GPR, NV_TYPE_F32);
1187 nvi->def[c]->insn = nvi;
1188 }
1189 for (c = 0; c < arg; ++c)
1190 nvi->src[c] = new_ref(bld->pc, t[c]);
1191
1192 nvi->tex_t = insn->Src[1].Register.Index;
1193 nvi->tex_s = 0;
1194 nvi->tex_mask = 0xf;
1195 nvi->tex_cube = (insn->Texture.Texture == TGSI_TEXTURE_CUBE) ? 1 : 0;
1196 nvi->tex_live = 0;
1197 nvi->tex_argc = arg;
1198 }
1199
1200 #define FOR_EACH_DST0_ENABLED_CHANNEL(chan, inst) \
1201 for (chan = 0; chan < 4; ++chan) \
1202 if ((inst)->Dst[0].Register.WriteMask & (1 << chan))
1203
1204 static void
1205 bld_instruction(struct bld_context *bld,
1206 const struct tgsi_full_instruction *insn)
1207 {
1208 struct nv_value *src0;
1209 struct nv_value *src1;
1210 struct nv_value *src2;
1211 struct nv_value *dst0[4];
1212 struct nv_value *temp;
1213 int c;
1214 uint opcode = translate_opcode(insn->Instruction.Opcode);
1215
1216 tgsi_dump_instruction(insn, 1);
1217
1218 switch (insn->Instruction.Opcode) {
1219 case TGSI_OPCODE_ADD:
1220 case TGSI_OPCODE_MAX:
1221 case TGSI_OPCODE_MIN:
1222 case TGSI_OPCODE_MUL:
1223 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
1224 src0 = emit_fetch(bld, insn, 0, c);
1225 src1 = emit_fetch(bld, insn, 1, c);
1226 dst0[c] = bld_insn_2(bld, opcode, src0, src1);
1227 }
1228 break;
1229 case TGSI_OPCODE_CMP:
1230 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
1231 src0 = emit_fetch(bld, insn, 0, c);
1232 src1 = emit_fetch(bld, insn, 1, c);
1233 src2 = emit_fetch(bld, insn, 2, c);
1234 src0 = bld_predicate(bld, src0, FALSE);
1235
1236 src1 = bld_insn_1(bld, NV_OP_MOV, src1);
1237 src1->insn->flags_src = new_ref(bld->pc, src0);
1238 src1->insn->cc = NV_CC_LT;
1239
1240 src2 = bld_insn_1(bld, NV_OP_MOV, src2);
1241 src2->insn->flags_src = new_ref(bld->pc, src0);
1242 src2->insn->cc = NV_CC_GE;
1243
1244 dst0[c] = bld_insn_2(bld, NV_OP_SELECT, src1, src2);
1245 }
1246 break;
1247 case TGSI_OPCODE_COS:
1248 src0 = emit_fetch(bld, insn, 0, 0);
1249 temp = bld_insn_1(bld, NV_OP_PRESIN, src0);
1250 if (insn->Dst[0].Register.WriteMask & 7)
1251 temp = bld_insn_1(bld, NV_OP_COS, temp);
1252 for (c = 0; c < 3; ++c)
1253 if (insn->Dst[0].Register.WriteMask & (1 << c))
1254 dst0[c] = temp;
1255 if (!(insn->Dst[0].Register.WriteMask & (1 << 3)))
1256 break;
1257 /* XXX: if src0.x is src0.w, don't emit new insns */
1258 src0 = emit_fetch(bld, insn, 0, 3);
1259 temp = bld_insn_1(bld, NV_OP_PRESIN, src0);
1260 dst0[3] = bld_insn_1(bld, NV_OP_COS, temp);
1261 break;
1262 case TGSI_OPCODE_DP3:
1263 src0 = emit_fetch(bld, insn, 0, 0);
1264 src1 = emit_fetch(bld, insn, 1, 0);
1265 temp = bld_insn_2(bld, NV_OP_MUL, src0, src1);
1266 for (c = 1; c < 3; ++c) {
1267 src0 = emit_fetch(bld, insn, 0, c);
1268 src1 = emit_fetch(bld, insn, 1, c);
1269 temp = bld_insn_3(bld, NV_OP_MAD, src0, src1, temp);
1270 }
1271 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn)
1272 dst0[c] = temp;
1273 break;
1274 case TGSI_OPCODE_DP4:
1275 src0 = emit_fetch(bld, insn, 0, 0);
1276 src1 = emit_fetch(bld, insn, 1, 0);
1277 temp = bld_insn_2(bld, NV_OP_MUL, src0, src1);
1278 for (c = 1; c < 4; ++c) {
1279 src0 = emit_fetch(bld, insn, 0, c);
1280 src1 = emit_fetch(bld, insn, 1, c);
1281 temp = bld_insn_3(bld, NV_OP_MAD, src0, src1, temp);
1282 }
1283 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn)
1284 dst0[c] = temp;
1285 break;
1286 case TGSI_OPCODE_EX2:
1287 src0 = emit_fetch(bld, insn, 0, 0);
1288 temp = bld_insn_1(bld, NV_OP_PREEX2, src0);
1289 temp = bld_insn_1(bld, NV_OP_EX2, temp);
1290 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn)
1291 dst0[c] = temp;
1292 break;
1293 case TGSI_OPCODE_FRC:
1294 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
1295 src0 = emit_fetch(bld, insn, 0, c);
1296 dst0[c] = bld_insn_1(bld, NV_OP_FLOOR, src0);
1297 dst0[c] = bld_insn_2(bld, NV_OP_SUB, src0, dst0[c]);
1298 }
1299 break;
1300 case TGSI_OPCODE_KIL:
1301 for (c = 0; c < 4; ++c) {
1302 src0 = emit_fetch(bld, insn, 0, c);
1303 bld_kil(bld, src0);
1304 }
1305 break;
1306 case TGSI_OPCODE_IF:
1307 {
1308 struct nv_basic_block *b = new_basic_block(bld->pc);
1309
1310 nvbb_attach_block(bld->pc->current_block, b, CFG_EDGE_FORWARD);
1311
1312 bld->join_bb[bld->cond_lvl] = bld->pc->current_block;
1313 bld->cond_bb[bld->cond_lvl] = bld->pc->current_block;
1314
1315 src1 = bld_predicate(bld, emit_fetch(bld, insn, 0, 0), TRUE);
1316
1317 bld_flow(bld, NV_OP_BRA, NV_CC_EQ, src1, NULL, FALSE);
1318
1319 ++bld->cond_lvl;
1320 bld_new_block(bld, b);
1321 }
1322 break;
1323 case TGSI_OPCODE_ELSE:
1324 {
1325 struct nv_basic_block *b = new_basic_block(bld->pc);
1326
1327 --bld->cond_lvl;
1328 nvbb_attach_block(bld->join_bb[bld->cond_lvl], b, CFG_EDGE_FORWARD);
1329
1330 bld->cond_bb[bld->cond_lvl]->exit->target = b;
1331 bld->cond_bb[bld->cond_lvl] = bld->pc->current_block;
1332
1333 new_instruction(bld->pc, NV_OP_BRA)->is_terminator = 1;
1334
1335 ++bld->cond_lvl;
1336 bld_new_block(bld, b);
1337 }
1338 break;
1339 case TGSI_OPCODE_ENDIF:
1340 {
1341 struct nv_basic_block *b = new_basic_block(bld->pc);
1342
1343 --bld->cond_lvl;
1344 nvbb_attach_block(bld->pc->current_block, b, CFG_EDGE_FORWARD);
1345 nvbb_attach_block(bld->cond_bb[bld->cond_lvl], b, CFG_EDGE_FORWARD);
1346
1347 bld->cond_bb[bld->cond_lvl]->exit->target = b;
1348
1349 if (0 && bld->join_bb[bld->cond_lvl]) {
1350 bld->join_bb[bld->cond_lvl]->exit->prev->target = b;
1351
1352 new_instruction(bld->pc, NV_OP_NOP)->is_join = TRUE;
1353 }
1354
1355 bld_new_block(bld, b);
1356 }
1357 break;
1358 case TGSI_OPCODE_BGNLOOP:
1359 {
1360 struct nv_basic_block *bl = new_basic_block(bld->pc);
1361 struct nv_basic_block *bb = new_basic_block(bld->pc);
1362
1363 bld->loop_bb[bld->loop_lvl] = bl;
1364 bld->brkt_bb[bld->loop_lvl] = bb;
1365
1366 bld_flow(bld, NV_OP_BREAKADDR, NV_CC_TR, NULL, bb, FALSE);
1367
1368 nvbb_attach_block(bld->pc->current_block, bl, CFG_EDGE_LOOP_ENTER);
1369
1370 bld_new_block(bld, bld->loop_bb[bld->loop_lvl++]);
1371
1372 if (bld->loop_lvl == bld->pc->loop_nesting_bound)
1373 bld->pc->loop_nesting_bound++;
1374
1375 bld_clear_def_use(&bld->tvs[0][0], BLD_MAX_TEMPS, bld->loop_lvl);
1376 bld_clear_def_use(&bld->avs[0][0], BLD_MAX_ADDRS, bld->loop_lvl);
1377 bld_clear_def_use(&bld->pvs[0][0], BLD_MAX_PREDS, bld->loop_lvl);
1378 }
1379 break;
1380 case TGSI_OPCODE_BRK:
1381 {
1382 struct nv_basic_block *bb = bld->brkt_bb[bld->loop_lvl - 1];
1383
1384 bld_flow(bld, NV_OP_BREAK, NV_CC_TR, NULL, bb, FALSE);
1385
1386 /* XXX: don't do this for redundant BRKs */
1387 nvbb_attach_block(bld->pc->current_block, bb, CFG_EDGE_LOOP_LEAVE);
1388 }
1389 break;
1390 case TGSI_OPCODE_CONT:
1391 {
1392 struct nv_basic_block *bb = bld->loop_bb[bld->loop_lvl - 1];
1393
1394 bld_flow(bld, NV_OP_BRA, NV_CC_TR, NULL, bb, FALSE);
1395
1396 nvbb_attach_block(bld->pc->current_block, bb, CFG_EDGE_BACK);
1397 }
1398 break;
1399 case TGSI_OPCODE_ENDLOOP:
1400 {
1401 struct nv_basic_block *bb = bld->loop_bb[--bld->loop_lvl];
1402
1403 bld_flow(bld, NV_OP_BRA, NV_CC_TR, NULL, bb, FALSE);
1404
1405 nvbb_attach_block(bld->pc->current_block, bb, CFG_EDGE_BACK);
1406
1407 bld_loop_end(bld, bb); /* replace loop-side operand of the phis */
1408
1409 bld_new_block(bld, bld->brkt_bb[bld->loop_lvl]);
1410 }
1411 break;
1412 case TGSI_OPCODE_ABS:
1413 case TGSI_OPCODE_CEIL:
1414 case TGSI_OPCODE_FLR:
1415 case TGSI_OPCODE_TRUNC:
1416 case TGSI_OPCODE_DDX:
1417 case TGSI_OPCODE_DDY:
1418 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
1419 src0 = emit_fetch(bld, insn, 0, c);
1420 dst0[c] = bld_insn_1(bld, opcode, src0);
1421 }
1422 break;
1423 case TGSI_OPCODE_LIT:
1424 bld_lit(bld, dst0, insn);
1425 break;
1426 case TGSI_OPCODE_LRP:
1427 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
1428 src0 = emit_fetch(bld, insn, 0, c);
1429 src1 = emit_fetch(bld, insn, 1, c);
1430 src2 = emit_fetch(bld, insn, 2, c);
1431 dst0[c] = bld_insn_2(bld, NV_OP_SUB, src1, src2);
1432 dst0[c] = bld_insn_3(bld, NV_OP_MAD, dst0[c], src0, src2);
1433 }
1434 break;
1435 case TGSI_OPCODE_MOV:
1436 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn)
1437 dst0[c] = emit_fetch(bld, insn, 0, c);
1438 break;
1439 case TGSI_OPCODE_MAD:
1440 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
1441 src0 = emit_fetch(bld, insn, 0, c);
1442 src1 = emit_fetch(bld, insn, 1, c);
1443 src2 = emit_fetch(bld, insn, 2, c);
1444 dst0[c] = bld_insn_3(bld, opcode, src0, src1, src2);
1445 }
1446 break;
1447 case TGSI_OPCODE_POW:
1448 src0 = emit_fetch(bld, insn, 0, 0);
1449 src1 = emit_fetch(bld, insn, 1, 0);
1450 temp = bld_pow(bld, src0, src1);
1451 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn)
1452 dst0[c] = temp;
1453 break;
1454 case TGSI_OPCODE_RCP:
1455 case TGSI_OPCODE_LG2:
1456 src0 = emit_fetch(bld, insn, 0, 0);
1457 temp = bld_insn_1(bld, opcode, src0);
1458 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn)
1459 dst0[c] = temp;
1460 break;
1461 case TGSI_OPCODE_RSQ:
1462 src0 = emit_fetch(bld, insn, 0, 0);
1463 temp = bld_insn_1(bld, NV_OP_ABS, src0);
1464 temp = bld_insn_1(bld, NV_OP_RSQ, temp);
1465 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn)
1466 dst0[c] = temp;
1467 break;
1468 case TGSI_OPCODE_SLT:
1469 case TGSI_OPCODE_SGE:
1470 case TGSI_OPCODE_SEQ:
1471 case TGSI_OPCODE_SGT:
1472 case TGSI_OPCODE_SLE:
1473 case TGSI_OPCODE_SNE:
1474 case TGSI_OPCODE_ISLT:
1475 case TGSI_OPCODE_ISGE:
1476 case TGSI_OPCODE_USEQ:
1477 case TGSI_OPCODE_USGE:
1478 case TGSI_OPCODE_USLT:
1479 case TGSI_OPCODE_USNE:
1480 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
1481 src0 = emit_fetch(bld, insn, 0, c);
1482 src1 = emit_fetch(bld, insn, 1, c);
1483 dst0[c] = bld_insn_2(bld, NV_OP_SET, src0, src1);
1484 dst0[c]->insn->set_cond = translate_setcc(insn->Instruction.Opcode);
1485 dst0[c]->reg.type = infer_dst_type(insn->Instruction.Opcode);
1486
1487 dst0[c]->insn->src[0]->typecast =
1488 dst0[c]->insn->src[1]->typecast =
1489 infer_src_type(insn->Instruction.Opcode);
1490
1491 if (dst0[c]->reg.type != NV_TYPE_F32)
1492 break;
1493 dst0[c] = bld_insn_1(bld, NV_OP_ABS, dst0[c]);
1494 dst0[c]->insn->src[0]->typecast = NV_TYPE_S32;
1495 dst0[c]->reg.type = NV_TYPE_S32;
1496 dst0[c] = bld_insn_1(bld, NV_OP_CVT, dst0[c]);
1497 dst0[c]->reg.type = NV_TYPE_F32;
1498 }
1499 break;
1500 case TGSI_OPCODE_SUB:
1501 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
1502 src0 = emit_fetch(bld, insn, 0, c);
1503 src1 = emit_fetch(bld, insn, 1, c);
1504 dst0[c] = bld_insn_2(bld, NV_OP_ADD, src0, src1);
1505 dst0[c]->insn->src[1]->mod ^= NV_MOD_NEG;
1506 }
1507 break;
1508 case TGSI_OPCODE_TEX:
1509 case TGSI_OPCODE_TXB:
1510 case TGSI_OPCODE_TXL:
1511 case TGSI_OPCODE_TXP:
1512 bld_tex(bld, dst0, insn);
1513 break;
1514 case TGSI_OPCODE_XPD:
1515 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
1516 if (c == 3) {
1517 dst0[3] = bld_imm_f32(bld, 1.0f);
1518 break;
1519 }
1520 src0 = emit_fetch(bld, insn, 0, (c + 1) % 3);
1521 src1 = emit_fetch(bld, insn, 1, (c + 2) % 3);
1522 dst0[c] = bld_insn_2(bld, NV_OP_MUL, src0, src1);
1523
1524 src0 = emit_fetch(bld, insn, 0, (c + 2) % 3);
1525 src1 = emit_fetch(bld, insn, 1, (c + 1) % 3);
1526 dst0[c] = bld_insn_3(bld, NV_OP_MAD, src0, src1, dst0[c]);
1527
1528 dst0[c]->insn->src[2]->mod ^= NV_MOD_NEG;
1529 }
1530 break;
1531 case TGSI_OPCODE_END:
1532 if (bld->ti->p->type == PIPE_SHADER_FRAGMENT)
1533 bld_export_outputs(bld);
1534 break;
1535 default:
1536 NOUVEAU_ERR("nv_bld: unhandled opcode %u\n", insn->Instruction.Opcode);
1537 abort();
1538 break;
1539 }
1540
1541 FOR_EACH_DST0_ENABLED_CHANNEL(c, insn)
1542 emit_store(bld, insn, c, dst0[c]);
1543 }
1544
1545 static INLINE void
1546 bld_free_value_trackers(struct bld_value_stack *base, int n)
1547 {
1548 int i, c;
1549
1550 for (i = 0; i < n; ++i)
1551 for (c = 0; c < 4; ++c)
1552 if (base[i * 4 + c].body)
1553 FREE(base[i * 4 + c].body);
1554 }
1555
1556 int
1557 nv50_tgsi_to_nc(struct nv_pc *pc, struct nv50_translation_info *ti)
1558 {
1559 struct bld_context *bld = CALLOC_STRUCT(bld_context);
1560 int c;
1561
1562 pc->root = pc->current_block = new_basic_block(pc);
1563
1564 bld->pc = pc;
1565 bld->ti = ti;
1566
1567 pc->loop_nesting_bound = 1;
1568
1569 c = util_bitcount(bld->ti->p->fp.interp >> 24);
1570 if (c && ti->p->type == PIPE_SHADER_FRAGMENT) {
1571 bld->frgcrd[3] = new_value(pc, NV_FILE_MEM_V, NV_TYPE_F32);
1572 bld->frgcrd[3]->reg.id = c - 1;
1573 bld->frgcrd[3] = bld_insn_1(bld, NV_OP_LINTERP, bld->frgcrd[3]);
1574 bld->frgcrd[3] = bld_insn_1(bld, NV_OP_RCP, bld->frgcrd[3]);
1575 }
1576
1577 tgsi_parse_init(&bld->parse[0], ti->p->pipe.tokens);
1578
1579 while (!tgsi_parse_end_of_tokens(&bld->parse[bld->call_lvl])) {
1580 const union tgsi_full_token *tok = &bld->parse[bld->call_lvl].FullToken;
1581
1582 tgsi_parse_token(&bld->parse[bld->call_lvl]);
1583
1584 switch (tok->Token.Type) {
1585 case TGSI_TOKEN_TYPE_INSTRUCTION:
1586 bld_instruction(bld, &tok->FullInstruction);
1587 break;
1588 default:
1589 break;
1590 }
1591 }
1592
1593 bld_free_value_trackers(&bld->tvs[0][0], BLD_MAX_TEMPS);
1594 bld_free_value_trackers(&bld->avs[0][0], BLD_MAX_ADDRS);
1595 bld_free_value_trackers(&bld->pvs[0][0], BLD_MAX_PREDS);
1596
1597 bld_free_value_trackers(&bld->ovs[0][0], PIPE_MAX_SHADER_OUTPUTS);
1598
1599 FREE(bld);
1600 return 0;
1601 }
1602
1603 /* If a variable is assigned in a loop, replace all references to the value
1604 * from outside the loop with a phi value.
1605 */
1606 static void
1607 bld_replace_value(struct nv_pc *pc, struct nv_basic_block *b,
1608 struct nv_value *old_val,
1609 struct nv_value *new_val)
1610 {
1611 struct nv_instruction *nvi;
1612
1613 for (nvi = b->entry; nvi; nvi = nvi->next) {
1614 int s;
1615 for (s = 0; s < 5; ++s) {
1616 if (!nvi->src[s])
1617 continue;
1618 if (nvi->src[s]->value == old_val)
1619 nv_reference(pc, &nvi->src[s], new_val);
1620 }
1621 if (nvi->flags_src && nvi->flags_src->value == old_val)
1622 nv_reference(pc, &nvi->flags_src, new_val);
1623 }
1624
1625 b->pass_seq = pc->pass_seq;
1626
1627 if (b->out[0] && b->out[0]->pass_seq < pc->pass_seq)
1628 bld_replace_value(pc, b->out[0], old_val, new_val);
1629
1630 if (b->out[1] && b->out[1]->pass_seq < pc->pass_seq)
1631 bld_replace_value(pc, b->out[1], old_val, new_val);
1632 }