2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
28 #include "nouveau/nouveau_util.h"
29 #include "nv50_context.h"
30 #include "nv50_resource.h"
32 static INLINE
uint32_t
33 nv50_vbo_type_to_hw(enum pipe_format format
)
35 const struct util_format_description
*desc
;
37 desc
= util_format_description(format
);
40 switch (desc
->channel
[0].type
) {
41 case UTIL_FORMAT_TYPE_FLOAT
:
42 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT
;
43 case UTIL_FORMAT_TYPE_UNSIGNED
:
44 if (desc
->channel
[0].normalized
) {
45 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UNORM
;
47 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_USCALED
;
48 case UTIL_FORMAT_TYPE_SIGNED
:
49 if (desc
->channel
[0].normalized
) {
50 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SNORM
;
52 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SSCALED
;
54 case PIPE_FORMAT_TYPE_UINT:
55 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UINT;
56 case PIPE_FORMAT_TYPE_SINT:
57 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SINT; */
63 static INLINE
uint32_t
64 nv50_vbo_size_to_hw(unsigned size
, unsigned nr_c
)
66 static const uint32_t hw_values
[] = {
68 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8
,
69 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8
,
70 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8
,
71 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8_8
,
72 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16
,
73 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16
,
74 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16
,
75 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16_16
,
77 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32
,
78 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32
,
79 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32
,
80 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32
};
82 /* we'd also have R11G11B10 and R10G10B10A2 */
84 assert(nr_c
> 0 && nr_c
<= 4);
90 return hw_values
[size
+ (nr_c
- 1)];
93 static INLINE
uint32_t
94 nv50_vbo_vtxelt_to_hw(struct pipe_vertex_element
*ve
)
96 uint32_t hw_type
, hw_size
;
97 enum pipe_format pf
= ve
->src_format
;
98 const struct util_format_description
*desc
;
99 unsigned size
, nr_components
;
101 desc
= util_format_description(pf
);
104 size
= util_format_get_component_bits(pf
, UTIL_FORMAT_COLORSPACE_RGB
, 0);
105 nr_components
= util_format_get_nr_components(pf
);
107 hw_type
= nv50_vbo_type_to_hw(pf
);
108 hw_size
= nv50_vbo_size_to_hw(size
, nr_components
);
110 if (!hw_type
|| !hw_size
) {
111 NOUVEAU_ERR("unsupported vbo format: %s\n", util_format_name(pf
));
116 if (desc
->swizzle
[0] == UTIL_FORMAT_SWIZZLE_Z
) /* BGRA */
117 hw_size
|= (1 << 31); /* no real swizzle bits :-( */
119 return (hw_type
| hw_size
);
123 struct nouveau_bo
*bo
;
131 instance_init(struct nv50_context
*nv50
, struct instance
*a
, unsigned first
)
135 for (i
= 0; i
< nv50
->vtxelt
->num_elements
; i
++) {
136 struct pipe_vertex_element
*ve
= &nv50
->vtxelt
->pipe
[i
];
137 struct pipe_vertex_buffer
*vb
;
139 a
[i
].divisor
= ve
->instance_divisor
;
141 vb
= &nv50
->vtxbuf
[ve
->vertex_buffer_index
];
143 a
[i
].bo
= nv50_resource(vb
->buffer
)->bo
;
144 a
[i
].stride
= vb
->stride
;
145 a
[i
].step
= first
% a
[i
].divisor
;
146 a
[i
].delta
= vb
->buffer_offset
+ ve
->src_offset
+
147 (first
* a
[i
].stride
);
153 instance_step(struct nv50_context
*nv50
, struct instance
*a
)
155 struct nouveau_channel
*chan
= nv50
->screen
->tesla
->channel
;
156 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
159 for (i
= 0; i
< nv50
->vtxelt
->num_elements
; i
++) {
163 BEGIN_RING(chan
, tesla
,
164 NV50TCL_VERTEX_ARRAY_START_HIGH(i
), 2);
165 OUT_RELOCh(chan
, a
[i
].bo
, a
[i
].delta
, NOUVEAU_BO_RD
|
166 NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
);
167 OUT_RELOCl(chan
, a
[i
].bo
, a
[i
].delta
, NOUVEAU_BO_RD
|
168 NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
);
169 if (++a
[i
].step
== a
[i
].divisor
) {
171 a
[i
].delta
+= a
[i
].stride
;
177 nv50_draw_arrays_instanced(struct pipe_context
*pipe
,
178 unsigned mode
, unsigned start
, unsigned count
,
179 unsigned startInstance
, unsigned instanceCount
)
181 struct nv50_context
*nv50
= nv50_context(pipe
);
182 struct nouveau_channel
*chan
= nv50
->screen
->tesla
->channel
;
183 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
184 struct instance a
[16];
185 unsigned prim
= nv50_prim(mode
);
187 instance_init(nv50
, a
, startInstance
);
188 if (!nv50_state_validate(nv50
, 10 + 16*3))
191 if (nv50
->vbo_fifo
) {
192 nv50_push_elements_instanced(pipe
, NULL
, 0, 0, mode
, start
,
193 count
, startInstance
,
198 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 2);
199 OUT_RING (chan
, NV50_CB_AUX
| (24 << 8));
200 OUT_RING (chan
, startInstance
);
201 while (instanceCount
--) {
202 if (AVAIL_RING(chan
) < (7 + 16*3)) {
204 if (!nv50_state_validate(nv50
, 7 + 16*3)) {
209 instance_step(nv50
, a
);
211 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BEGIN
, 1);
212 OUT_RING (chan
, prim
);
213 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BUFFER_FIRST
, 2);
214 OUT_RING (chan
, start
);
215 OUT_RING (chan
, count
);
216 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_END
, 1);
224 nv50_draw_arrays(struct pipe_context
*pipe
, unsigned mode
, unsigned start
,
227 nv50_draw_arrays_instanced(pipe
, mode
, start
, count
, 0, 1);
231 struct nv50_context
*nv50
;
236 inline_elt08(void *priv
, unsigned start
, unsigned count
)
238 struct inline_ctx
*ctx
= priv
;
239 struct nouveau_grobj
*tesla
= ctx
->nv50
->screen
->tesla
;
240 struct nouveau_channel
*chan
= tesla
->channel
;
241 uint8_t *map
= (uint8_t *)ctx
->map
+ start
;
244 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U32
, 1);
245 OUT_RING (chan
, map
[0]);
254 BEGIN_RING_NI(chan
, tesla
, NV50TCL_VB_ELEMENT_U16
, count
);
256 OUT_RING(chan
, (map
[1] << 16) | map
[0]);
262 inline_elt16(void *priv
, unsigned start
, unsigned count
)
264 struct inline_ctx
*ctx
= priv
;
265 struct nouveau_grobj
*tesla
= ctx
->nv50
->screen
->tesla
;
266 struct nouveau_channel
*chan
= tesla
->channel
;
267 uint16_t *map
= (uint16_t *)ctx
->map
+ start
;
270 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U32
, 1);
271 OUT_RING (chan
, map
[0]);
280 BEGIN_RING_NI(chan
, tesla
, NV50TCL_VB_ELEMENT_U16
, count
);
282 OUT_RING(chan
, (map
[1] << 16) | map
[0]);
288 inline_elt32(void *priv
, unsigned start
, unsigned count
)
290 struct inline_ctx
*ctx
= priv
;
291 struct nouveau_grobj
*tesla
= ctx
->nv50
->screen
->tesla
;
292 struct nouveau_channel
*chan
= tesla
->channel
;
294 BEGIN_RING_NI(chan
, tesla
, NV50TCL_VB_ELEMENT_U32
, count
);
295 OUT_RINGp (chan
, (uint32_t *)ctx
->map
+ start
, count
);
299 inline_edgeflag(void *priv
, boolean enabled
)
301 struct inline_ctx
*ctx
= priv
;
302 struct nouveau_grobj
*tesla
= ctx
->nv50
->screen
->tesla
;
303 struct nouveau_channel
*chan
= tesla
->channel
;
305 BEGIN_RING(chan
, tesla
, NV50TCL_EDGEFLAG_ENABLE
, 1);
306 OUT_RING (chan
, enabled
? 1 : 0);
310 nv50_draw_elements_inline(struct pipe_context
*pipe
,
311 struct pipe_resource
*indexBuffer
, unsigned indexSize
,
312 unsigned mode
, unsigned start
, unsigned count
,
313 unsigned startInstance
, unsigned instanceCount
)
315 struct nv50_context
*nv50
= nv50_context(pipe
);
316 struct nouveau_channel
*chan
= nv50
->screen
->tesla
->channel
;
317 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
318 struct pipe_transfer
*transfer
;
319 struct instance a
[16];
320 struct inline_ctx ctx
;
321 struct u_split_prim s
;
325 overhead
= 16*3; /* potential instance adjustments */
326 overhead
+= 4; /* Begin()/End() */
327 overhead
+= 4; /* potential edgeflag disable/reenable */
328 overhead
+= 3; /* potentially 3 VTX_ELT_U16/U32 packet headers */
332 s
.emit
= inline_elt08
;
335 s
.emit
= inline_elt16
;
337 s
.emit
= inline_elt32
;
338 s
.edge
= inline_edgeflag
;
341 ctx
.map
= pipe_buffer_map(pipe
, indexBuffer
, PIPE_TRANSFER_READ
, &transfer
);
346 instance_init(nv50
, a
, startInstance
);
347 if (!nv50_state_validate(nv50
, overhead
+ 6 + 3))
350 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 2);
351 OUT_RING (chan
, NV50_CB_AUX
| (24 << 8));
352 OUT_RING (chan
, startInstance
);
353 while (instanceCount
--) {
357 u_split_prim_init(&s
, mode
, start
, count
);
359 if (AVAIL_RING(chan
) < (overhead
+ 6)) {
361 if (!nv50_state_validate(nv50
, (overhead
+ 6))) {
367 max_verts
= AVAIL_RING(chan
) - overhead
;
368 if (max_verts
> 2047)
372 instance_step(nv50
, a
);
374 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BEGIN
, 1);
375 OUT_RING (chan
, nv50_prim(s
.mode
) | (nzi
? (1<<28) : 0));
376 done
= u_split_prim_next(&s
, max_verts
);
377 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_END
, 1);
384 pipe_buffer_unmap(pipe
, indexBuffer
, transfer
);
388 nv50_draw_elements_instanced(struct pipe_context
*pipe
,
389 struct pipe_resource
*indexBuffer
,
390 unsigned indexSize
, int indexBias
,
391 unsigned mode
, unsigned start
, unsigned count
,
392 unsigned startInstance
, unsigned instanceCount
)
394 struct nv50_context
*nv50
= nv50_context(pipe
);
395 struct nouveau_channel
*chan
= nv50
->screen
->tesla
->channel
;
396 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
397 struct instance a
[16];
398 unsigned prim
= nv50_prim(mode
);
400 instance_init(nv50
, a
, startInstance
);
401 if (!nv50_state_validate(nv50
, 13 + 16*3))
404 assert(indexBias
== 0);
406 if (nv50
->vbo_fifo
) {
407 nv50_push_elements_instanced(pipe
, indexBuffer
, indexSize
,
408 indexBias
, mode
, start
, count
,
409 startInstance
, instanceCount
);
412 if (!(indexBuffer
->bind
& PIPE_BIND_INDEX_BUFFER
) || indexSize
== 1) {
413 nv50_draw_elements_inline(pipe
, indexBuffer
, indexSize
,
414 mode
, start
, count
, startInstance
,
419 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 2);
420 OUT_RING (chan
, NV50_CB_AUX
| (24 << 8));
421 OUT_RING (chan
, startInstance
);
422 while (instanceCount
--) {
423 if (AVAIL_RING(chan
) < (7 + 16*3)) {
425 if (!nv50_state_validate(nv50
, 10 + 16*3)) {
430 instance_step(nv50
, a
);
432 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BEGIN
, 1);
433 OUT_RING (chan
, prim
);
434 if (indexSize
== 4) {
435 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U32
| 0x30000, 0);
436 OUT_RING (chan
, count
);
437 nouveau_pushbuf_submit(chan
,
438 nv50_resource(indexBuffer
)->bo
,
439 start
<< 2, count
<< 2);
441 if (indexSize
== 2) {
442 unsigned vb_start
= (start
& ~1);
443 unsigned vb_end
= (start
+ count
+ 1) & ~1;
444 unsigned dwords
= (vb_end
- vb_start
) >> 1;
446 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U16_SETUP
, 1);
447 OUT_RING (chan
, ((start
& 1) << 31) | count
);
448 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U16
| 0x30000, 0);
449 OUT_RING (chan
, dwords
);
450 nouveau_pushbuf_submit(chan
,
451 nv50_resource(indexBuffer
)->bo
,
452 vb_start
<< 1, dwords
<< 2);
453 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U16_SETUP
, 1);
456 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_END
, 1);
464 nv50_draw_elements(struct pipe_context
*pipe
,
465 struct pipe_resource
*indexBuffer
,
466 unsigned indexSize
, int indexBias
,
467 unsigned mode
, unsigned start
, unsigned count
)
469 nv50_draw_elements_instanced(pipe
, indexBuffer
, indexSize
, indexBias
,
470 mode
, start
, count
, 0, 1);
473 static INLINE boolean
474 nv50_vbo_static_attrib(struct nv50_context
*nv50
, unsigned attrib
,
475 struct nouveau_stateobj
**pso
,
476 struct pipe_vertex_element
*ve
,
477 struct pipe_vertex_buffer
*vb
)
480 struct nouveau_stateobj
*so
;
481 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
482 struct nouveau_bo
*bo
= nv50_resource(vb
->buffer
)->bo
;
485 unsigned nr_components
= util_format_get_nr_components(ve
->src_format
);
487 ret
= nouveau_bo_map(bo
, NOUVEAU_BO_RD
);
491 util_format_read_4f(ve
->src_format
, v
, 0, (uint8_t *)bo
->map
+
492 (vb
->buffer_offset
+ ve
->src_offset
), 0,
496 *pso
= so
= so_new(nv50
->vtxelt
->num_elements
,
497 nv50
->vtxelt
->num_elements
* 4, 0);
499 switch (nr_components
) {
501 so_method(so
, tesla
, NV50TCL_VTX_ATTR_4F_X(attrib
), 4);
502 so_data (so
, fui(v
[0]));
503 so_data (so
, fui(v
[1]));
504 so_data (so
, fui(v
[2]));
505 so_data (so
, fui(v
[3]));
508 so_method(so
, tesla
, NV50TCL_VTX_ATTR_3F_X(attrib
), 3);
509 so_data (so
, fui(v
[0]));
510 so_data (so
, fui(v
[1]));
511 so_data (so
, fui(v
[2]));
514 so_method(so
, tesla
, NV50TCL_VTX_ATTR_2F_X(attrib
), 2);
515 so_data (so
, fui(v
[0]));
516 so_data (so
, fui(v
[1]));
519 if (attrib
== nv50
->vertprog
->cfg
.edgeflag_in
) {
520 so_method(so
, tesla
, NV50TCL_EDGEFLAG_ENABLE
, 1);
521 so_data (so
, v
[0] ? 1 : 0);
523 so_method(so
, tesla
, NV50TCL_VTX_ATTR_1F(attrib
), 1);
524 so_data (so
, fui(v
[0]));
527 nouveau_bo_unmap(bo
);
531 nouveau_bo_unmap(bo
);
536 nv50_vtxelt_construct(struct nv50_vtxelt_stateobj
*cso
)
540 for (i
= 0; i
< cso
->num_elements
; ++i
) {
541 struct pipe_vertex_element
*ve
= &cso
->pipe
[i
];
543 cso
->hw
[i
] = nv50_vbo_vtxelt_to_hw(ve
);
547 struct nouveau_stateobj
*
548 nv50_vbo_validate(struct nv50_context
*nv50
)
550 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
551 struct nouveau_stateobj
*vtxbuf
, *vtxfmt
, *vtxattr
;
554 /* don't validate if Gallium took away our buffers */
555 if (nv50
->vtxbuf_nr
== 0)
559 if (nv50
->screen
->force_push
||
560 nv50
->vertprog
->cfg
.edgeflag_in
< 16)
561 nv50
->vbo_fifo
= 0xffff;
563 for (i
= 0; i
< nv50
->vtxbuf_nr
; i
++) {
564 if (nv50
->vtxbuf
[i
].stride
&&
565 !(nv50
->vtxbuf
[i
].buffer
->bind
& PIPE_BIND_VERTEX_BUFFER
))
566 nv50
->vbo_fifo
= 0xffff;
569 n_ve
= MAX2(nv50
->vtxelt
->num_elements
, nv50
->state
.vtxelt_nr
);
572 vtxbuf
= so_new(n_ve
* 2, n_ve
* 5, nv50
->vtxelt
->num_elements
* 4);
573 vtxfmt
= so_new(1, n_ve
, 0);
574 so_method(vtxfmt
, tesla
, NV50TCL_VERTEX_ARRAY_ATTRIB(0), n_ve
);
576 for (i
= 0; i
< nv50
->vtxelt
->num_elements
; i
++) {
577 struct pipe_vertex_element
*ve
= &nv50
->vtxelt
->pipe
[i
];
578 struct pipe_vertex_buffer
*vb
=
579 &nv50
->vtxbuf
[ve
->vertex_buffer_index
];
580 struct nouveau_bo
*bo
= nv50_resource(vb
->buffer
)->bo
;
581 uint32_t hw
= nv50
->vtxelt
->hw
[i
];
584 nv50_vbo_static_attrib(nv50
, i
, &vtxattr
, ve
, vb
)) {
585 so_data(vtxfmt
, hw
| (1 << 4));
587 so_method(vtxbuf
, tesla
,
588 NV50TCL_VERTEX_ARRAY_FORMAT(i
), 1);
591 nv50
->vbo_fifo
&= ~(1 << i
);
595 if (nv50
->vbo_fifo
) {
596 so_data (vtxfmt
, hw
| (ve
->instance_divisor
? (1 << 4) : i
));
597 so_method(vtxbuf
, tesla
,
598 NV50TCL_VERTEX_ARRAY_FORMAT(i
), 1);
603 so_data(vtxfmt
, hw
| i
);
605 so_method(vtxbuf
, tesla
, NV50TCL_VERTEX_ARRAY_FORMAT(i
), 3);
606 so_data (vtxbuf
, 0x20000000 |
607 (ve
->instance_divisor
? 0 : vb
->stride
));
608 so_reloc (vtxbuf
, bo
, vb
->buffer_offset
+
609 ve
->src_offset
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
|
610 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
611 so_reloc (vtxbuf
, bo
, vb
->buffer_offset
+
612 ve
->src_offset
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
|
613 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
615 /* vertex array limits */
616 so_method(vtxbuf
, tesla
, NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i
), 2);
617 so_reloc (vtxbuf
, bo
, vb
->buffer
->width0
- 1,
618 NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
|
619 NOUVEAU_BO_HIGH
, 0, 0);
620 so_reloc (vtxbuf
, bo
, vb
->buffer
->width0
- 1,
621 NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
|
622 NOUVEAU_BO_LOW
, 0, 0);
624 for (; i
< n_ve
; ++i
) {
625 so_data (vtxfmt
, 0x7e080010);
627 so_method(vtxbuf
, tesla
, NV50TCL_VERTEX_ARRAY_FORMAT(i
), 1);
630 nv50
->state
.vtxelt_nr
= nv50
->vtxelt
->num_elements
;
632 so_ref (vtxbuf
, &nv50
->state
.vtxbuf
);
633 so_ref (vtxattr
, &nv50
->state
.vtxattr
);
634 so_ref (NULL
, &vtxbuf
);
635 so_ref (NULL
, &vtxattr
);