src/gallium/drivers/nv50/nv50_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "pipe/p_context.h"
  24 #include "pipe/p_state.h"
  25 #include "util/u_inlines.h"
  26 #include "util/u_format.h"
  27 #include "translate/translate.h"
  28
  29 #include "nv50_context.h"
  30 #include "nv50_resource.h"
  31
  32 #include "nv50_3d.xml.h"
  33
  34 void
  35 nv50_vertex_state_delete(struct pipe_context *pipe,
  36                          void *hwcso)
  37 {
  38    struct nv50_vertex_stateobj *so = hwcso;
  39
  40    if (so->translate)
  41       so->translate->release(so->translate);
  42    FREE(hwcso);
  43 }
  44
  45 void *
  46 nv50_vertex_state_create(struct pipe_context *pipe,
  47                          unsigned num_elements,
  48                          const struct pipe_vertex_element *elements)
  49 {
  50     struct nv50_vertex_stateobj *so;
  51     struct translate_key transkey;
  52     unsigned i;
  53
  54     so = MALLOC(sizeof(*so) +
  55                 num_elements * sizeof(struct nv50_vertex_element));
  56     if (!so)
  57         return NULL;
  58     so->num_elements = num_elements;
  59     so->instance_elts = 0;
  60     so->instance_bufs = 0;
  61     so->need_conversion = FALSE;
  62
  63     transkey.nr_elements = 0;
  64     transkey.output_stride = 0;
  65
  66     for (i = 0; i < num_elements; ++i) {
  67         const struct pipe_vertex_element *ve = &elements[i];
  68         const unsigned vbi = ve->vertex_buffer_index;
  69         enum pipe_format fmt = ve->src_format;
  70
  71         so->element[i].pipe = elements[i];
  72         so->element[i].state = nv50_format_table[fmt].vtx;
  73
  74         if (!so->element[i].state) {
  75             switch (util_format_get_nr_components(fmt)) {
  76             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  77             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  78             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  79             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  80             default:
  81                 assert(0);
  82                 return NULL;
  83             }
  84             so->element[i].state = nv50_format_table[fmt].vtx;
  85             so->need_conversion = TRUE;
  86         }
  87         so->element[i].state |= i;
  88
  89         if (1) {
  90             unsigned j = transkey.nr_elements++;
  91
  92             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
  93             transkey.element[j].input_format = ve->src_format;
  94             transkey.element[j].input_buffer = vbi;
  95             transkey.element[j].input_offset = ve->src_offset;
  96             transkey.element[j].instance_divisor = ve->instance_divisor;
  97
  98             transkey.element[j].output_format = fmt;
  99             transkey.element[j].output_offset = transkey.output_stride;
 100             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
 101
 102             if (unlikely(ve->instance_divisor)) {
 103                so->instance_elts |= 1 << i;
 104                so->instance_bufs |= 1 << vbi;
 105             }
 106         }
 107     }
 108
 109     so->translate = translate_create(&transkey);
 110     so->vertex_size = transkey.output_stride / 4;
 111     so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
 112        MAX2(so->vertex_size, 1);
 113
 114     return so;
 115 }
 116
 117 #define NV50_3D_VERTEX_ATTRIB_INACTIVE              \
 118    NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT |         \
 119    NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
 120    NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
 121
 122 static void
 123 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
 124                   struct pipe_vertex_element *ve, unsigned attr)
 125 {
 126    const void *data;
 127    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 128    struct nv04_resource *res = nv04_resource(vb->buffer);
 129    float v[4];
 130    const unsigned nc = util_format_get_nr_components(ve->src_format);
 131
 132    data = nouveau_resource_map_offset(&nv50->base, res, vb->buffer_offset +
 133                                       ve->src_offset, NOUVEAU_BO_RD);
 134
 135    util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
 136
 137    switch (nc) {
 138    case 4:
 139       BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
 140       PUSH_DATAf(push, v[0]);
 141       PUSH_DATAf(push, v[1]);
 142       PUSH_DATAf(push, v[2]);
 143       PUSH_DATAf(push, v[3]);
 144       break;
 145    case 3:
 146       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
 147       PUSH_DATAf(push, v[0]);
 148       PUSH_DATAf(push, v[1]);
 149       PUSH_DATAf(push, v[2]);
 150       break;
 151    case 2:
 152       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
 153       PUSH_DATAf(push, v[0]);
 154       PUSH_DATAf(push, v[1]);
 155       break;
 156    case 1:
 157       if (attr == nv50->vertprog->vp.edgeflag) {
 158          BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 159          PUSH_DATA (push, v[0] ? 1 : 0);
 160       }
 161       BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
 162       PUSH_DATAf(push, v[0]);
 163       break;
 164    default:
 165       assert(0);
 166       break;
 167    }
 168 }
 169
 170 static INLINE void
 171 nv50_vbuf_range(struct nv50_context *nv50, int vbi,
 172                 uint32_t *base, uint32_t *size)
 173 {
 174    if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
 175       /* TODO: use min and max instance divisor to get a proper range */
 176       *base = 0;
 177       *size = nv50->vtxbuf[vbi].buffer->width0;
 178    } else {
 179       assert(nv50->vbo_max_index != ~0);
 180       *base = nv50->vbo_min_index * nv50->vtxbuf[vbi].stride;
 181       *size = (nv50->vbo_max_index -
 182                nv50->vbo_min_index + 1) * nv50->vtxbuf[vbi].stride;
 183    }
 184 }
 185
 186 static void
 187 nv50_prevalidate_vbufs(struct nv50_context *nv50)
 188 {
 189    struct pipe_vertex_buffer *vb;
 190    struct nv04_resource *buf;
 191    int i;
 192    uint32_t base, size;
 193
 194    nv50->vbo_fifo = nv50->vbo_user = 0;
 195
 196    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX);
 197
 198    for (i = 0; i < nv50->num_vtxbufs; ++i) {
 199       vb = &nv50->vtxbuf[i];
 200       if (!vb->stride)
 201          continue;
 202       buf = nv04_resource(vb->buffer);
 203
 204       /* NOTE: user buffers with temporary storage count as mapped by GPU */
 205       if (!nouveau_resource_mapped_by_gpu(vb->buffer)) {
 206          if (nv50->vbo_push_hint) {
 207             nv50->vbo_fifo = ~0;
 208             continue;
 209          } else {
 210             if (buf->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY) {
 211                nv50->vbo_user |= 1 << i;
 212                assert(vb->stride > vb->buffer_offset);
 213                nv50_vbuf_range(nv50, i, &base, &size);
 214                nouveau_user_buffer_upload(&nv50->base, buf, base, size);
 215             } else {
 216                nouveau_buffer_migrate(&nv50->base, buf, NOUVEAU_BO_GART);
 217             }
 218             nv50->base.vbo_dirty = TRUE;
 219          }
 220       }
 221       BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
 222    }
 223 }
 224
 225 static void
 226 nv50_update_user_vbufs(struct nv50_context *nv50)
 227 {
 228    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 229    uint32_t base, offset, size;
 230    int i;
 231    uint32_t written = 0;
 232
 233    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX);
 234
 235    for (i = 0; i < nv50->vertex->num_elements; ++i) {
 236       struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
 237       const int b = ve->vertex_buffer_index;
 238       struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
 239       struct nv04_resource *buf = nv04_resource(vb->buffer);
 240
 241       if (!(nv50->vbo_user & (1 << b))) {
 242          BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
 243          continue;
 244       }
 245
 246       if (!vb->stride) {
 247          nv50_emit_vtxattr(nv50, vb, ve, i);
 248          continue;
 249       }
 250       nv50_vbuf_range(nv50, b, &base, &size);
 251
 252       if (!(written & (1 << b))) {
 253          written |= 1 << b;
 254          nouveau_user_buffer_upload(&nv50->base, buf, base, size);
 255       }
 256       offset = vb->buffer_offset + ve->src_offset;
 257
 258       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 259       PUSH_DATAh(push, buf->address + base + size - 1);
 260       PUSH_DATA (push, buf->address + base + size - 1);
 261       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
 262       PUSH_DATAh(push, buf->address + offset);
 263       PUSH_DATA (push, buf->address + offset);
 264
 265       BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
 266    }
 267    nv50->base.vbo_dirty = TRUE;
 268 }
 269
 270 static INLINE void
 271 nv50_release_user_vbufs(struct nv50_context *nv50)
 272 {
 273    uint32_t vbo_user = nv50->vbo_user;
 274
 275    while (vbo_user) {
 276       int i = ffs(vbo_user) - 1;
 277       vbo_user &= ~(1 << i);
 278
 279       nouveau_buffer_release_gpu_storage(nv04_resource(nv50->vtxbuf[i].buffer));
 280    }
 281 }
 282
 283 void
 284 nv50_vertex_arrays_validate(struct nv50_context *nv50)
 285 {
 286    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 287    struct nv50_vertex_stateobj *vertex = nv50->vertex;
 288    struct pipe_vertex_buffer *vb;
 289    struct nv50_vertex_element *ve;
 290    unsigned i;
 291
 292    if (unlikely(vertex->need_conversion)) {
 293       nv50->vbo_fifo = ~0;
 294       nv50->vbo_user = 0;
 295    } else {
 296       nv50_prevalidate_vbufs(nv50);
 297    }
 298
 299    BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), vertex->num_elements);
 300    for (i = 0; i < vertex->num_elements; ++i) {
 301       ve = &vertex->element[i];
 302       vb = &nv50->vtxbuf[ve->pipe.vertex_buffer_index];
 303
 304       if (likely(vb->stride) || nv50->vbo_fifo) {
 305          PUSH_DATA(push, ve->state);
 306       } else {
 307          PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
 308          nv50->vbo_fifo &= ~(1 << i);
 309       }
 310    }
 311
 312    for (i = 0; i < vertex->num_elements; ++i) {
 313       struct nv04_resource *res;
 314       unsigned size, offset;
 315
 316       ve = &vertex->element[i];
 317       vb = &nv50->vtxbuf[ve->pipe.vertex_buffer_index];
 318
 319       if (unlikely(ve->pipe.instance_divisor)) {
 320          if (!(nv50->state.instance_elts & (1 << i))) {
 321             BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 322             PUSH_DATA (push, 1);
 323          }
 324          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
 325          PUSH_DATA (push, ve->pipe.instance_divisor);
 326       } else
 327       if (unlikely(nv50->state.instance_elts & (1 << i))) {
 328          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 329          PUSH_DATA (push, 0);
 330       }
 331
 332       res = nv04_resource(vb->buffer);
 333
 334       if (nv50->vbo_fifo || unlikely(vb->stride == 0)) {
 335          if (!nv50->vbo_fifo)
 336             nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
 337          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 338          PUSH_DATA (push, 0);
 339          continue;
 340       }
 341
 342       size = vb->buffer->width0;
 343       offset = ve->pipe.src_offset + vb->buffer_offset;
 344
 345       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 346       PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 347       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 348       PUSH_DATAh(push, res->address + size - 1);
 349       PUSH_DATA (push, res->address + size - 1);
 350       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
 351       PUSH_DATAh(push, res->address + offset);
 352       PUSH_DATA (push, res->address + offset);
 353    }
 354    for (; i < nv50->state.num_vtxelts; ++i) {
 355       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(i)), 1);
 356       PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 357       if (unlikely(nv50->state.instance_elts & (1 << i))) {
 358          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 359          PUSH_DATA (push, 0);
 360       }
 361       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 362       PUSH_DATA (push, 0);
 363    }
 364
 365    nv50->state.num_vtxelts = vertex->num_elements;
 366    nv50->state.instance_elts = vertex->instance_elts;
 367 }
 368
 369 #define NV50_PRIM_GL_CASE(n) \
 370    case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 371
 372 static INLINE unsigned
 373 nv50_prim_gl(unsigned prim)
 374 {
 375    switch (prim) {
 376    NV50_PRIM_GL_CASE(POINTS);
 377    NV50_PRIM_GL_CASE(LINES);
 378    NV50_PRIM_GL_CASE(LINE_LOOP);
 379    NV50_PRIM_GL_CASE(LINE_STRIP);
 380    NV50_PRIM_GL_CASE(TRIANGLES);
 381    NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
 382    NV50_PRIM_GL_CASE(TRIANGLE_FAN);
 383    NV50_PRIM_GL_CASE(QUADS);
 384    NV50_PRIM_GL_CASE(QUAD_STRIP);
 385    NV50_PRIM_GL_CASE(POLYGON);
 386    NV50_PRIM_GL_CASE(LINES_ADJACENCY);
 387    NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 388    NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 389    NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 390    default:
 391       return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 392       break;
 393    }
 394 }
 395
 396 static void
 397 nv50_draw_arrays(struct nv50_context *nv50,
 398                  unsigned mode, unsigned start, unsigned count,
 399                  unsigned instance_count)
 400 {
 401    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 402    unsigned prim;
 403
 404    if (nv50->state.index_bias) {
 405       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 406       PUSH_DATA (push, 0);
 407       nv50->state.index_bias = 0;
 408    }
 409
 410    prim = nv50_prim_gl(mode);
 411
 412    while (instance_count--) {
 413       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 414       PUSH_DATA (push, prim);
 415       BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
 416       PUSH_DATA (push, start);
 417       PUSH_DATA (push, count);
 418       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 419       PUSH_DATA (push, 0);
 420
 421       prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 422    }
 423 }
 424
 425 static void
 426 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, uint8_t *map,
 427                               unsigned start, unsigned count)
 428 {
 429    map += start;
 430
 431    if (count & 3) {
 432       unsigned i;
 433       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
 434       for (i = 0; i < (count & 3); ++i)
 435          PUSH_DATA(push, *map++);
 436       count &= ~3;
 437    }
 438    while (count) {
 439       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 440
 441       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
 442       for (i = 0; i < nr; ++i) {
 443          PUSH_DATA(push,
 444                    (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 445          map += 4;
 446       }
 447       count -= nr * 4;
 448    }
 449 }
 450
 451 static void
 452 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, uint16_t *map,
 453                               unsigned start, unsigned count)
 454 {
 455    map += start;
 456
 457    if (count & 1) {
 458       count &= ~1;
 459       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 460       PUSH_DATA (push, *map++);
 461    }
 462    while (count) {
 463       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 464
 465       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 466       for (i = 0; i < nr; ++i) {
 467          PUSH_DATA(push, (map[1] << 16) | map[0]);
 468          map += 2;
 469       }
 470       count -= nr * 2;
 471    }
 472 }
 473
 474 static void
 475 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, uint32_t *map,
 476                               unsigned start, unsigned count)
 477 {
 478    map += start;
 479
 480    while (count) {
 481       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 482
 483       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
 484       PUSH_DATAp(push, map, nr);
 485
 486       map += nr;
 487       count -= nr;
 488    }
 489 }
 490
 491 static void
 492 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push, uint32_t *map,
 493                                     unsigned start, unsigned count)
 494 {
 495    map += start;
 496
 497    if (count & 1) {
 498       count--;
 499       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 500       PUSH_DATA (push, *map++);
 501    }
 502    while (count) {
 503       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 504
 505       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 506       for (i = 0; i < nr; ++i) {
 507          PUSH_DATA(push, (map[1] << 16) | map[0]);
 508          map += 2;
 509       }
 510       count -= nr * 2;
 511    }
 512 }
 513
 514 static void
 515 nv50_draw_elements(struct nv50_context *nv50, boolean shorten,
 516                    unsigned mode, unsigned start, unsigned count,
 517                    unsigned instance_count, int32_t index_bias)
 518 {
 519    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 520    void *data;
 521    struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
 522    unsigned prim;
 523    const unsigned index_size = nv50->idxbuf.index_size;
 524
 525    prim = nv50_prim_gl(mode);
 526
 527    if (index_bias != nv50->state.index_bias) {
 528       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 529       PUSH_DATA (push, index_bias);
 530       nv50->state.index_bias = index_bias;
 531    }
 532
 533    if (nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer)) {
 534       unsigned pb_start;
 535       unsigned pb_bytes;
 536       const unsigned base = buf->offset;
 537
 538       start += nv50->idxbuf.offset >> (index_size >> 1);
 539
 540       while (instance_count--) {
 541          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 542          PUSH_DATA (push, prim);
 543
 544          nouveau_pushbuf_space(push, 8, 0, 1);
 545
 546          switch (index_size) {
 547          case 4:
 548             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
 549             nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
 550             break;
 551          case 2:
 552             pb_start = (start & ~1) * 2;
 553             pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
 554
 555             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 556             PUSH_DATA (push, (start << 31) | count);
 557             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
 558             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 559             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 560             PUSH_DATA (push, 0);
 561             break;
 562          default:
 563             assert(index_size == 1);
 564             pb_start = start & ~3;
 565             pb_bytes = ((start + count + 3) & ~3) - pb_start;
 566
 567             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 568             PUSH_DATA (push, (start << 30) | count);
 569             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
 570             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 571             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 572             PUSH_DATA (push, 0);
 573             break;
 574          }
 575          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 576          PUSH_DATA (push, 0);
 577
 578          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 579       }
 580    } else {
 581       data = nouveau_resource_map_offset(&nv50->base, buf,
 582                                          nv50->idxbuf.offset, NOUVEAU_BO_RD);
 583       if (!data)
 584          return;
 585
 586       while (instance_count--) {
 587          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 588          PUSH_DATA (push, prim);
 589          switch (index_size) {
 590          case 1:
 591             nv50_draw_elements_inline_u08(push, data, start, count);
 592             break;
 593          case 2:
 594             nv50_draw_elements_inline_u16(push, data, start, count);
 595             break;
 596          case 4:
 597             if (shorten)
 598                nv50_draw_elements_inline_u32_short(push, data, start, count);
 599             else
 600                nv50_draw_elements_inline_u32(push, data, start, count);
 601             break;
 602          default:
 603             assert(0);
 604             return;
 605          }
 606          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 607          PUSH_DATA (push, 0);
 608
 609          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 610       }
 611    }
 612 }
 613
 614 static void
 615 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
 616 {
 617    struct nv50_screen *screen = chan->user_priv;
 618
 619    nouveau_fence_update(&screen->base, TRUE);
 620
 621    nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, TRUE);
 622 }
 623
 624 void
 625 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 626 {
 627    struct nv50_context *nv50 = nv50_context(pipe);
 628    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 629
 630    /* For picking only a few vertices from a large user buffer, push is better,
 631     * if index count is larger and we expect repeated vertices, suggest upload.
 632     */
 633    nv50->vbo_push_hint = /* the 64 is heuristic */
 634       !(info->indexed &&
 635         ((info->max_index - info->min_index + 64) < info->count));
 636
 637    nv50->vbo_min_index = info->min_index;
 638    nv50->vbo_max_index = info->max_index;
 639
 640    if (nv50->vbo_push_hint != !!nv50->vbo_fifo)
 641       nv50->dirty |= NV50_NEW_ARRAYS;
 642
 643    if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_VERTEX | NV50_NEW_ARRAYS)))
 644       nv50_update_user_vbufs(nv50);
 645
 646    nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
 647
 648    push->kick_notify = nv50_draw_vbo_kick_notify;
 649
 650    if (nv50->vbo_fifo) {
 651       nv50_push_vbo(nv50, info);
 652       push->kick_notify = nv50_default_kick_notify;
 653       nouveau_pushbuf_bufctx(push, NULL);
 654       return;
 655    }
 656
 657    if (nv50->state.instance_base != info->start_instance) {
 658       nv50->state.instance_base = info->start_instance;
 659       /* NOTE: this does not affect the shader input, should it ? */
 660       BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
 661       PUSH_DATA (push, info->start_instance);
 662    }
 663
 664    if (nv50->base.vbo_dirty) {
 665       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 666       PUSH_DATA (push, 0);
 667       nv50->base.vbo_dirty = FALSE;
 668    }
 669
 670    if (!info->indexed) {
 671       nv50_draw_arrays(nv50,
 672                        info->mode, info->start, info->count,
 673                        info->instance_count);
 674    } else {
 675       boolean shorten = info->max_index <= 65535;
 676
 677       assert(nv50->idxbuf.buffer);
 678
 679       if (info->primitive_restart != nv50->state.prim_restart) {
 680          if (info->primitive_restart) {
 681             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
 682             PUSH_DATA (push, 1);
 683             PUSH_DATA (push, info->restart_index);
 684
 685             if (info->restart_index > 65535)
 686                shorten = FALSE;
 687          } else {
 688             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
 689             PUSH_DATA (push, 0);
 690          }
 691          nv50->state.prim_restart = info->primitive_restart;
 692       } else
 693       if (info->primitive_restart) {
 694          BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
 695          PUSH_DATA (push, info->restart_index);
 696
 697          if (info->restart_index > 65535)
 698             shorten = FALSE;
 699       }
 700
 701       nv50_draw_elements(nv50, shorten,
 702                          info->mode, info->start, info->count,
 703                          info->instance_count, info->index_bias);
 704    }
 705    push->kick_notify = nv50_default_kick_notify;
 706
 707    nv50_release_user_vbufs(nv50);
 708
 709    nouveau_pushbuf_bufctx(push, NULL);
 710 }