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cb3ea382f3d8bd0fdedd93bf586fbe00bf3cb081
[mesa.git] / src / gallium / drivers / nv50 / nv50_vbo.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
27 #include "translate/translate.h"
28
29 #include "nv50_context.h"
30 #include "nv50_resource.h"
31
32 #include "nv50_3d.xml.h"
33
34 void
35 nv50_vertex_state_delete(struct pipe_context *pipe,
36 void *hwcso)
37 {
38 struct nv50_vertex_stateobj *so = hwcso;
39
40 if (so->translate)
41 so->translate->release(so->translate);
42 FREE(hwcso);
43 }
44
45 void *
46 nv50_vertex_state_create(struct pipe_context *pipe,
47 unsigned num_elements,
48 const struct pipe_vertex_element *elements)
49 {
50 struct nv50_vertex_stateobj *so;
51 struct translate_key transkey;
52 unsigned i;
53
54 so = MALLOC(sizeof(*so) +
55 num_elements * sizeof(struct nv50_vertex_element));
56 if (!so)
57 return NULL;
58 so->num_elements = num_elements;
59 so->instance_elts = 0;
60 so->instance_bufs = 0;
61 so->need_conversion = FALSE;
62
63 transkey.nr_elements = 0;
64 transkey.output_stride = 0;
65
66 for (i = 0; i < num_elements; ++i) {
67 const struct pipe_vertex_element *ve = &elements[i];
68 const unsigned vbi = ve->vertex_buffer_index;
69 enum pipe_format fmt = ve->src_format;
70
71 so->element[i].pipe = elements[i];
72 so->element[i].state = nv50_format_table[fmt].vtx;
73
74 if (!so->element[i].state) {
75 switch (util_format_get_nr_components(fmt)) {
76 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
77 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
78 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
79 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
80 default:
81 assert(0);
82 return NULL;
83 }
84 so->element[i].state = nv50_format_table[fmt].vtx;
85 so->need_conversion = TRUE;
86 }
87 so->element[i].state |= i;
88
89 if (1) {
90 unsigned j = transkey.nr_elements++;
91
92 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
93 transkey.element[j].input_format = ve->src_format;
94 transkey.element[j].input_buffer = vbi;
95 transkey.element[j].input_offset = ve->src_offset;
96 transkey.element[j].instance_divisor = ve->instance_divisor;
97
98 transkey.element[j].output_format = fmt;
99 transkey.element[j].output_offset = transkey.output_stride;
100 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
101
102 if (unlikely(ve->instance_divisor)) {
103 so->instance_elts |= 1 << i;
104 so->instance_bufs |= 1 << vbi;
105 }
106 }
107 }
108
109 so->translate = translate_create(&transkey);
110 so->vertex_size = transkey.output_stride / 4;
111 so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
112 MAX2(so->vertex_size, 1);
113
114 return so;
115 }
116
117 #define NV50_3D_VERTEX_ATTRIB_INACTIVE \
118 NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT | \
119 NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
120 NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
121
122 static void
123 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
124 struct pipe_vertex_element *ve, unsigned attr)
125 {
126 const void *data;
127 struct nouveau_channel *chan = nv50->screen->base.channel;
128 struct nv04_resource *res = nv04_resource(vb->buffer);
129 float v[4];
130 const unsigned nc = util_format_get_nr_components(ve->src_format);
131
132 data = nouveau_resource_map_offset(&nv50->base, res, vb->buffer_offset +
133 ve->src_offset, NOUVEAU_BO_RD);
134
135 util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
136
137 switch (nc) {
138 case 4:
139 BEGIN_RING(chan, RING_3D(VTX_ATTR_4F_X(attr)), 4);
140 OUT_RINGf (chan, v[0]);
141 OUT_RINGf (chan, v[1]);
142 OUT_RINGf (chan, v[2]);
143 OUT_RINGf (chan, v[3]);
144 break;
145 case 3:
146 BEGIN_RING(chan, RING_3D(VTX_ATTR_3F_X(attr)), 3);
147 OUT_RINGf (chan, v[0]);
148 OUT_RINGf (chan, v[1]);
149 OUT_RINGf (chan, v[2]);
150 break;
151 case 2:
152 BEGIN_RING(chan, RING_3D(VTX_ATTR_2F_X(attr)), 2);
153 OUT_RINGf (chan, v[0]);
154 OUT_RINGf (chan, v[1]);
155 break;
156 case 1:
157 if (attr == nv50->vertprog->vp.edgeflag) {
158 BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
159 OUT_RING (chan, v[0] ? 1 : 0);
160 }
161 BEGIN_RING(chan, RING_3D(VTX_ATTR_1F(attr)), 1);
162 OUT_RINGf (chan, v[0]);
163 break;
164 default:
165 assert(0);
166 break;
167 }
168 }
169
170 static INLINE void
171 nv50_vbuf_range(struct nv50_context *nv50, int vbi,
172 uint32_t *base, uint32_t *size)
173 {
174 if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
175 /* TODO: use min and max instance divisor to get a proper range */
176 *base = 0;
177 *size = nv50->vtxbuf[vbi].buffer->width0;
178 } else {
179 assert(nv50->vbo_max_index != ~0);
180 *base = nv50->vbo_min_index * nv50->vtxbuf[vbi].stride;
181 *size = (nv50->vbo_max_index -
182 nv50->vbo_min_index + 1) * nv50->vtxbuf[vbi].stride;
183 }
184 }
185
186 static void
187 nv50_prevalidate_vbufs(struct nv50_context *nv50)
188 {
189 struct pipe_vertex_buffer *vb;
190 struct nv04_resource *buf;
191 int i;
192 uint32_t base, size;
193
194 nv50->vbo_fifo = nv50->vbo_user = 0;
195
196 nv50_bufctx_reset(nv50, NV50_BUFCTX_VERTEX);
197
198 for (i = 0; i < nv50->num_vtxbufs; ++i) {
199 vb = &nv50->vtxbuf[i];
200 if (!vb->stride)
201 continue;
202 buf = nv04_resource(vb->buffer);
203
204 /* NOTE: user buffers with temporary storage count as mapped by GPU */
205 if (!nouveau_resource_mapped_by_gpu(vb->buffer)) {
206 if (nv50->vbo_push_hint) {
207 nv50->vbo_fifo = ~0;
208 continue;
209 } else {
210 if (buf->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY) {
211 nv50->vbo_user |= 1 << i;
212 assert(vb->stride > vb->buffer_offset);
213 nv50_vbuf_range(nv50, i, &base, &size);
214 nouveau_user_buffer_upload(buf, base, size);
215 } else {
216 nouveau_buffer_migrate(&nv50->base, buf, NOUVEAU_BO_GART);
217 }
218 nv50->base.vbo_dirty = TRUE;
219 }
220 }
221 nv50_bufctx_add_resident(nv50, NV50_BUFCTX_VERTEX, buf, NOUVEAU_BO_RD);
222 }
223 }
224
225 static void
226 nv50_update_user_vbufs(struct nv50_context *nv50)
227 {
228 struct nouveau_channel *chan = nv50->screen->base.channel;
229 uint32_t base, offset, size;
230 int i;
231 uint32_t written = 0;
232
233 for (i = 0; i < nv50->vertex->num_elements; ++i) {
234 struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
235 const int b = ve->vertex_buffer_index;
236 struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
237 struct nv04_resource *buf = nv04_resource(vb->buffer);
238
239 if (!(nv50->vbo_user & (1 << b)))
240 continue;
241
242 if (!vb->stride) {
243 nv50_emit_vtxattr(nv50, vb, ve, i);
244 continue;
245 }
246 nv50_vbuf_range(nv50, b, &base, &size);
247
248 if (!(written & (1 << b))) {
249 written |= 1 << b;
250 nouveau_user_buffer_upload(buf, base, size);
251 }
252 offset = vb->buffer_offset + ve->src_offset;
253
254 MARK_RING (chan, 6, 4);
255 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
256 OUT_RESRCh(chan, buf, base + size - 1, NOUVEAU_BO_RD);
257 OUT_RESRCl(chan, buf, base + size - 1, NOUVEAU_BO_RD);
258 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
259 OUT_RESRCh(chan, buf, offset, NOUVEAU_BO_RD);
260 OUT_RESRCl(chan, buf, offset, NOUVEAU_BO_RD);
261 }
262 nv50->base.vbo_dirty = TRUE;
263 }
264
265 static INLINE void
266 nv50_release_user_vbufs(struct nv50_context *nv50)
267 {
268 uint32_t vbo_user = nv50->vbo_user;
269
270 while (vbo_user) {
271 int i = ffs(vbo_user) - 1;
272 vbo_user &= ~(1 << i);
273
274 nouveau_buffer_release_gpu_storage(nv04_resource(nv50->vtxbuf[i].buffer));
275 }
276 }
277
278 void
279 nv50_vertex_arrays_validate(struct nv50_context *nv50)
280 {
281 struct nouveau_channel *chan = nv50->screen->base.channel;
282 struct nv50_vertex_stateobj *vertex = nv50->vertex;
283 struct pipe_vertex_buffer *vb;
284 struct nv50_vertex_element *ve;
285 unsigned i;
286
287 if (unlikely(vertex->need_conversion)) {
288 nv50->vbo_fifo = ~0;
289 nv50->vbo_user = 0;
290 } else {
291 nv50_prevalidate_vbufs(nv50);
292 }
293
294 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_ATTRIB(0)), vertex->num_elements);
295 for (i = 0; i < vertex->num_elements; ++i) {
296 ve = &vertex->element[i];
297 vb = &nv50->vtxbuf[ve->pipe.vertex_buffer_index];
298
299 if (likely(vb->stride) || nv50->vbo_fifo) {
300 OUT_RING(chan, ve->state);
301 } else {
302 OUT_RING(chan, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
303 nv50->vbo_fifo &= ~(1 << i);
304 }
305 }
306
307 for (i = 0; i < vertex->num_elements; ++i) {
308 struct nv04_resource *res;
309 unsigned size, offset;
310
311 ve = &vertex->element[i];
312 vb = &nv50->vtxbuf[ve->pipe.vertex_buffer_index];
313
314 if (unlikely(ve->pipe.instance_divisor)) {
315 if (!(nv50->state.instance_elts & (1 << i))) {
316 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
317 OUT_RING (chan, 1);
318 }
319 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
320 OUT_RING (chan, ve->pipe.instance_divisor);
321 } else
322 if (unlikely(nv50->state.instance_elts & (1 << i))) {
323 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
324 OUT_RING (chan, 0);
325 }
326
327 res = nv04_resource(vb->buffer);
328
329 if (nv50->vbo_fifo || unlikely(vb->stride == 0)) {
330 if (!nv50->vbo_fifo)
331 nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
332 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
333 OUT_RING (chan, 0);
334 continue;
335 }
336
337 size = vb->buffer->width0;
338 offset = ve->pipe.src_offset + vb->buffer_offset;
339
340 MARK_RING (chan, 8, 4);
341 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
342 OUT_RING (chan, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
343 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
344 OUT_RESRCh(chan, res, size - 1, NOUVEAU_BO_RD);
345 OUT_RESRCl(chan, res, size - 1, NOUVEAU_BO_RD);
346 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
347 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
348 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
349 }
350 for (; i < nv50->state.num_vtxelts; ++i) {
351 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_ATTRIB(i)), 1);
352 OUT_RING (chan, NV50_3D_VERTEX_ATTRIB_INACTIVE);
353 if (unlikely(nv50->state.instance_elts & (1 << i))) {
354 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
355 OUT_RING (chan, 0);
356 }
357 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
358 OUT_RING (chan, 0);
359 }
360
361 nv50->state.num_vtxelts = vertex->num_elements;
362 nv50->state.instance_elts = vertex->instance_elts;
363 }
364
365 #define NV50_PRIM_GL_CASE(n) \
366 case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
367
368 static INLINE unsigned
369 nv50_prim_gl(unsigned prim)
370 {
371 switch (prim) {
372 NV50_PRIM_GL_CASE(POINTS);
373 NV50_PRIM_GL_CASE(LINES);
374 NV50_PRIM_GL_CASE(LINE_LOOP);
375 NV50_PRIM_GL_CASE(LINE_STRIP);
376 NV50_PRIM_GL_CASE(TRIANGLES);
377 NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
378 NV50_PRIM_GL_CASE(TRIANGLE_FAN);
379 NV50_PRIM_GL_CASE(QUADS);
380 NV50_PRIM_GL_CASE(QUAD_STRIP);
381 NV50_PRIM_GL_CASE(POLYGON);
382 NV50_PRIM_GL_CASE(LINES_ADJACENCY);
383 NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
384 NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
385 NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
386 default:
387 return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
388 break;
389 }
390 }
391
392 static void
393 nv50_draw_vbo_flush_notify(struct nouveau_channel *chan)
394 {
395 struct nv50_screen *screen = chan->user_private;
396
397 nouveau_fence_update(&screen->base, TRUE);
398
399 nv50_bufctx_emit_relocs(screen->cur_ctx);
400 }
401
402 static void
403 nv50_draw_arrays(struct nv50_context *nv50,
404 unsigned mode, unsigned start, unsigned count,
405 unsigned instance_count)
406 {
407 struct nouveau_channel *chan = nv50->screen->base.channel;
408 unsigned prim;
409
410 if (nv50->state.index_bias) {
411 BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
412 OUT_RING (chan, 0);
413 nv50->state.index_bias = 0;
414 }
415
416 prim = nv50_prim_gl(mode);
417
418 while (instance_count--) {
419 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
420 OUT_RING (chan, prim);
421 BEGIN_RING(chan, RING_3D(VERTEX_BUFFER_FIRST), 2);
422 OUT_RING (chan, start);
423 OUT_RING (chan, count);
424 BEGIN_RING(chan, RING_3D(VERTEX_END_GL), 1);
425 OUT_RING (chan, 0);
426
427 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
428 }
429 }
430
431 static void
432 nv50_draw_elements_inline_u08(struct nouveau_channel *chan, uint8_t *map,
433 unsigned start, unsigned count)
434 {
435 map += start;
436
437 if (count & 3) {
438 unsigned i;
439 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), count & 3);
440 for (i = 0; i < (count & 3); ++i)
441 OUT_RING(chan, *map++);
442 count &= ~3;
443 }
444 while (count) {
445 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
446
447 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U8), nr);
448 for (i = 0; i < nr; ++i) {
449 OUT_RING(chan,
450 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
451 map += 4;
452 }
453 count -= nr * 4;
454 }
455 }
456
457 static void
458 nv50_draw_elements_inline_u16(struct nouveau_channel *chan, uint16_t *map,
459 unsigned start, unsigned count)
460 {
461 map += start;
462
463 if (count & 1) {
464 count &= ~1;
465 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
466 OUT_RING (chan, *map++);
467 }
468 while (count) {
469 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
470
471 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
472 for (i = 0; i < nr; ++i) {
473 OUT_RING(chan, (map[1] << 16) | map[0]);
474 map += 2;
475 }
476 count -= nr * 2;
477 }
478 }
479
480 static void
481 nv50_draw_elements_inline_u32(struct nouveau_channel *chan, uint32_t *map,
482 unsigned start, unsigned count)
483 {
484 map += start;
485
486 while (count) {
487 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
488
489 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), nr);
490 OUT_RINGp (chan, map, nr);
491
492 map += nr;
493 count -= nr;
494 }
495 }
496
497 static void
498 nv50_draw_elements_inline_u32_short(struct nouveau_channel *chan, uint32_t *map,
499 unsigned start, unsigned count)
500 {
501 map += start;
502
503 if (count & 1) {
504 count--;
505 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
506 OUT_RING (chan, *map++);
507 }
508 while (count) {
509 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
510
511 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
512 for (i = 0; i < nr; ++i) {
513 OUT_RING(chan, (map[1] << 16) | map[0]);
514 map += 2;
515 }
516 count -= nr * 2;
517 }
518 }
519
520 static void
521 nv50_draw_elements(struct nv50_context *nv50, boolean shorten,
522 unsigned mode, unsigned start, unsigned count,
523 unsigned instance_count, int32_t index_bias)
524 {
525 struct nouveau_channel *chan = nv50->screen->base.channel;
526 void *data;
527 unsigned prim;
528 const unsigned index_size = nv50->idxbuf.index_size;
529
530 prim = nv50_prim_gl(mode);
531
532 if (index_bias != nv50->state.index_bias) {
533 BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
534 OUT_RING (chan, index_bias);
535 nv50->state.index_bias = index_bias;
536 }
537
538 if (nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer)) {
539 struct nv04_resource *res = nv04_resource(nv50->idxbuf.buffer);
540
541 start += nv50->idxbuf.offset >> (index_size >> 1);
542
543 while (instance_count--) {
544 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
545 OUT_RING (chan, mode);
546
547 switch (index_size) {
548 case 4:
549 {
550 WAIT_RING (chan, 2);
551 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32) | 0x30000, 0);
552 OUT_RING (chan, count);
553 nouveau_pushbuf_submit(chan, res->bo, res->offset + start * 4,
554 count * 4);
555 }
556 break;
557 case 2:
558 {
559 unsigned pb_start = (start & ~1);
560 unsigned pb_words = (((start + count + 1) & ~1) - pb_start) >> 1;
561
562 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U16_SETUP), 1);
563 OUT_RING (chan, (start << 31) | count);
564 WAIT_RING (chan, 2);
565 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U16) | 0x30000, 0);
566 OUT_RING (chan, pb_words);
567 nouveau_pushbuf_submit(chan, res->bo, res->offset + pb_start * 2,
568 pb_words * 4);
569 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U16_SETUP), 1);
570 OUT_RING (chan, 0);
571 break;
572 }
573 case 1:
574 {
575 unsigned pb_start = (start & ~3);
576 unsigned pb_words = (((start + count + 3) & ~3) - pb_start) >> 1;
577
578 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U8_SETUP), 1);
579 OUT_RING (chan, (start << 30) | count);
580 WAIT_RING (chan, 2);
581 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U8) | 0x30000, 0);
582 OUT_RING (chan, pb_words);
583 nouveau_pushbuf_submit(chan, res->bo, res->offset + pb_start,
584 pb_words * 4);
585 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U8_SETUP), 1);
586 OUT_RING (chan, 0);
587 break;
588 }
589 default:
590 assert(0);
591 return;
592 }
593 BEGIN_RING(chan, RING_3D(VERTEX_END_GL), 1);
594 OUT_RING (chan, 0);
595
596 nv50_resource_fence(res, NOUVEAU_BO_RD);
597
598 mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
599 }
600 } else {
601 data = nouveau_resource_map_offset(&nv50->base,
602 nv04_resource(nv50->idxbuf.buffer),
603 nv50->idxbuf.offset, NOUVEAU_BO_RD);
604 if (!data)
605 return;
606
607 while (instance_count--) {
608 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
609 OUT_RING (chan, prim);
610 switch (index_size) {
611 case 1:
612 nv50_draw_elements_inline_u08(chan, data, start, count);
613 break;
614 case 2:
615 nv50_draw_elements_inline_u16(chan, data, start, count);
616 break;
617 case 4:
618 if (shorten)
619 nv50_draw_elements_inline_u32_short(chan, data, start, count);
620 else
621 nv50_draw_elements_inline_u32(chan, data, start, count);
622 break;
623 default:
624 assert(0);
625 return;
626 }
627 BEGIN_RING(chan, RING_3D(VERTEX_END_GL), 1);
628 OUT_RING (chan, 0);
629
630 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
631 }
632 }
633 }
634
635 void
636 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
637 {
638 struct nv50_context *nv50 = nv50_context(pipe);
639 struct nouveau_channel *chan = nv50->screen->base.channel;
640
641 /* For picking only a few vertices from a large user buffer, push is better,
642 * if index count is larger and we expect repeated vertices, suggest upload.
643 */
644 nv50->vbo_push_hint = /* the 64 is heuristic */
645 !(info->indexed &&
646 ((info->max_index - info->min_index + 64) < info->count));
647
648 nv50->vbo_min_index = info->min_index;
649 nv50->vbo_max_index = info->max_index;
650
651 if (nv50->vbo_push_hint != !!nv50->vbo_fifo)
652 nv50->dirty |= NV50_NEW_ARRAYS;
653
654 if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_VERTEX | NV50_NEW_ARRAYS)))
655 nv50_update_user_vbufs(nv50);
656
657 nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
658
659 chan->flush_notify = nv50_draw_vbo_flush_notify;
660
661 if (nv50->vbo_fifo) {
662 nv50_push_vbo(nv50, info);
663 chan->flush_notify = nv50_default_flush_notify;
664 return;
665 }
666
667 if (nv50->state.instance_base != info->start_instance) {
668 nv50->state.instance_base = info->start_instance;
669 /* NOTE: this does not affect the shader input, should it ? */
670 BEGIN_RING(chan, RING_3D(VB_INSTANCE_BASE), 1);
671 OUT_RING (chan, info->start_instance);
672 }
673
674 if (nv50->base.vbo_dirty) {
675 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 1);
676 OUT_RING (chan, 0);
677 nv50->base.vbo_dirty = FALSE;
678 }
679
680 if (!info->indexed) {
681 nv50_draw_arrays(nv50,
682 info->mode, info->start, info->count,
683 info->instance_count);
684 } else {
685 boolean shorten = info->max_index <= 65535;
686
687 assert(nv50->idxbuf.buffer);
688
689 if (info->primitive_restart != nv50->state.prim_restart) {
690 if (info->primitive_restart) {
691 BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 2);
692 OUT_RING (chan, 1);
693 OUT_RING (chan, info->restart_index);
694
695 if (info->restart_index > 65535)
696 shorten = FALSE;
697 } else {
698 BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 1);
699 OUT_RING (chan, 0);
700 }
701 nv50->state.prim_restart = info->primitive_restart;
702 } else
703 if (info->primitive_restart) {
704 BEGIN_RING(chan, RING_3D(PRIM_RESTART_INDEX), 1);
705 OUT_RING (chan, info->restart_index);
706
707 if (info->restart_index > 65535)
708 shorten = FALSE;
709 }
710
711 nv50_draw_elements(nv50, shorten,
712 info->mode, info->start, info->count,
713 info->instance_count, info->index_bias);
714 }
715 chan->flush_notify = nv50_default_flush_notify;
716
717 nv50_release_user_vbufs(nv50);
718 }