src/gallium/drivers/nv50/nv50_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "pipe/p_context.h"
  24 #include "pipe/p_state.h"
  25 #include "util/u_inlines.h"
  26 #include "util/u_format.h"
  27 #include "translate/translate.h"
  28
  29 #include "nv50_context.h"
  30 #include "nv50_resource.h"
  31
  32 #include "nv50_3d.xml.h"
  33
  34 void
  35 nv50_vertex_state_delete(struct pipe_context *pipe,
  36                          void *hwcso)
  37 {
  38    struct nv50_vertex_stateobj *so = hwcso;
  39
  40    if (so->translate)
  41       so->translate->release(so->translate);
  42    FREE(hwcso);
  43 }
  44
  45 void *
  46 nv50_vertex_state_create(struct pipe_context *pipe,
  47                          unsigned num_elements,
  48                          const struct pipe_vertex_element *elements)
  49 {
  50     struct nv50_vertex_stateobj *so;
  51     struct translate_key transkey;
  52     unsigned i;
  53
  54     so = MALLOC(sizeof(*so) +
  55                 num_elements * sizeof(struct nv50_vertex_element));
  56     if (!so)
  57         return NULL;
  58     so->num_elements = num_elements;
  59     so->instance_elts = 0;
  60     so->instance_bufs = 0;
  61     so->need_conversion = FALSE;
  62
  63     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  64
  65     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  66        so->min_instance_div[i] = 0xffffffff;
  67
  68     transkey.nr_elements = 0;
  69     transkey.output_stride = 0;
  70
  71     for (i = 0; i < num_elements; ++i) {
  72         const struct pipe_vertex_element *ve = &elements[i];
  73         const unsigned vbi = ve->vertex_buffer_index;
  74         unsigned size;
  75         enum pipe_format fmt = ve->src_format;
  76
  77         so->element[i].pipe = elements[i];
  78         so->element[i].state = nv50_format_table[fmt].vtx;
  79
  80         if (!so->element[i].state) {
  81             switch (util_format_get_nr_components(fmt)) {
  82             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  83             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  84             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  85             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  86             default:
  87                 assert(0);
  88                 FREE(so);
  89                 return NULL;
  90             }
  91             so->element[i].state = nv50_format_table[fmt].vtx;
  92             so->need_conversion = TRUE;
  93         }
  94         so->element[i].state |= i;
  95
  96         size = util_format_get_blocksize(fmt);
  97         if (so->vb_access_size[vbi] < (ve->src_offset + size))
  98            so->vb_access_size[vbi] = ve->src_offset + size;
  99
 100         if (1) {
 101             unsigned j = transkey.nr_elements++;
 102
 103             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
 104             transkey.element[j].input_format = ve->src_format;
 105             transkey.element[j].input_buffer = vbi;
 106             transkey.element[j].input_offset = ve->src_offset;
 107             transkey.element[j].instance_divisor = ve->instance_divisor;
 108
 109             transkey.element[j].output_format = fmt;
 110             transkey.element[j].output_offset = transkey.output_stride;
 111             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
 112
 113             if (unlikely(ve->instance_divisor)) {
 114                so->instance_elts |= 1 << i;
 115                so->instance_bufs |= 1 << vbi;
 116                if (ve->instance_divisor < so->min_instance_div[vbi])
 117                   so->min_instance_div[vbi] = ve->instance_divisor;
 118             }
 119         }
 120     }
 121
 122     so->translate = translate_create(&transkey);
 123     so->vertex_size = transkey.output_stride / 4;
 124     so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
 125        MAX2(so->vertex_size, 1);
 126
 127     return so;
 128 }
 129
 130 #define NV50_3D_VERTEX_ATTRIB_INACTIVE              \
 131    NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT |         \
 132    NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
 133    NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
 134
 135 static void
 136 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
 137                   struct pipe_vertex_element *ve, unsigned attr)
 138 {
 139    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 140    const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset;
 141    float v[4];
 142    const unsigned nc = util_format_get_nr_components(ve->src_format);
 143
 144    assert(vb->user_buffer);
 145
 146    util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
 147
 148    switch (nc) {
 149    case 4:
 150       BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
 151       PUSH_DATAf(push, v[0]);
 152       PUSH_DATAf(push, v[1]);
 153       PUSH_DATAf(push, v[2]);
 154       PUSH_DATAf(push, v[3]);
 155       break;
 156    case 3:
 157       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
 158       PUSH_DATAf(push, v[0]);
 159       PUSH_DATAf(push, v[1]);
 160       PUSH_DATAf(push, v[2]);
 161       break;
 162    case 2:
 163       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
 164       PUSH_DATAf(push, v[0]);
 165       PUSH_DATAf(push, v[1]);
 166       break;
 167    case 1:
 168       if (attr == nv50->vertprog->vp.edgeflag) {
 169          BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 170          PUSH_DATA (push, v[0] ? 1 : 0);
 171       }
 172       BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
 173       PUSH_DATAf(push, v[0]);
 174       break;
 175    default:
 176       assert(0);
 177       break;
 178    }
 179 }
 180
 181 static INLINE void
 182 nv50_user_vbuf_range(struct nv50_context *nv50, int vbi,
 183                      uint32_t *base, uint32_t *size)
 184 {
 185    if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
 186       /* TODO: use min and max instance divisor to get a proper range */
 187       *base = 0;
 188       *size = nv50->vtxbuf[vbi].buffer->width0;
 189    } else {
 190       /* NOTE: if there are user buffers, we *must* have index bounds */
 191       assert(nv50->vb_elt_limit != ~0);
 192       *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
 193       *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
 194          nv50->vertex->vb_access_size[vbi];
 195    }
 196 }
 197
 198 static void
 199 nv50_upload_user_buffers(struct nv50_context *nv50,
 200                          uint64_t addrs[], uint32_t limits[])
 201 {
 202    unsigned b;
 203
 204    for (b = 0; b < nv50->num_vtxbufs; ++b) {
 205       struct nouveau_bo *bo;
 206       const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
 207       uint32_t base, size;
 208
 209       if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
 210          continue;
 211       nv50_user_vbuf_range(nv50, b, &base, &size);
 212
 213       limits[b] = base + size - 1;
 214       addrs[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, base, size,
 215                                       &bo);
 216       if (addrs[b])
 217          BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, NOUVEAU_BO_GART |
 218                       NOUVEAU_BO_RD, bo);
 219    }
 220    nv50->base.vbo_dirty = TRUE;
 221 }
 222
 223 static void
 224 nv50_update_user_vbufs(struct nv50_context *nv50)
 225 {
 226    uint64_t address[PIPE_MAX_ATTRIBS];
 227    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 228    unsigned i;
 229    uint32_t written = 0;
 230
 231    for (i = 0; i < nv50->vertex->num_elements; ++i) {
 232       struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
 233       const unsigned b = ve->vertex_buffer_index;
 234       struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
 235       uint32_t base, size;
 236
 237       if (!(nv50->vbo_user & (1 << b)))
 238          continue;
 239
 240       if (!vb->stride) {
 241          nv50_emit_vtxattr(nv50, vb, ve, i);
 242          continue;
 243       }
 244       nv50_user_vbuf_range(nv50, b, &base, &size);
 245
 246       if (!(written & (1 << b))) {
 247          struct nouveau_bo *bo;
 248          const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 249          written |= 1 << b;
 250          address[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer,
 251                                            base, size, &bo);
 252          if (address[b])
 253             BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, bo_flags, bo);
 254       }
 255
 256       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 257       PUSH_DATAh(push, address[b] + base + size - 1);
 258       PUSH_DATA (push, address[b] + base + size - 1);
 259       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
 260       PUSH_DATAh(push, address[b] + ve->src_offset);
 261       PUSH_DATA (push, address[b] + ve->src_offset);
 262    }
 263    nv50->base.vbo_dirty = TRUE;
 264 }
 265
 266 static INLINE void
 267 nv50_release_user_vbufs(struct nv50_context *nv50)
 268 {
 269    if (nv50->vbo_user) {
 270       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX_TMP);
 271       nouveau_scratch_done(&nv50->base);
 272    }
 273 }
 274
 275 void
 276 nv50_vertex_arrays_validate(struct nv50_context *nv50)
 277 {
 278    uint64_t addrs[PIPE_MAX_ATTRIBS];
 279    uint32_t limits[PIPE_MAX_ATTRIBS];
 280    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 281    struct nv50_vertex_stateobj *vertex = nv50->vertex;
 282    struct pipe_vertex_buffer *vb;
 283    struct nv50_vertex_element *ve;
 284    uint32_t mask;
 285    uint32_t refd = 0;
 286    unsigned i;
 287    const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
 288
 289    if (unlikely(vertex->need_conversion))
 290       nv50->vbo_fifo = ~0;
 291    else
 292    if (nv50->vbo_user & ~nv50->vbo_constant)
 293       nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
 294    else
 295       nv50->vbo_fifo = 0;
 296
 297    if (!nv50->vbo_fifo) {
 298       /* if vertex buffer was written by GPU - flush VBO cache */
 299       for (i = 0; i < nv50->num_vtxbufs; ++i) {
 300          struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer);
 301          if (buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 302             buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 303             nv50->base.vbo_dirty = TRUE;
 304             break;
 305          }
 306       }
 307    }
 308
 309    /* update vertex format state */
 310    BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
 311    if (nv50->vbo_fifo) {
 312       nv50->state.num_vtxelts = vertex->num_elements;
 313       for (i = 0; i < vertex->num_elements; ++i)
 314          PUSH_DATA (push, vertex->element[i].state);
 315       for (; i < n; ++i)
 316          PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 317       for (i = 0; i < n; ++i) {
 318          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 319          PUSH_DATA (push, 0);
 320       }
 321       return;
 322    }
 323    for (i = 0; i < vertex->num_elements; ++i) {
 324       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 325       ve = &vertex->element[i];
 326       vb = &nv50->vtxbuf[b];
 327
 328       if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
 329          PUSH_DATA(push, ve->state);
 330       else
 331          PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
 332    }
 333    for (; i < n; ++i)
 334       PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 335
 336    /* update per-instance enables */
 337    mask = vertex->instance_elts ^ nv50->state.instance_elts;
 338    while (mask) {
 339       const int i = ffs(mask) - 1;
 340       mask &= ~(1 << i);
 341       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 342       PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
 343    }
 344    nv50->state.instance_elts = vertex->instance_elts;
 345
 346    if (nv50->vbo_user & ~nv50->vbo_constant)
 347       nv50_upload_user_buffers(nv50, addrs, limits);
 348
 349    /* update buffers and set constant attributes */
 350    for (i = 0; i < vertex->num_elements; ++i) {
 351       uint64_t address, limit;
 352       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 353       ve = &vertex->element[i];
 354       vb = &nv50->vtxbuf[b];
 355
 356       if (unlikely(nv50->vbo_constant & (1 << b))) {
 357          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 358          PUSH_DATA (push, 0);
 359          nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
 360          continue;
 361       } else
 362       if (nv50->vbo_user & (1 << b)) {
 363          address = addrs[b] + ve->pipe.src_offset;
 364          limit = addrs[b] + limits[b];
 365       } else {
 366          struct nv04_resource *buf = nv04_resource(vb->buffer);
 367          if (!(refd & (1 << b))) {
 368             refd |= 1 << b;
 369             BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
 370          }
 371          address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
 372          limit = buf->address + buf->base.width0 - 1;
 373       }
 374
 375       if (unlikely(ve->pipe.instance_divisor)) {
 376          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
 377          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 378          PUSH_DATAh(push, address);
 379          PUSH_DATA (push, address);
 380          PUSH_DATA (push, ve->pipe.instance_divisor);
 381       } else {
 382          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
 383          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 384          PUSH_DATAh(push, address);
 385          PUSH_DATA (push, address);
 386       }
 387       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 388       PUSH_DATAh(push, limit);
 389       PUSH_DATA (push, limit);
 390    }
 391    for (; i < nv50->state.num_vtxelts; ++i) {
 392       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 393       PUSH_DATA (push, 0);
 394    }
 395    nv50->state.num_vtxelts = vertex->num_elements;
 396 }
 397
 398 #define NV50_PRIM_GL_CASE(n) \
 399    case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 400
 401 static INLINE unsigned
 402 nv50_prim_gl(unsigned prim)
 403 {
 404    switch (prim) {
 405    NV50_PRIM_GL_CASE(POINTS);
 406    NV50_PRIM_GL_CASE(LINES);
 407    NV50_PRIM_GL_CASE(LINE_LOOP);
 408    NV50_PRIM_GL_CASE(LINE_STRIP);
 409    NV50_PRIM_GL_CASE(TRIANGLES);
 410    NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
 411    NV50_PRIM_GL_CASE(TRIANGLE_FAN);
 412    NV50_PRIM_GL_CASE(QUADS);
 413    NV50_PRIM_GL_CASE(QUAD_STRIP);
 414    NV50_PRIM_GL_CASE(POLYGON);
 415    NV50_PRIM_GL_CASE(LINES_ADJACENCY);
 416    NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 417    NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 418    NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 419    default:
 420       return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 421       break;
 422    }
 423 }
 424
 425 /* For pre-nva0 transform feedback. */
 426 static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
 427 {
 428    [PIPE_PRIM_POINTS] = 1,
 429    [PIPE_PRIM_LINES] = 2,
 430    [PIPE_PRIM_LINE_LOOP] = 2,
 431    [PIPE_PRIM_LINE_STRIP] = 2,
 432    [PIPE_PRIM_TRIANGLES] = 3,
 433    [PIPE_PRIM_TRIANGLE_STRIP] = 3,
 434    [PIPE_PRIM_TRIANGLE_FAN] = 3,
 435    [PIPE_PRIM_QUADS] = 3,
 436    [PIPE_PRIM_QUAD_STRIP] = 3,
 437    [PIPE_PRIM_POLYGON] = 3,
 438    [PIPE_PRIM_LINES_ADJACENCY] = 2,
 439    [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
 440    [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
 441    [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
 442 };
 443
 444 static void
 445 nv50_draw_arrays(struct nv50_context *nv50,
 446                  unsigned mode, unsigned start, unsigned count,
 447                  unsigned instance_count)
 448 {
 449    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 450    unsigned prim;
 451
 452    if (nv50->state.index_bias) {
 453       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 454       PUSH_DATA (push, 0);
 455       nv50->state.index_bias = 0;
 456    }
 457
 458    prim = nv50_prim_gl(mode);
 459
 460    while (instance_count--) {
 461       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 462       PUSH_DATA (push, prim);
 463       BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
 464       PUSH_DATA (push, start);
 465       PUSH_DATA (push, count);
 466       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 467       PUSH_DATA (push, 0);
 468
 469       prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 470    }
 471 }
 472
 473 static void
 474 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
 475                               unsigned start, unsigned count)
 476 {
 477    map += start;
 478
 479    if (count & 3) {
 480       unsigned i;
 481       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
 482       for (i = 0; i < (count & 3); ++i)
 483          PUSH_DATA(push, *map++);
 484       count &= ~3;
 485    }
 486    while (count) {
 487       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 488
 489       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
 490       for (i = 0; i < nr; ++i) {
 491          PUSH_DATA(push,
 492                    (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 493          map += 4;
 494       }
 495       count -= nr * 4;
 496    }
 497 }
 498
 499 static void
 500 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
 501                               unsigned start, unsigned count)
 502 {
 503    map += start;
 504
 505    if (count & 1) {
 506       count &= ~1;
 507       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 508       PUSH_DATA (push, *map++);
 509    }
 510    while (count) {
 511       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 512
 513       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 514       for (i = 0; i < nr; ++i) {
 515          PUSH_DATA(push, (map[1] << 16) | map[0]);
 516          map += 2;
 517       }
 518       count -= nr * 2;
 519    }
 520 }
 521
 522 static void
 523 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
 524                               unsigned start, unsigned count)
 525 {
 526    map += start;
 527
 528    while (count) {
 529       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 530
 531       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
 532       PUSH_DATAp(push, map, nr);
 533
 534       map += nr;
 535       count -= nr;
 536    }
 537 }
 538
 539 static void
 540 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
 541                                     const uint32_t *map,
 542                                     unsigned start, unsigned count)
 543 {
 544    map += start;
 545
 546    if (count & 1) {
 547       count--;
 548       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 549       PUSH_DATA (push, *map++);
 550    }
 551    while (count) {
 552       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 553
 554       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 555       for (i = 0; i < nr; ++i) {
 556          PUSH_DATA(push, (map[1] << 16) | map[0]);
 557          map += 2;
 558       }
 559       count -= nr * 2;
 560    }
 561 }
 562
 563 static void
 564 nv50_draw_elements(struct nv50_context *nv50, boolean shorten,
 565                    unsigned mode, unsigned start, unsigned count,
 566                    unsigned instance_count, int32_t index_bias)
 567 {
 568    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 569    unsigned prim;
 570    const unsigned index_size = nv50->idxbuf.index_size;
 571
 572    prim = nv50_prim_gl(mode);
 573
 574    if (index_bias != nv50->state.index_bias) {
 575       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 576       PUSH_DATA (push, index_bias);
 577       nv50->state.index_bias = index_bias;
 578    }
 579
 580    if (nv50->idxbuf.buffer) {
 581       struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
 582       unsigned pb_start;
 583       unsigned pb_bytes;
 584       const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3;
 585
 586       start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1);
 587
 588       assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
 589
 590       while (instance_count--) {
 591          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 592          PUSH_DATA (push, prim);
 593
 594          nouveau_pushbuf_space(push, 8, 0, 1);
 595
 596          switch (index_size) {
 597          case 4:
 598             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
 599             nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
 600             break;
 601          case 2:
 602             pb_start = (start & ~1) * 2;
 603             pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
 604
 605             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 606             PUSH_DATA (push, (start << 31) | count);
 607             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
 608             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 609             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 610             PUSH_DATA (push, 0);
 611             break;
 612          default:
 613             assert(index_size == 1);
 614             pb_start = start & ~3;
 615             pb_bytes = ((start + count + 3) & ~3) - pb_start;
 616
 617             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 618             PUSH_DATA (push, (start << 30) | count);
 619             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
 620             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 621             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 622             PUSH_DATA (push, 0);
 623             break;
 624          }
 625          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 626          PUSH_DATA (push, 0);
 627
 628          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 629       }
 630    } else {
 631       const void *data = nv50->idxbuf.user_buffer;
 632
 633       while (instance_count--) {
 634          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 635          PUSH_DATA (push, prim);
 636          switch (index_size) {
 637          case 1:
 638             nv50_draw_elements_inline_u08(push, data, start, count);
 639             break;
 640          case 2:
 641             nv50_draw_elements_inline_u16(push, data, start, count);
 642             break;
 643          case 4:
 644             if (shorten)
 645                nv50_draw_elements_inline_u32_short(push, data, start, count);
 646             else
 647                nv50_draw_elements_inline_u32(push, data, start, count);
 648             break;
 649          default:
 650             assert(0);
 651             return;
 652          }
 653          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 654          PUSH_DATA (push, 0);
 655
 656          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 657       }
 658    }
 659 }
 660
 661 static void
 662 nva0_draw_stream_output(struct nv50_context *nv50,
 663                         const struct pipe_draw_info *info)
 664 {
 665    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 666    struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
 667    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
 668    unsigned num_instances = info->instance_count;
 669    unsigned mode = nv50_prim_gl(info->mode);
 670
 671    if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
 672       /* A proper implementation without waiting doesn't seem possible,
 673        * so don't bother.
 674        */
 675       NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
 676       return;
 677    }
 678
 679    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 680       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 681       PUSH_SPACE(push, 4);
 682       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
 683       PUSH_DATA (push, 0);
 684       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 685       PUSH_DATA (push, 0);
 686    }
 687
 688    assert(num_instances);
 689    do {
 690       PUSH_SPACE(push, 8);
 691       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 692       PUSH_DATA (push, mode);
 693       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
 694       PUSH_DATA (push, 0);
 695       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
 696       PUSH_DATA (push, 0);
 697       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BYTES), 1);
 698       nv50_query_pushbuf_submit(push, so->pq, 0x4);
 699       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 700       PUSH_DATA (push, 0);
 701
 702       mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 703    } while (--num_instances);
 704 }
 705
 706 static void
 707 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
 708 {
 709    struct nv50_screen *screen = chan->user_priv;
 710
 711    nouveau_fence_update(&screen->base, TRUE);
 712
 713    nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, TRUE);
 714 }
 715
 716 void
 717 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 718 {
 719    struct nv50_context *nv50 = nv50_context(pipe);
 720    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 721
 722    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
 723    nv50->vb_elt_first = info->min_index + info->index_bias;
 724    nv50->vb_elt_limit = info->max_index - info->min_index;
 725    nv50->instance_off = info->start_instance;
 726    nv50->instance_max = info->instance_count - 1;
 727
 728    /* For picking only a few vertices from a large user buffer, push is better,
 729     * if index count is larger and we expect repeated vertices, suggest upload.
 730     */
 731    nv50->vbo_push_hint = /* the 64 is heuristic */
 732       !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count));
 733
 734    if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_ARRAYS | NV50_NEW_VERTEX))) {
 735       if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
 736          nv50->dirty |= NV50_NEW_ARRAYS;
 737       else
 738       if (!nv50->vbo_fifo)
 739          nv50_update_user_vbufs(nv50);
 740    }
 741
 742    if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
 743       nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
 744
 745    nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
 746
 747    push->kick_notify = nv50_draw_vbo_kick_notify;
 748
 749    if (nv50->vbo_fifo) {
 750       nv50_push_vbo(nv50, info);
 751       push->kick_notify = nv50_default_kick_notify;
 752       nouveau_pushbuf_bufctx(push, NULL);
 753       return;
 754    }
 755
 756    if (nv50->state.instance_base != info->start_instance) {
 757       nv50->state.instance_base = info->start_instance;
 758       /* NOTE: this does not affect the shader input, should it ? */
 759       BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
 760       PUSH_DATA (push, info->start_instance);
 761    }
 762
 763    if (nv50->base.vbo_dirty) {
 764       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 765       PUSH_DATA (push, 0);
 766       nv50->base.vbo_dirty = FALSE;
 767    }
 768
 769    if (info->indexed) {
 770       boolean shorten = info->max_index <= 65535;
 771
 772       if (info->primitive_restart != nv50->state.prim_restart) {
 773          if (info->primitive_restart) {
 774             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
 775             PUSH_DATA (push, 1);
 776             PUSH_DATA (push, info->restart_index);
 777
 778             if (info->restart_index > 65535)
 779                shorten = FALSE;
 780          } else {
 781             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
 782             PUSH_DATA (push, 0);
 783          }
 784          nv50->state.prim_restart = info->primitive_restart;
 785       } else
 786       if (info->primitive_restart) {
 787          BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
 788          PUSH_DATA (push, info->restart_index);
 789
 790          if (info->restart_index > 65535)
 791             shorten = FALSE;
 792       }
 793
 794       nv50_draw_elements(nv50, shorten,
 795                          info->mode, info->start, info->count,
 796                          info->instance_count, info->index_bias);
 797    } else
 798    if (unlikely(info->count_from_stream_output)) {
 799       nva0_draw_stream_output(nv50, info);
 800    } else {
 801       nv50_draw_arrays(nv50,
 802                        info->mode, info->start, info->count,
 803                        info->instance_count);
 804    }
 805    push->kick_notify = nv50_default_kick_notify;
 806
 807    nv50_release_user_vbufs(nv50);
 808
 809    nouveau_pushbuf_bufctx(push, NULL);
 810 }