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nv50: remove horrific abuse of nouveau_channel.flush_notify
[mesa.git] / src / gallium / drivers / nv50 / nv50_vbo.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
27
28 #include "nv50_context.h"
29
30 static boolean
31 nv50_push_elements_u08(struct nv50_context *, uint8_t *, unsigned);
32
33 static boolean
34 nv50_push_elements_u16(struct nv50_context *, uint16_t *, unsigned);
35
36 static boolean
37 nv50_push_elements_u32(struct nv50_context *, uint32_t *, unsigned);
38
39 static boolean
40 nv50_push_arrays(struct nv50_context *, unsigned, unsigned);
41
42 #define NV50_USING_LOATHED_EDGEFLAG(ctx) ((ctx)->vertprog->cfg.edgeflag_in < 16)
43
44 static INLINE unsigned
45 nv50_prim(unsigned mode)
46 {
47 switch (mode) {
48 case PIPE_PRIM_POINTS: return NV50TCL_VERTEX_BEGIN_POINTS;
49 case PIPE_PRIM_LINES: return NV50TCL_VERTEX_BEGIN_LINES;
50 case PIPE_PRIM_LINE_LOOP: return NV50TCL_VERTEX_BEGIN_LINE_LOOP;
51 case PIPE_PRIM_LINE_STRIP: return NV50TCL_VERTEX_BEGIN_LINE_STRIP;
52 case PIPE_PRIM_TRIANGLES: return NV50TCL_VERTEX_BEGIN_TRIANGLES;
53 case PIPE_PRIM_TRIANGLE_STRIP:
54 return NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP;
55 case PIPE_PRIM_TRIANGLE_FAN: return NV50TCL_VERTEX_BEGIN_TRIANGLE_FAN;
56 case PIPE_PRIM_QUADS: return NV50TCL_VERTEX_BEGIN_QUADS;
57 case PIPE_PRIM_QUAD_STRIP: return NV50TCL_VERTEX_BEGIN_QUAD_STRIP;
58 case PIPE_PRIM_POLYGON: return NV50TCL_VERTEX_BEGIN_POLYGON;
59 case PIPE_PRIM_LINES_ADJACENCY:
60 return NV50TCL_VERTEX_BEGIN_LINES_ADJACENCY;
61 case PIPE_PRIM_LINE_STRIP_ADJACENCY:
62 return NV50TCL_VERTEX_BEGIN_LINE_STRIP_ADJACENCY;
63 case PIPE_PRIM_TRIANGLES_ADJACENCY:
64 return NV50TCL_VERTEX_BEGIN_TRIANGLES_ADJACENCY;
65 case PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY:
66 return NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP_ADJACENCY;
67 default:
68 break;
69 }
70
71 NOUVEAU_ERR("invalid primitive type %d\n", mode);
72 return NV50TCL_VERTEX_BEGIN_POINTS;
73 }
74
75 static INLINE uint32_t
76 nv50_vbo_type_to_hw(enum pipe_format format)
77 {
78 const struct util_format_description *desc;
79
80 desc = util_format_description(format);
81 assert(desc);
82
83 switch (desc->channel[0].type) {
84 case UTIL_FORMAT_TYPE_FLOAT:
85 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT;
86 case UTIL_FORMAT_TYPE_UNSIGNED:
87 if (desc->channel[0].normalized) {
88 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UNORM;
89 }
90 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_USCALED;
91 case UTIL_FORMAT_TYPE_SIGNED:
92 if (desc->channel[0].normalized) {
93 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SNORM;
94 }
95 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SSCALED;
96 /*
97 case PIPE_FORMAT_TYPE_UINT:
98 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UINT;
99 case PIPE_FORMAT_TYPE_SINT:
100 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SINT; */
101 default:
102 return 0;
103 }
104 }
105
106 static INLINE uint32_t
107 nv50_vbo_size_to_hw(unsigned size, unsigned nr_c)
108 {
109 static const uint32_t hw_values[] = {
110 0, 0, 0, 0,
111 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8,
112 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8,
113 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8,
114 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8_8,
115 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16,
116 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16,
117 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16,
118 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16_16,
119 0, 0, 0, 0,
120 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32,
121 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32,
122 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32,
123 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 };
124
125 /* we'd also have R11G11B10 and R10G10B10A2 */
126
127 assert(nr_c > 0 && nr_c <= 4);
128
129 if (size > 32)
130 return 0;
131 size >>= (3 - 2);
132
133 return hw_values[size + (nr_c - 1)];
134 }
135
136 static INLINE uint32_t
137 nv50_vbo_vtxelt_to_hw(struct pipe_vertex_element *ve)
138 {
139 uint32_t hw_type, hw_size;
140 enum pipe_format pf = ve->src_format;
141 const struct util_format_description *desc;
142 unsigned size, nr_components;
143
144 desc = util_format_description(pf);
145 assert(desc);
146
147 size = util_format_get_component_bits(pf, UTIL_FORMAT_COLORSPACE_RGB, 0);
148 nr_components = util_format_get_nr_components(pf);
149
150 hw_type = nv50_vbo_type_to_hw(pf);
151 hw_size = nv50_vbo_size_to_hw(size, nr_components);
152
153 if (!hw_type || !hw_size) {
154 NOUVEAU_ERR("unsupported vbo format: %s\n", util_format_name(pf));
155 abort();
156 return 0x24e80000;
157 }
158
159 if (desc->swizzle[0] == UTIL_FORMAT_SWIZZLE_Z) /* BGRA */
160 hw_size |= (1 << 31); /* no real swizzle bits :-( */
161
162 return (hw_type | hw_size);
163 }
164
165 /* For instanced drawing from user buffers, hitting the FIFO repeatedly
166 * with the same vertex data is probably worse than uploading all data.
167 */
168 static boolean
169 nv50_upload_vtxbuf(struct nv50_context *nv50, unsigned i)
170 {
171 struct nv50_screen *nscreen = nv50->screen;
172 struct pipe_screen *pscreen = &nscreen->base.base;
173 struct pipe_buffer *buf = nscreen->strm_vbuf[i];
174 struct pipe_vertex_buffer *vb = &nv50->vtxbuf[i];
175 uint8_t *src;
176 unsigned size = align(vb->buffer->size, 4096);
177
178 if (buf && buf->size < size)
179 pipe_buffer_reference(&nscreen->strm_vbuf[i], NULL);
180
181 if (!nscreen->strm_vbuf[i]) {
182 nscreen->strm_vbuf[i] = pipe_buffer_create(
183 pscreen, 0, PIPE_BUFFER_USAGE_VERTEX, size);
184 buf = nscreen->strm_vbuf[i];
185 }
186
187 src = pipe_buffer_map(pscreen, vb->buffer, PIPE_BUFFER_USAGE_CPU_READ);
188 if (!src)
189 return FALSE;
190 src += vb->buffer_offset;
191
192 size = (vb->max_index + 1) * vb->stride + 16; /* + 16 is for stride 0 */
193 if (vb->buffer_offset + size > vb->buffer->size)
194 size = vb->buffer->size - vb->buffer_offset;
195
196 pipe_buffer_write(pscreen, buf, vb->buffer_offset, size, src);
197 pipe_buffer_unmap(pscreen, vb->buffer);
198
199 vb->buffer = buf; /* don't pipe_reference, this is a private copy */
200 return TRUE;
201 }
202
203 static void
204 nv50_upload_user_vbufs(struct nv50_context *nv50)
205 {
206 unsigned i;
207
208 if (nv50->vbo_fifo)
209 nv50->dirty |= NV50_NEW_ARRAYS;
210 if (!(nv50->dirty & NV50_NEW_ARRAYS))
211 return;
212
213 for (i = 0; i < nv50->vtxbuf_nr; ++i) {
214 if (nv50->vtxbuf[i].buffer->usage & PIPE_BUFFER_USAGE_VERTEX)
215 continue;
216 nv50_upload_vtxbuf(nv50, i);
217 }
218 }
219
220 static void
221 nv50_set_static_vtxattr(struct nv50_context *nv50, unsigned i, void *data)
222 {
223 struct nouveau_grobj *tesla = nv50->screen->tesla;
224 struct nouveau_channel *chan = tesla->channel;
225 float v[4];
226 enum pipe_format pf = nv50->vtxelt->pipe[i].src_format;
227 unsigned nr_components = util_format_get_nr_components(pf);
228
229 util_format_read_4f(pf, v, 0, data, 0, 0, 0, 1, 1);
230
231 switch (nr_components) {
232 case 4:
233 BEGIN_RING(chan, tesla, NV50TCL_VTX_ATTR_4F_X(i), 4);
234 OUT_RINGf (chan, v[0]);
235 OUT_RINGf (chan, v[1]);
236 OUT_RINGf (chan, v[2]);
237 OUT_RINGf (chan, v[3]);
238 break;
239 case 3:
240 BEGIN_RING(chan, tesla, NV50TCL_VTX_ATTR_3F_X(i), 3);
241 OUT_RINGf (chan, v[0]);
242 OUT_RINGf (chan, v[1]);
243 OUT_RINGf (chan, v[2]);
244 break;
245 case 2:
246 BEGIN_RING(chan, tesla, NV50TCL_VTX_ATTR_2F_X(i), 2);
247 OUT_RINGf (chan, v[0]);
248 OUT_RINGf (chan, v[1]);
249 break;
250 case 1:
251 BEGIN_RING(chan, tesla, NV50TCL_VTX_ATTR_1F(i), 1);
252 OUT_RINGf (chan, v[0]);
253 break;
254 default:
255 assert(0);
256 break;
257 }
258 }
259
260 static unsigned
261 init_per_instance_arrays_immd(struct nv50_context *nv50,
262 unsigned startInstance,
263 unsigned pos[16], unsigned step[16])
264 {
265 struct nouveau_bo *bo;
266 unsigned i, b, count = 0;
267
268 for (i = 0; i < nv50->vtxelt->num_elements; ++i) {
269 if (!nv50->vtxelt->pipe[i].instance_divisor)
270 continue;
271 ++count;
272 b = nv50->vtxelt->pipe[i].vertex_buffer_index;
273
274 pos[i] = nv50->vtxelt->pipe[i].src_offset +
275 nv50->vtxbuf[b].buffer_offset +
276 startInstance * nv50->vtxbuf[b].stride;
277 step[i] = startInstance %
278 nv50->vtxelt->pipe[i].instance_divisor;
279
280 bo = nouveau_bo(nv50->vtxbuf[b].buffer);
281 if (!bo->map)
282 nouveau_bo_map(bo, NOUVEAU_BO_RD);
283
284 nv50_set_static_vtxattr(nv50, i, (uint8_t *)bo->map + pos[i]);
285 }
286
287 return count;
288 }
289
290 static unsigned
291 init_per_instance_arrays(struct nv50_context *nv50,
292 unsigned startInstance,
293 unsigned pos[16], unsigned step[16])
294 {
295 struct nouveau_grobj *tesla = nv50->screen->tesla;
296 struct nouveau_channel *chan = tesla->channel;
297 struct nouveau_bo *bo;
298 struct nouveau_stateobj *so;
299 unsigned i, b, count = 0, num_elements = nv50->vtxelt->num_elements;
300 const uint32_t rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
301
302 if (nv50->vbo_fifo)
303 return init_per_instance_arrays_immd(nv50, startInstance,
304 pos, step);
305
306 so = so_new(num_elements, num_elements * 2, num_elements * 2);
307
308 for (i = 0; i < nv50->vtxelt->num_elements; ++i) {
309 if (!nv50->vtxelt->pipe[i].instance_divisor)
310 continue;
311 ++count;
312 b = nv50->vtxelt->pipe[i].vertex_buffer_index;
313
314 pos[i] = nv50->vtxelt->pipe[i].src_offset +
315 nv50->vtxbuf[b].buffer_offset +
316 startInstance * nv50->vtxbuf[b].stride;
317
318 if (!startInstance) {
319 step[i] = 0;
320 continue;
321 }
322 step[i] = startInstance %
323 nv50->vtxelt->pipe[i].instance_divisor;
324
325 bo = nouveau_bo(nv50->vtxbuf[b].buffer);
326
327 so_method(so, tesla, NV50TCL_VERTEX_ARRAY_START_HIGH(i), 2);
328 so_reloc (so, bo, pos[i], rl | NOUVEAU_BO_HIGH, 0, 0);
329 so_reloc (so, bo, pos[i], rl | NOUVEAU_BO_LOW, 0, 0);
330 }
331
332 if (count && startInstance) {
333 so_ref (so, &nv50->state.instbuf); /* for flush notify */
334 so_emit(chan, nv50->state.instbuf);
335 }
336 so_ref (NULL, &so);
337
338 return count;
339 }
340
341 static void
342 step_per_instance_arrays_immd(struct nv50_context *nv50,
343 unsigned pos[16], unsigned step[16])
344 {
345 struct nouveau_bo *bo;
346 unsigned i, b;
347
348 for (i = 0; i < nv50->vtxelt->num_elements; ++i) {
349 if (!nv50->vtxelt->pipe[i].instance_divisor)
350 continue;
351 if (++step[i] != nv50->vtxelt->pipe[i].instance_divisor)
352 continue;
353 b = nv50->vtxelt->pipe[i].vertex_buffer_index;
354 bo = nouveau_bo(nv50->vtxbuf[b].buffer);
355
356 step[i] = 0;
357 pos[i] += nv50->vtxbuf[b].stride;
358
359 nv50_set_static_vtxattr(nv50, i, (uint8_t *)bo->map + pos[i]);
360 }
361 }
362
363 static void
364 step_per_instance_arrays(struct nv50_context *nv50,
365 unsigned pos[16], unsigned step[16])
366 {
367 struct nouveau_grobj *tesla = nv50->screen->tesla;
368 struct nouveau_channel *chan = tesla->channel;
369 struct nouveau_bo *bo;
370 struct nouveau_stateobj *so;
371 unsigned i, b, num_elements = nv50->vtxelt->num_elements;
372 const uint32_t rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
373
374 if (nv50->vbo_fifo) {
375 step_per_instance_arrays_immd(nv50, pos, step);
376 return;
377 }
378
379 so = so_new(num_elements, num_elements * 2, num_elements * 2);
380
381 for (i = 0; i < nv50->vtxelt->num_elements; ++i) {
382 if (!nv50->vtxelt->pipe[i].instance_divisor)
383 continue;
384 b = nv50->vtxelt->pipe[i].vertex_buffer_index;
385
386 if (++step[i] == nv50->vtxelt->pipe[i].instance_divisor) {
387 step[i] = 0;
388 pos[i] += nv50->vtxbuf[b].stride;
389 }
390
391 bo = nouveau_bo(nv50->vtxbuf[b].buffer);
392
393 so_method(so, tesla, NV50TCL_VERTEX_ARRAY_START_HIGH(i), 2);
394 so_reloc (so, bo, pos[i], rl | NOUVEAU_BO_HIGH, 0, 0);
395 so_reloc (so, bo, pos[i], rl | NOUVEAU_BO_LOW, 0, 0);
396 }
397
398 so_ref (so, &nv50->state.instbuf); /* for flush notify */
399 so_ref (NULL, &so);
400
401 so_emit(chan, nv50->state.instbuf);
402 }
403
404 static INLINE void
405 nv50_unmap_vbufs(struct nv50_context *nv50)
406 {
407 unsigned i;
408
409 for (i = 0; i < nv50->vtxbuf_nr; ++i)
410 if (nouveau_bo(nv50->vtxbuf[i].buffer)->map)
411 nouveau_bo_unmap(nouveau_bo(nv50->vtxbuf[i].buffer));
412 }
413
414 void
415 nv50_draw_arrays_instanced(struct pipe_context *pipe,
416 unsigned mode, unsigned start, unsigned count,
417 unsigned startInstance, unsigned instanceCount)
418 {
419 struct nv50_context *nv50 = nv50_context(pipe);
420 struct nouveau_channel *chan = nv50->screen->tesla->channel;
421 struct nouveau_grobj *tesla = nv50->screen->tesla;
422 unsigned i, nz_divisors;
423 unsigned step[16], pos[16];
424
425 if (!NV50_USING_LOATHED_EDGEFLAG(nv50))
426 nv50_upload_user_vbufs(nv50);
427
428 if (!nv50_state_validate(nv50, 0))
429 return;
430 chan->flush_notify = nv50_state_flush_notify;
431
432 nz_divisors = init_per_instance_arrays(nv50, startInstance, pos, step);
433
434 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 2);
435 OUT_RING (chan, NV50_CB_AUX | (24 << 8));
436 OUT_RING (chan, startInstance);
437
438 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
439 OUT_RING (chan, nv50_prim(mode));
440
441 if (nv50->vbo_fifo)
442 nv50_push_arrays(nv50, start, count);
443 else {
444 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BUFFER_FIRST, 2);
445 OUT_RING (chan, start);
446 OUT_RING (chan, count);
447 }
448 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
449 OUT_RING (chan, 0);
450
451 for (i = 1; i < instanceCount; i++) {
452 if (nz_divisors) /* any non-zero array divisors ? */
453 step_per_instance_arrays(nv50, pos, step);
454
455 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
456 OUT_RING (chan, nv50_prim(mode) | (1 << 28));
457
458 if (nv50->vbo_fifo)
459 nv50_push_arrays(nv50, start, count);
460 else {
461 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BUFFER_FIRST, 2);
462 OUT_RING (chan, start);
463 OUT_RING (chan, count);
464 }
465 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
466 OUT_RING (chan, 0);
467 }
468
469 chan->flush_notify = NULL;
470 nv50_unmap_vbufs(nv50);
471
472 so_ref(NULL, &nv50->state.instbuf);
473 }
474
475 void
476 nv50_draw_arrays(struct pipe_context *pipe, unsigned mode, unsigned start,
477 unsigned count)
478 {
479 struct nv50_context *nv50 = nv50_context(pipe);
480 struct nouveau_channel *chan = nv50->screen->tesla->channel;
481 struct nouveau_grobj *tesla = nv50->screen->tesla;
482 boolean ret;
483
484 if (!nv50_state_validate(nv50, 11))
485 return;
486 chan->flush_notify = nv50_state_flush_notify;
487
488 BEGIN_RING(chan, tesla, 0x142c, 1);
489 OUT_RING (chan, 0);
490 BEGIN_RING(chan, tesla, 0x142c, 1);
491 OUT_RING (chan, 0);
492
493 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
494 OUT_RING (chan, nv50_prim(mode));
495
496 if (nv50->vbo_fifo)
497 ret = nv50_push_arrays(nv50, start, count);
498 else {
499 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BUFFER_FIRST, 2);
500 OUT_RING (chan, start);
501 OUT_RING (chan, count);
502 ret = TRUE;
503 }
504 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
505 OUT_RING (chan, 0);
506
507 chan->flush_notify = NULL;
508 nv50_unmap_vbufs(nv50);
509
510 /* XXX: not sure what to do if ret != TRUE: flush and retry?
511 */
512 assert(ret);
513 }
514
515 static INLINE boolean
516 nv50_draw_elements_inline_u08(struct nv50_context *nv50, uint8_t *map,
517 unsigned start, unsigned count)
518 {
519 struct nouveau_channel *chan = nv50->screen->tesla->channel;
520 struct nouveau_grobj *tesla = nv50->screen->tesla;
521
522 map += start;
523
524 if (nv50->vbo_fifo)
525 return nv50_push_elements_u08(nv50, map, count);
526
527 if (count & 1) {
528 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U32, 1);
529 OUT_RING (chan, map[0]);
530 map++;
531 count--;
532 }
533
534 while (count) {
535 unsigned nr = count > 2046 ? 2046 : count;
536 int i;
537
538 BEGIN_RING_NI(chan, tesla, NV50TCL_VB_ELEMENT_U16, nr >> 1);
539 for (i = 0; i < nr; i += 2)
540 OUT_RING (chan, (map[i + 1] << 16) | map[i]);
541
542 count -= nr;
543 map += nr;
544 }
545 return TRUE;
546 }
547
548 static INLINE boolean
549 nv50_draw_elements_inline_u16(struct nv50_context *nv50, uint16_t *map,
550 unsigned start, unsigned count)
551 {
552 struct nouveau_channel *chan = nv50->screen->tesla->channel;
553 struct nouveau_grobj *tesla = nv50->screen->tesla;
554
555 map += start;
556
557 if (nv50->vbo_fifo)
558 return nv50_push_elements_u16(nv50, map, count);
559
560 if (count & 1) {
561 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U32, 1);
562 OUT_RING (chan, map[0]);
563 map++;
564 count--;
565 }
566
567 while (count) {
568 unsigned nr = count > 2046 ? 2046 : count;
569 int i;
570
571 BEGIN_RING_NI(chan, tesla, NV50TCL_VB_ELEMENT_U16, nr >> 1);
572 for (i = 0; i < nr; i += 2)
573 OUT_RING (chan, (map[i + 1] << 16) | map[i]);
574
575 count -= nr;
576 map += nr;
577 }
578 return TRUE;
579 }
580
581 static INLINE boolean
582 nv50_draw_elements_inline_u32(struct nv50_context *nv50, uint32_t *map,
583 unsigned start, unsigned count)
584 {
585 struct nouveau_channel *chan = nv50->screen->tesla->channel;
586 struct nouveau_grobj *tesla = nv50->screen->tesla;
587
588 map += start;
589
590 if (nv50->vbo_fifo)
591 return nv50_push_elements_u32(nv50, map, count);
592
593 while (count) {
594 unsigned nr = count > 2047 ? 2047 : count;
595
596 BEGIN_RING_NI(chan, tesla, NV50TCL_VB_ELEMENT_U32, nr);
597 OUT_RINGp (chan, map, nr);
598
599 count -= nr;
600 map += nr;
601 }
602 return TRUE;
603 }
604
605 static INLINE void
606 nv50_draw_elements_inline(struct nv50_context *nv50,
607 void *map, unsigned indexSize,
608 unsigned start, unsigned count)
609 {
610 switch (indexSize) {
611 case 1:
612 nv50_draw_elements_inline_u08(nv50, map, start, count);
613 break;
614 case 2:
615 nv50_draw_elements_inline_u16(nv50, map, start, count);
616 break;
617 case 4:
618 nv50_draw_elements_inline_u32(nv50, map, start, count);
619 break;
620 }
621 }
622
623 void
624 nv50_draw_elements_instanced(struct pipe_context *pipe,
625 struct pipe_buffer *indexBuffer,
626 unsigned indexSize,
627 unsigned mode, unsigned start, unsigned count,
628 unsigned startInstance, unsigned instanceCount)
629 {
630 struct nv50_context *nv50 = nv50_context(pipe);
631 struct nouveau_grobj *tesla = nv50->screen->tesla;
632 struct nouveau_channel *chan = tesla->channel;
633 struct pipe_screen *pscreen = pipe->screen;
634 void *map;
635 unsigned i, nz_divisors;
636 unsigned step[16], pos[16];
637
638 map = pipe_buffer_map(pscreen, indexBuffer, PIPE_BUFFER_USAGE_CPU_READ);
639
640 if (!NV50_USING_LOATHED_EDGEFLAG(nv50))
641 nv50_upload_user_vbufs(nv50);
642
643 if (!nv50_state_validate(nv50, 0))
644 return;
645 chan->flush_notify = nv50_state_flush_notify;
646
647 nz_divisors = init_per_instance_arrays(nv50, startInstance, pos, step);
648
649 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 2);
650 OUT_RING (chan, NV50_CB_AUX | (24 << 8));
651 OUT_RING (chan, startInstance);
652
653 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
654 OUT_RING (chan, nv50_prim(mode));
655
656 nv50_draw_elements_inline(nv50, map, indexSize, start, count);
657
658 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
659 OUT_RING (chan, 0);
660
661 for (i = 1; i < instanceCount; ++i) {
662 if (nz_divisors) /* any non-zero array divisors ? */
663 step_per_instance_arrays(nv50, pos, step);
664
665 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
666 OUT_RING (chan, nv50_prim(mode) | (1 << 28));
667
668 nv50_draw_elements_inline(nv50, map, indexSize, start, count);
669
670 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
671 OUT_RING (chan, 0);
672 }
673
674 chan->flush_notify = NULL;
675 nv50_unmap_vbufs(nv50);
676
677 so_ref(NULL, &nv50->state.instbuf);
678 }
679
680 void
681 nv50_draw_elements(struct pipe_context *pipe,
682 struct pipe_buffer *indexBuffer, unsigned indexSize,
683 unsigned mode, unsigned start, unsigned count)
684 {
685 struct nv50_context *nv50 = nv50_context(pipe);
686 struct nouveau_channel *chan = nv50->screen->tesla->channel;
687 struct nouveau_grobj *tesla = nv50->screen->tesla;
688 struct pipe_screen *pscreen = pipe->screen;
689 void *map;
690
691 if (!nv50_state_validate(nv50, 14))
692 return;
693 chan->flush_notify = nv50_state_flush_notify;
694
695 BEGIN_RING(chan, tesla, 0x142c, 1);
696 OUT_RING (chan, 0);
697 BEGIN_RING(chan, tesla, 0x142c, 1);
698 OUT_RING (chan, 0);
699
700 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
701 OUT_RING (chan, nv50_prim(mode));
702
703 if (!nv50->vbo_fifo && indexSize == 4) {
704 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U32 | 0x30000, 0);
705 OUT_RING (chan, count);
706 nouveau_pushbuf_submit(chan, nouveau_bo(indexBuffer),
707 start << 2, count << 2);
708 } else
709 if (!nv50->vbo_fifo && indexSize == 2) {
710 unsigned vb_start = (start & ~1);
711 unsigned vb_end = (start + count + 1) & ~1;
712 unsigned dwords = (vb_end - vb_start) >> 1;
713
714 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U16_SETUP, 1);
715 OUT_RING (chan, ((start & 1) << 31) | count);
716 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U16 | 0x30000, 0);
717 OUT_RING (chan, dwords);
718 nouveau_pushbuf_submit(chan, nouveau_bo(indexBuffer),
719 vb_start << 1, dwords << 2);
720 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U16_SETUP, 1);
721 OUT_RING (chan, 0);
722 } else {
723 map = pipe_buffer_map(pscreen, indexBuffer,
724 PIPE_BUFFER_USAGE_CPU_READ);
725 nv50_draw_elements_inline(nv50, map, indexSize, start, count);
726 nv50_unmap_vbufs(nv50);
727 pipe_buffer_unmap(pscreen, indexBuffer);
728 }
729
730 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
731 OUT_RING (chan, 0);
732 chan->flush_notify = NULL;
733 }
734
735 static INLINE boolean
736 nv50_vbo_static_attrib(struct nv50_context *nv50, unsigned attrib,
737 struct nouveau_stateobj **pso,
738 struct pipe_vertex_element *ve,
739 struct pipe_vertex_buffer *vb)
740
741 {
742 struct nouveau_stateobj *so;
743 struct nouveau_grobj *tesla = nv50->screen->tesla;
744 struct nouveau_bo *bo = nouveau_bo(vb->buffer);
745 float v[4];
746 int ret;
747 unsigned nr_components = util_format_get_nr_components(ve->src_format);
748
749 ret = nouveau_bo_map(bo, NOUVEAU_BO_RD);
750 if (ret)
751 return FALSE;
752
753 util_format_read_4f(ve->src_format, v, 0, (uint8_t *)bo->map +
754 (vb->buffer_offset + ve->src_offset), 0,
755 0, 0, 1, 1);
756 so = *pso;
757 if (!so)
758 *pso = so = so_new(nv50->vtxelt->num_elements,
759 nv50->vtxelt->num_elements * 4, 0);
760
761 switch (nr_components) {
762 case 4:
763 so_method(so, tesla, NV50TCL_VTX_ATTR_4F_X(attrib), 4);
764 so_data (so, fui(v[0]));
765 so_data (so, fui(v[1]));
766 so_data (so, fui(v[2]));
767 so_data (so, fui(v[3]));
768 break;
769 case 3:
770 so_method(so, tesla, NV50TCL_VTX_ATTR_3F_X(attrib), 3);
771 so_data (so, fui(v[0]));
772 so_data (so, fui(v[1]));
773 so_data (so, fui(v[2]));
774 break;
775 case 2:
776 so_method(so, tesla, NV50TCL_VTX_ATTR_2F_X(attrib), 2);
777 so_data (so, fui(v[0]));
778 so_data (so, fui(v[1]));
779 break;
780 case 1:
781 if (attrib == nv50->vertprog->cfg.edgeflag_in) {
782 so_method(so, tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
783 so_data (so, v[0] ? 1 : 0);
784 }
785 so_method(so, tesla, NV50TCL_VTX_ATTR_1F(attrib), 1);
786 so_data (so, fui(v[0]));
787 break;
788 default:
789 nouveau_bo_unmap(bo);
790 return FALSE;
791 }
792
793 nouveau_bo_unmap(bo);
794 return TRUE;
795 }
796
797 void
798 nv50_vtxelt_construct(struct nv50_vtxelt_stateobj *cso)
799 {
800 unsigned i;
801
802 for (i = 0; i < cso->num_elements; ++i) {
803 struct pipe_vertex_element *ve = &cso->pipe[i];
804
805 cso->hw[i] = nv50_vbo_vtxelt_to_hw(ve);
806 }
807 }
808
809 struct nouveau_stateobj *
810 nv50_vbo_validate(struct nv50_context *nv50)
811 {
812 struct nouveau_grobj *tesla = nv50->screen->tesla;
813 struct nouveau_stateobj *vtxbuf, *vtxfmt, *vtxattr;
814 unsigned i, n_ve;
815
816 /* don't validate if Gallium took away our buffers */
817 if (nv50->vtxbuf_nr == 0)
818 return NULL;
819 nv50->vbo_fifo = 0;
820
821 for (i = 0; i < nv50->vtxbuf_nr; ++i)
822 if (nv50->vtxbuf[i].stride &&
823 !(nv50->vtxbuf[i].buffer->usage & PIPE_BUFFER_USAGE_VERTEX))
824 nv50->vbo_fifo = 0xffff;
825
826 if (NV50_USING_LOATHED_EDGEFLAG(nv50))
827 nv50->vbo_fifo = 0xffff; /* vertprog can't set edgeflag */
828
829 n_ve = MAX2(nv50->vtxelt->num_elements, nv50->state.vtxelt_nr);
830
831 vtxattr = NULL;
832 vtxbuf = so_new(n_ve * 2, n_ve * 5, nv50->vtxelt->num_elements * 4);
833 vtxfmt = so_new(1, n_ve, 0);
834 so_method(vtxfmt, tesla, NV50TCL_VERTEX_ARRAY_ATTRIB(0), n_ve);
835
836 for (i = 0; i < nv50->vtxelt->num_elements; i++) {
837 struct pipe_vertex_element *ve = &nv50->vtxelt->pipe[i];
838 struct pipe_vertex_buffer *vb =
839 &nv50->vtxbuf[ve->vertex_buffer_index];
840 struct nouveau_bo *bo = nouveau_bo(vb->buffer);
841 uint32_t hw = nv50->vtxelt->hw[i];
842
843 if (!vb->stride &&
844 nv50_vbo_static_attrib(nv50, i, &vtxattr, ve, vb)) {
845 so_data(vtxfmt, hw | (1 << 4));
846
847 so_method(vtxbuf, tesla,
848 NV50TCL_VERTEX_ARRAY_FORMAT(i), 1);
849 so_data (vtxbuf, 0);
850
851 nv50->vbo_fifo &= ~(1 << i);
852 continue;
853 }
854
855 if (nv50->vbo_fifo) {
856 so_data (vtxfmt, hw |
857 (ve->instance_divisor ? (1 << 4) : i));
858 so_method(vtxbuf, tesla,
859 NV50TCL_VERTEX_ARRAY_FORMAT(i), 1);
860 so_data (vtxbuf, 0);
861 continue;
862 }
863 so_data(vtxfmt, hw | i);
864
865 so_method(vtxbuf, tesla, NV50TCL_VERTEX_ARRAY_FORMAT(i), 3);
866 so_data (vtxbuf, 0x20000000 |
867 (ve->instance_divisor ? 0 : vb->stride));
868 so_reloc (vtxbuf, bo, vb->buffer_offset +
869 ve->src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
870 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
871 so_reloc (vtxbuf, bo, vb->buffer_offset +
872 ve->src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
873 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
874
875 /* vertex array limits */
876 so_method(vtxbuf, tesla, NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
877 so_reloc (vtxbuf, bo, vb->buffer->size - 1,
878 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
879 NOUVEAU_BO_HIGH, 0, 0);
880 so_reloc (vtxbuf, bo, vb->buffer->size - 1,
881 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
882 NOUVEAU_BO_LOW, 0, 0);
883 }
884 for (; i < n_ve; ++i) {
885 so_data (vtxfmt, 0x7e080010);
886
887 so_method(vtxbuf, tesla, NV50TCL_VERTEX_ARRAY_FORMAT(i), 1);
888 so_data (vtxbuf, 0);
889 }
890 nv50->state.vtxelt_nr = nv50->vtxelt->num_elements;
891
892 so_ref (vtxbuf, &nv50->state.vtxbuf);
893 so_ref (vtxattr, &nv50->state.vtxattr);
894 so_ref (NULL, &vtxbuf);
895 so_ref (NULL, &vtxattr);
896 return vtxfmt;
897 }
898
899 typedef void (*pfn_push)(struct nouveau_channel *, void *);
900
901 struct nv50_vbo_emitctx
902 {
903 pfn_push push[16];
904 uint8_t *map[16];
905 unsigned stride[16];
906 unsigned nr_ve;
907 unsigned vtx_dwords;
908 unsigned vtx_max;
909
910 float edgeflag;
911 unsigned ve_edgeflag;
912 };
913
914 static INLINE void
915 emit_vtx_next(struct nouveau_channel *chan, struct nv50_vbo_emitctx *emit)
916 {
917 unsigned i;
918
919 for (i = 0; i < emit->nr_ve; ++i) {
920 emit->push[i](chan, emit->map[i]);
921 emit->map[i] += emit->stride[i];
922 }
923 }
924
925 static INLINE void
926 emit_vtx(struct nouveau_channel *chan, struct nv50_vbo_emitctx *emit,
927 uint32_t vi)
928 {
929 unsigned i;
930
931 for (i = 0; i < emit->nr_ve; ++i)
932 emit->push[i](chan, emit->map[i] + emit->stride[i] * vi);
933 }
934
935 static INLINE boolean
936 nv50_map_vbufs(struct nv50_context *nv50)
937 {
938 int i;
939
940 for (i = 0; i < nv50->vtxbuf_nr; ++i) {
941 struct pipe_vertex_buffer *vb = &nv50->vtxbuf[i];
942 unsigned size = vb->stride * (vb->max_index + 1) + 16;
943
944 if (nouveau_bo(vb->buffer)->map)
945 continue;
946
947 size = vb->stride * (vb->max_index + 1) + 16;
948 size = MIN2(size, vb->buffer->size);
949 if (!size)
950 size = vb->buffer->size;
951
952 if (nouveau_bo_map_range(nouveau_bo(vb->buffer),
953 0, size, NOUVEAU_BO_RD))
954 break;
955 }
956
957 if (i == nv50->vtxbuf_nr)
958 return TRUE;
959 for (; i >= 0; --i)
960 nouveau_bo_unmap(nouveau_bo(nv50->vtxbuf[i].buffer));
961 return FALSE;
962 }
963
964 static void
965 emit_b32_1(struct nouveau_channel *chan, void *data)
966 {
967 uint32_t *v = data;
968
969 OUT_RING(chan, v[0]);
970 }
971
972 static void
973 emit_b32_2(struct nouveau_channel *chan, void *data)
974 {
975 uint32_t *v = data;
976
977 OUT_RING(chan, v[0]);
978 OUT_RING(chan, v[1]);
979 }
980
981 static void
982 emit_b32_3(struct nouveau_channel *chan, void *data)
983 {
984 uint32_t *v = data;
985
986 OUT_RING(chan, v[0]);
987 OUT_RING(chan, v[1]);
988 OUT_RING(chan, v[2]);
989 }
990
991 static void
992 emit_b32_4(struct nouveau_channel *chan, void *data)
993 {
994 uint32_t *v = data;
995
996 OUT_RING(chan, v[0]);
997 OUT_RING(chan, v[1]);
998 OUT_RING(chan, v[2]);
999 OUT_RING(chan, v[3]);
1000 }
1001
1002 static void
1003 emit_b16_1(struct nouveau_channel *chan, void *data)
1004 {
1005 uint16_t *v = data;
1006
1007 OUT_RING(chan, v[0]);
1008 }
1009
1010 static void
1011 emit_b16_3(struct nouveau_channel *chan, void *data)
1012 {
1013 uint16_t *v = data;
1014
1015 OUT_RING(chan, (v[1] << 16) | v[0]);
1016 OUT_RING(chan, v[2]);
1017 }
1018
1019 static void
1020 emit_b08_1(struct nouveau_channel *chan, void *data)
1021 {
1022 uint8_t *v = data;
1023
1024 OUT_RING(chan, v[0]);
1025 }
1026
1027 static void
1028 emit_b08_3(struct nouveau_channel *chan, void *data)
1029 {
1030 uint8_t *v = data;
1031
1032 OUT_RING(chan, (v[2] << 16) | (v[1] << 8) | v[0]);
1033 }
1034
1035 static boolean
1036 emit_prepare(struct nv50_context *nv50, struct nv50_vbo_emitctx *emit,
1037 unsigned start)
1038 {
1039 unsigned i;
1040
1041 if (nv50_map_vbufs(nv50) == FALSE)
1042 return FALSE;
1043
1044 emit->ve_edgeflag = nv50->vertprog->cfg.edgeflag_in;
1045
1046 emit->edgeflag = 0.5f;
1047 emit->nr_ve = 0;
1048 emit->vtx_dwords = 0;
1049
1050 for (i = 0; i < nv50->vtxelt->num_elements; ++i) {
1051 struct pipe_vertex_element *ve;
1052 struct pipe_vertex_buffer *vb;
1053 unsigned n, size, nr_components;
1054 const struct util_format_description *desc;
1055
1056 ve = &nv50->vtxelt->pipe[i];
1057 vb = &nv50->vtxbuf[ve->vertex_buffer_index];
1058 if (!(nv50->vbo_fifo & (1 << i)) || ve->instance_divisor)
1059 continue;
1060 n = emit->nr_ve++;
1061
1062 emit->stride[n] = vb->stride;
1063 emit->map[n] = (uint8_t *)nouveau_bo(vb->buffer)->map +
1064 vb->buffer_offset +
1065 (start * vb->stride + ve->src_offset);
1066
1067 desc = util_format_description(ve->src_format);
1068 assert(desc);
1069
1070 size = util_format_get_component_bits(
1071 ve->src_format, UTIL_FORMAT_COLORSPACE_RGB, 0);
1072 nr_components = util_format_get_nr_components(ve->src_format);
1073
1074 assert(nr_components > 0 && nr_components <= 4);
1075
1076 /* It shouldn't be necessary to push the implicit 1s
1077 * for case 3 and size 8 cases 1, 2, 3.
1078 */
1079 switch (size) {
1080 default:
1081 NOUVEAU_ERR("unsupported vtxelt size: %u\n", size);
1082 return FALSE;
1083 case 32:
1084 switch (nr_components) {
1085 case 1: emit->push[n] = emit_b32_1; break;
1086 case 2: emit->push[n] = emit_b32_2; break;
1087 case 3: emit->push[n] = emit_b32_3; break;
1088 case 4: emit->push[n] = emit_b32_4; break;
1089 }
1090 emit->vtx_dwords += nr_components;
1091 break;
1092 case 16:
1093 switch (nr_components) {
1094 case 1: emit->push[n] = emit_b16_1; break;
1095 case 2: emit->push[n] = emit_b32_1; break;
1096 case 3: emit->push[n] = emit_b16_3; break;
1097 case 4: emit->push[n] = emit_b32_2; break;
1098 }
1099 emit->vtx_dwords += (nr_components + 1) >> 1;
1100 break;
1101 case 8:
1102 switch (nr_components) {
1103 case 1: emit->push[n] = emit_b08_1; break;
1104 case 2: emit->push[n] = emit_b16_1; break;
1105 case 3: emit->push[n] = emit_b08_3; break;
1106 case 4: emit->push[n] = emit_b32_1; break;
1107 }
1108 emit->vtx_dwords += 1;
1109 break;
1110 }
1111 }
1112
1113 emit->vtx_max = 512 / emit->vtx_dwords;
1114 if (emit->ve_edgeflag < 16)
1115 emit->vtx_max = 1;
1116
1117 return TRUE;
1118 }
1119
1120 static INLINE void
1121 set_edgeflag(struct nouveau_channel *chan,
1122 struct nouveau_grobj *tesla,
1123 struct nv50_vbo_emitctx *emit, uint32_t index)
1124 {
1125 unsigned i = emit->ve_edgeflag;
1126
1127 if (i < 16) {
1128 float f = *((float *)(emit->map[i] + index * emit->stride[i]));
1129
1130 if (emit->edgeflag != f) {
1131 emit->edgeflag = f;
1132
1133 BEGIN_RING(chan, tesla, 0x15e4, 1);
1134 OUT_RING (chan, f ? 1 : 0);
1135 }
1136 }
1137 }
1138
1139 static boolean
1140 nv50_push_arrays(struct nv50_context *nv50, unsigned start, unsigned count)
1141 {
1142 struct nouveau_channel *chan = nv50->screen->base.channel;
1143 struct nouveau_grobj *tesla = nv50->screen->tesla;
1144 struct nv50_vbo_emitctx emit;
1145
1146 if (emit_prepare(nv50, &emit, start) == FALSE)
1147 return FALSE;
1148
1149 while (count) {
1150 unsigned i, dw, nr = MIN2(count, emit.vtx_max);
1151 dw = nr * emit.vtx_dwords;
1152
1153 set_edgeflag(chan, tesla, &emit, 0); /* nr will be 1 */
1154
1155 BEGIN_RING_NI(chan, tesla, NV50TCL_VERTEX_DATA, dw);
1156 for (i = 0; i < nr; ++i)
1157 emit_vtx_next(chan, &emit);
1158
1159 count -= nr;
1160 }
1161
1162 return TRUE;
1163 }
1164
1165 static boolean
1166 nv50_push_elements_u32(struct nv50_context *nv50, uint32_t *map, unsigned count)
1167 {
1168 struct nouveau_channel *chan = nv50->screen->base.channel;
1169 struct nouveau_grobj *tesla = nv50->screen->tesla;
1170 struct nv50_vbo_emitctx emit;
1171
1172 if (emit_prepare(nv50, &emit, 0) == FALSE)
1173 return FALSE;
1174
1175 while (count) {
1176 unsigned i, dw, nr = MIN2(count, emit.vtx_max);
1177 dw = nr * emit.vtx_dwords;
1178
1179 set_edgeflag(chan, tesla, &emit, *map);
1180
1181 BEGIN_RING_NI(chan, tesla, NV50TCL_VERTEX_DATA, dw);
1182 for (i = 0; i < nr; ++i)
1183 emit_vtx(chan, &emit, *map++);
1184
1185 count -= nr;
1186 }
1187
1188 return TRUE;
1189 }
1190
1191 static boolean
1192 nv50_push_elements_u16(struct nv50_context *nv50, uint16_t *map, unsigned count)
1193 {
1194 struct nouveau_channel *chan = nv50->screen->base.channel;
1195 struct nouveau_grobj *tesla = nv50->screen->tesla;
1196 struct nv50_vbo_emitctx emit;
1197
1198 if (emit_prepare(nv50, &emit, 0) == FALSE)
1199 return FALSE;
1200
1201 while (count) {
1202 unsigned i, dw, nr = MIN2(count, emit.vtx_max);
1203 dw = nr * emit.vtx_dwords;
1204
1205 set_edgeflag(chan, tesla, &emit, *map);
1206
1207 BEGIN_RING_NI(chan, tesla, NV50TCL_VERTEX_DATA, dw);
1208 for (i = 0; i < nr; ++i)
1209 emit_vtx(chan, &emit, *map++);
1210
1211 count -= nr;
1212 }
1213
1214 return TRUE;
1215 }
1216
1217 static boolean
1218 nv50_push_elements_u08(struct nv50_context *nv50, uint8_t *map, unsigned count)
1219 {
1220 struct nouveau_channel *chan = nv50->screen->base.channel;
1221 struct nouveau_grobj *tesla = nv50->screen->tesla;
1222 struct nv50_vbo_emitctx emit;
1223
1224 if (emit_prepare(nv50, &emit, 0) == FALSE)
1225 return FALSE;
1226
1227 while (count) {
1228 unsigned i, dw, nr = MIN2(count, emit.vtx_max);
1229 dw = nr * emit.vtx_dwords;
1230
1231 set_edgeflag(chan, tesla, &emit, *map);
1232
1233 BEGIN_RING_NI(chan, tesla, NV50TCL_VERTEX_DATA, dw);
1234 for (i = 0; i < nr; ++i)
1235 emit_vtx(chan, &emit, *map++);
1236
1237 count -= nr;
1238 }
1239
1240 return TRUE;
1241 }