src/gallium/drivers/nv50/nv50_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "pipe/p_context.h"
  24 #include "pipe/p_state.h"
  25 #include "util/u_inlines.h"
  26 #include "util/u_format.h"
  27 #include "translate/translate.h"
  28
  29 #include "nv50_context.h"
  30 #include "nv50_resource.h"
  31
  32 #include "nv50_3d.xml.h"
  33
  34 void
  35 nv50_vertex_state_delete(struct pipe_context *pipe,
  36                          void *hwcso)
  37 {
  38    struct nv50_vertex_stateobj *so = hwcso;
  39
  40    if (so->translate)
  41       so->translate->release(so->translate);
  42    FREE(hwcso);
  43 }
  44
  45 void *
  46 nv50_vertex_state_create(struct pipe_context *pipe,
  47                          unsigned num_elements,
  48                          const struct pipe_vertex_element *elements)
  49 {
  50     struct nv50_vertex_stateobj *so;
  51     struct translate_key transkey;
  52     unsigned i;
  53
  54     so = MALLOC(sizeof(*so) +
  55                 num_elements * sizeof(struct nv50_vertex_element));
  56     if (!so)
  57         return NULL;
  58     so->num_elements = num_elements;
  59     so->instance_elts = 0;
  60     so->instance_bufs = 0;
  61     so->need_conversion = FALSE;
  62
  63     transkey.nr_elements = 0;
  64     transkey.output_stride = 0;
  65
  66     for (i = 0; i < num_elements; ++i) {
  67         const struct pipe_vertex_element *ve = &elements[i];
  68         const unsigned vbi = ve->vertex_buffer_index;
  69         enum pipe_format fmt = ve->src_format;
  70
  71         so->element[i].pipe = elements[i];
  72         so->element[i].state = nv50_format_table[fmt].vtx;
  73
  74         if (!so->element[i].state) {
  75             switch (util_format_get_nr_components(fmt)) {
  76             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  77             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  78             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  79             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  80             default:
  81                 assert(0);
  82                 return NULL;
  83             }
  84             so->element[i].state = nv50_format_table[fmt].vtx;
  85             so->need_conversion = TRUE;
  86         }
  87         so->element[i].state |= i;
  88
  89         if (1) {
  90             unsigned j = transkey.nr_elements++;
  91
  92             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
  93             transkey.element[j].input_format = ve->src_format;
  94             transkey.element[j].input_buffer = vbi;
  95             transkey.element[j].input_offset = ve->src_offset;
  96             transkey.element[j].instance_divisor = ve->instance_divisor;
  97
  98             transkey.element[j].output_format = fmt;
  99             transkey.element[j].output_offset = transkey.output_stride;
 100             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
 101
 102             if (unlikely(ve->instance_divisor)) {
 103                so->instance_elts |= 1 << i;
 104                so->instance_bufs |= 1 << vbi;
 105             }
 106         }
 107     }
 108
 109     so->translate = translate_create(&transkey);
 110     so->vertex_size = transkey.output_stride / 4;
 111     so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
 112        MAX2(so->vertex_size, 1);
 113
 114     return so;
 115 }
 116
 117 #define NV50_3D_VERTEX_ATTRIB_INACTIVE              \
 118    NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT |         \
 119    NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
 120    NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
 121
 122 static void
 123 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
 124                   struct pipe_vertex_element *ve, unsigned attr)
 125 {
 126    const void *data;
 127    struct nouveau_channel *chan = nv50->screen->base.channel;
 128    struct nv04_resource *res = nv04_resource(vb->buffer);
 129    float v[4];
 130    const unsigned nc = util_format_get_nr_components(ve->src_format);
 131
 132    data = nouveau_resource_map_offset(&nv50->base, res, vb->buffer_offset +
 133                                       ve->src_offset, NOUVEAU_BO_RD);
 134
 135    util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
 136
 137    switch (nc) {
 138    case 4:
 139       BEGIN_RING(chan, RING_3D(VTX_ATTR_4F_X(attr)), 4);
 140       OUT_RINGf (chan, v[0]);
 141       OUT_RINGf (chan, v[1]);
 142       OUT_RINGf (chan, v[2]);
 143       OUT_RINGf (chan, v[3]);
 144       break;
 145    case 3:
 146       BEGIN_RING(chan, RING_3D(VTX_ATTR_3F_X(attr)), 3);
 147       OUT_RINGf (chan, v[0]);
 148       OUT_RINGf (chan, v[1]);
 149       OUT_RINGf (chan, v[2]);
 150       break;
 151    case 2:
 152       BEGIN_RING(chan, RING_3D(VTX_ATTR_2F_X(attr)), 2);
 153       OUT_RINGf (chan, v[0]);
 154       OUT_RINGf (chan, v[1]);
 155       break;
 156    case 1:
 157       if (attr == nv50->vertprog->vp.edgeflag) {
 158          BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 159          OUT_RING  (chan, v[0] ? 1 : 0);
 160       }
 161       BEGIN_RING(chan, RING_3D(VTX_ATTR_1F(attr)), 1);
 162       OUT_RINGf (chan, v[0]);
 163       break;
 164    default:
 165       assert(0);
 166       break;
 167    }
 168 }
 169
 170 static INLINE void
 171 nv50_vbuf_range(struct nv50_context *nv50, int vbi,
 172                 uint32_t *base, uint32_t *size)
 173 {
 174    if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
 175       /* TODO: use min and max instance divisor to get a proper range */
 176       *base = 0;
 177       *size = nv50->vtxbuf[vbi].buffer->width0;
 178    } else {
 179       assert(nv50->vbo_max_index != ~0);
 180       *base = nv50->vbo_min_index * nv50->vtxbuf[vbi].stride;
 181       *size = (nv50->vbo_max_index -
 182                nv50->vbo_min_index + 1) * nv50->vtxbuf[vbi].stride;
 183    }
 184 }
 185
 186 static void
 187 nv50_prevalidate_vbufs(struct nv50_context *nv50)
 188 {
 189    struct pipe_vertex_buffer *vb;
 190    struct nv04_resource *buf;
 191    int i;
 192    uint32_t base, size;
 193
 194    nv50->vbo_fifo = nv50->vbo_user = 0;
 195
 196    nv50_bufctx_reset(nv50, NV50_BUFCTX_VERTEX);
 197
 198    for (i = 0; i < nv50->num_vtxbufs; ++i) {
 199       vb = &nv50->vtxbuf[i];
 200       if (!vb->stride)
 201          continue;
 202       buf = nv04_resource(vb->buffer);
 203
 204       /* NOTE: user buffers with temporary storage count as mapped by GPU */
 205       if (!nouveau_resource_mapped_by_gpu(vb->buffer)) {
 206          if (nv50->vbo_push_hint) {
 207             nv50->vbo_fifo = ~0;
 208             continue;
 209          } else {
 210             if (buf->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY) {
 211                nv50->vbo_user |= 1 << i;
 212                assert(vb->stride > vb->buffer_offset);
 213                nv50_vbuf_range(nv50, i, &base, &size);
 214                nouveau_user_buffer_upload(buf, base, size);
 215             } else {
 216                nouveau_buffer_migrate(&nv50->base, buf, NOUVEAU_BO_GART);
 217             }
 218             nv50->base.vbo_dirty = TRUE;
 219          }
 220       }
 221       nv50_bufctx_add_resident(nv50, NV50_BUFCTX_VERTEX, buf, NOUVEAU_BO_RD);
 222       nouveau_buffer_adjust_score(&nv50->base, buf, 1);
 223    }
 224 }
 225
 226 static void
 227 nv50_update_user_vbufs(struct nv50_context *nv50)
 228 {
 229    struct nouveau_channel *chan = nv50->screen->base.channel;
 230    uint32_t base, offset, size;
 231    int i;
 232    uint32_t written = 0;
 233
 234    for (i = 0; i < nv50->vertex->num_elements; ++i) {
 235       struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
 236       const int b = ve->vertex_buffer_index;
 237       struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
 238       struct nv04_resource *buf = nv04_resource(vb->buffer);
 239
 240       if (!(nv50->vbo_user & (1 << b)))
 241          continue;
 242
 243       if (!vb->stride) {
 244          nv50_emit_vtxattr(nv50, vb, ve, i);
 245          continue;
 246       }
 247       nv50_vbuf_range(nv50, b, &base, &size);
 248
 249       if (!(written & (1 << b))) {
 250          written |= 1 << b;
 251          nouveau_user_buffer_upload(buf, base, size);
 252       }
 253       offset = vb->buffer_offset + ve->src_offset;
 254
 255       MARK_RING (chan, 6, 4);
 256       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 257       OUT_RESRCh(chan, buf, base + size - 1, NOUVEAU_BO_RD);
 258       OUT_RESRCl(chan, buf, base + size - 1, NOUVEAU_BO_RD);
 259       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
 260       OUT_RESRCh(chan, buf, offset, NOUVEAU_BO_RD);
 261       OUT_RESRCl(chan, buf, offset, NOUVEAU_BO_RD);
 262    }
 263    nv50->base.vbo_dirty = TRUE;
 264 }
 265
 266 static INLINE void
 267 nv50_release_user_vbufs(struct nv50_context *nv50)
 268 {
 269    uint32_t vbo_user = nv50->vbo_user;
 270
 271    while (vbo_user) {
 272       int i = ffs(vbo_user) - 1;
 273       vbo_user &= ~(1 << i);
 274
 275       nouveau_buffer_release_gpu_storage(nv04_resource(nv50->vtxbuf[i].buffer));
 276    }
 277 }
 278
 279 void
 280 nv50_vertex_arrays_validate(struct nv50_context *nv50)
 281 {
 282    struct nouveau_channel *chan = nv50->screen->base.channel;
 283    struct nv50_vertex_stateobj *vertex = nv50->vertex;
 284    struct pipe_vertex_buffer *vb;
 285    struct nv50_vertex_element *ve;
 286    unsigned i;
 287
 288    if (unlikely(vertex->need_conversion)) {
 289       nv50->vbo_fifo = ~0;
 290       nv50->vbo_user = 0;
 291    } else {
 292       nv50_prevalidate_vbufs(nv50);
 293    }
 294
 295    BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_ATTRIB(0)), vertex->num_elements);
 296    for (i = 0; i < vertex->num_elements; ++i) {
 297       ve = &vertex->element[i];
 298       vb = &nv50->vtxbuf[ve->pipe.vertex_buffer_index];
 299
 300       if (likely(vb->stride) || nv50->vbo_fifo) {
 301          OUT_RING(chan, ve->state);
 302       } else {
 303          OUT_RING(chan, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
 304          nv50->vbo_fifo &= ~(1 << i);
 305       }
 306    }
 307
 308    for (i = 0; i < vertex->num_elements; ++i) {
 309       struct nv04_resource *res;
 310       unsigned size, offset;
 311
 312       ve = &vertex->element[i];
 313       vb = &nv50->vtxbuf[ve->pipe.vertex_buffer_index];
 314
 315       if (unlikely(ve->pipe.instance_divisor)) {
 316          if (!(nv50->state.instance_elts & (1 << i))) {
 317             BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 318             OUT_RING  (chan, 1);
 319          }
 320          BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
 321          OUT_RING  (chan, ve->pipe.instance_divisor);
 322       } else
 323       if (unlikely(nv50->state.instance_elts & (1 << i))) {
 324          BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 325          OUT_RING  (chan, 0);
 326       }
 327
 328       res = nv04_resource(vb->buffer);
 329
 330       if (nv50->vbo_fifo || unlikely(vb->stride == 0)) {
 331          if (!nv50->vbo_fifo)
 332             nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
 333          BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
 334          OUT_RING  (chan, 0);
 335          continue;
 336       }
 337
 338       size = vb->buffer->width0;
 339       offset = ve->pipe.src_offset + vb->buffer_offset;
 340
 341       MARK_RING (chan, 8, 4);
 342       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
 343       OUT_RING  (chan, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 344       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 345       OUT_RESRCh(chan, res, size - 1, NOUVEAU_BO_RD);
 346       OUT_RESRCl(chan, res, size - 1, NOUVEAU_BO_RD);
 347       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
 348       OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
 349       OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
 350    }
 351    for (; i < nv50->state.num_vtxelts; ++i) {
 352       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_ATTRIB(i)), 1);
 353       OUT_RING  (chan, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 354       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
 355       OUT_RING  (chan, 0);
 356    }
 357
 358    nv50->state.num_vtxelts = vertex->num_elements;
 359    nv50->state.instance_elts = vertex->instance_elts;
 360 }
 361
 362 #define NV50_PRIM_GL_CASE(n) \
 363    case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 364
 365 static INLINE unsigned
 366 nv50_prim_gl(unsigned prim)
 367 {
 368    switch (prim) {
 369    NV50_PRIM_GL_CASE(POINTS);
 370    NV50_PRIM_GL_CASE(LINES);
 371    NV50_PRIM_GL_CASE(LINE_LOOP);
 372    NV50_PRIM_GL_CASE(LINE_STRIP);
 373    NV50_PRIM_GL_CASE(TRIANGLES);
 374    NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
 375    NV50_PRIM_GL_CASE(TRIANGLE_FAN);
 376    NV50_PRIM_GL_CASE(QUADS);
 377    NV50_PRIM_GL_CASE(QUAD_STRIP);
 378    NV50_PRIM_GL_CASE(POLYGON);
 379    NV50_PRIM_GL_CASE(LINES_ADJACENCY);
 380    NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 381    NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 382    NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 383    default:
 384       return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 385       break;
 386    }
 387 }
 388
 389 static void
 390 nv50_draw_vbo_flush_notify(struct nouveau_channel *chan)
 391 {
 392    struct nv50_screen *screen = chan->user_private;
 393
 394    nouveau_fence_update(&screen->base, TRUE);
 395
 396    nv50_bufctx_emit_relocs(screen->cur_ctx);
 397 }
 398
 399 static void
 400 nv50_draw_arrays(struct nv50_context *nv50,
 401                  unsigned mode, unsigned start, unsigned count,
 402                  unsigned instance_count)
 403 {
 404    struct nouveau_channel *chan = nv50->screen->base.channel;
 405    unsigned prim;
 406
 407    if (nv50->state.index_bias) {
 408       BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
 409       OUT_RING  (chan, 0);
 410       nv50->state.index_bias = 0;
 411    }
 412
 413    prim = nv50_prim_gl(mode);
 414
 415    while (instance_count--) {
 416       BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
 417       OUT_RING  (chan, prim);
 418       BEGIN_RING(chan, RING_3D(VERTEX_BUFFER_FIRST), 2);
 419       OUT_RING  (chan, start);
 420       OUT_RING  (chan, count);
 421       BEGIN_RING(chan, RING_3D(VERTEX_END_GL), 1);
 422       OUT_RING  (chan, 0);
 423
 424       prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 425    }
 426 }
 427
 428 static void
 429 nv50_draw_elements_inline_u08(struct nouveau_channel *chan, uint8_t *map,
 430                               unsigned start, unsigned count)
 431 {
 432    map += start;
 433
 434    if (count & 3) {
 435       unsigned i;
 436       BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), count & 3);
 437       for (i = 0; i < (count & 3); ++i)
 438          OUT_RING(chan, *map++);
 439       count &= ~3;
 440    }
 441    while (count) {
 442       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 443
 444       BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U8), nr);
 445       for (i = 0; i < nr; ++i) {
 446          OUT_RING(chan,
 447                   (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 448          map += 4;
 449       }
 450       count -= nr * 4;
 451    }
 452 }
 453
 454 static void
 455 nv50_draw_elements_inline_u16(struct nouveau_channel *chan, uint16_t *map,
 456                               unsigned start, unsigned count)
 457 {
 458    map += start;
 459
 460    if (count & 1) {
 461       count &= ~1;
 462       BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
 463       OUT_RING  (chan, *map++);
 464    }
 465    while (count) {
 466       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 467
 468       BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
 469       for (i = 0; i < nr; ++i) {
 470          OUT_RING(chan, (map[1] << 16) | map[0]);
 471          map += 2;
 472       }
 473       count -= nr * 2;
 474    }
 475 }
 476
 477 static void
 478 nv50_draw_elements_inline_u32(struct nouveau_channel *chan, uint32_t *map,
 479                               unsigned start, unsigned count)
 480 {
 481    map += start;
 482
 483    while (count) {
 484       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 485
 486       BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), nr);
 487       OUT_RINGp    (chan, map, nr);
 488
 489       map += nr;
 490       count -= nr;
 491    }
 492 }
 493
 494 static void
 495 nv50_draw_elements_inline_u32_short(struct nouveau_channel *chan, uint32_t *map,
 496                                     unsigned start, unsigned count)
 497 {
 498    map += start;
 499
 500    if (count & 1) {
 501       count--;
 502       BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
 503       OUT_RING  (chan, *map++);
 504    }
 505    while (count) {
 506       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 507
 508       BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
 509       for (i = 0; i < nr; ++i) {
 510          OUT_RING(chan, (map[1] << 16) | map[0]);
 511          map += 2;
 512       }
 513       count -= nr * 2;
 514    }
 515 }
 516
 517 static void
 518 nv50_draw_elements(struct nv50_context *nv50, boolean shorten,
 519                    unsigned mode, unsigned start, unsigned count,
 520                    unsigned instance_count, int32_t index_bias)
 521 {
 522    struct nouveau_channel *chan = nv50->screen->base.channel;
 523    void *data;
 524    unsigned prim;
 525    const unsigned index_size = nv50->idxbuf.index_size;
 526
 527    prim = nv50_prim_gl(mode);
 528
 529    if (index_bias != nv50->state.index_bias) {
 530       BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
 531       OUT_RING  (chan, index_bias);
 532       nv50->state.index_bias = index_bias;
 533    }
 534
 535    if (nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer)) {
 536       struct nv04_resource *res = nv04_resource(nv50->idxbuf.buffer);
 537
 538       start += nv50->idxbuf.offset >> (index_size >> 1);
 539
 540       nouveau_buffer_adjust_score(&nv50->base, res, 1);
 541
 542       while (instance_count--) {
 543          BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
 544          OUT_RING  (chan, mode);
 545
 546          switch (index_size) {
 547          case 4:
 548          {
 549             WAIT_RING (chan, 2);
 550             BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32) | 0x30000, 0);
 551             OUT_RING  (chan, count);
 552             nouveau_pushbuf_submit(chan, res->bo, res->offset + start * 4,
 553                                    count * 4);
 554          }
 555             break;
 556          case 2:
 557          {
 558             unsigned pb_start = (start & ~1);
 559             unsigned pb_words = (((start + count + 1) & ~1) - pb_start) >> 1;
 560
 561             BEGIN_RING(chan, RING_3D(VB_ELEMENT_U16_SETUP), 1);
 562             OUT_RING  (chan, (start << 31) | count);
 563             WAIT_RING (chan, 2);
 564             BEGIN_RING(chan, RING_3D(VB_ELEMENT_U16) | 0x30000, 0);
 565             OUT_RING  (chan, pb_words);
 566             nouveau_pushbuf_submit(chan, res->bo, res->offset + pb_start * 2,
 567                                    pb_words * 4);
 568             BEGIN_RING(chan, RING_3D(VB_ELEMENT_U16_SETUP), 1);
 569             OUT_RING  (chan, 0);
 570             break;
 571          }
 572          case 1:
 573          {
 574             unsigned pb_start = (start & ~3);
 575             unsigned pb_words = (((start + count + 3) & ~3) - pb_start) >> 1;
 576
 577             BEGIN_RING(chan, RING_3D(VB_ELEMENT_U8_SETUP), 1);
 578             OUT_RING  (chan, (start << 30) | count);
 579             WAIT_RING (chan, 2);
 580             BEGIN_RING(chan, RING_3D(VB_ELEMENT_U8) | 0x30000, 0);
 581             OUT_RING  (chan, pb_words);
 582             nouveau_pushbuf_submit(chan, res->bo, res->offset + pb_start,
 583                                    pb_words * 4);
 584             BEGIN_RING(chan, RING_3D(VB_ELEMENT_U8_SETUP), 1);
 585             OUT_RING  (chan, 0);
 586             break;
 587          }
 588          default:
 589             assert(0);
 590             return;
 591          }
 592          BEGIN_RING(chan, RING_3D(VERTEX_END_GL), 1);
 593          OUT_RING  (chan, 0);
 594
 595          nv50_resource_fence(res, NOUVEAU_BO_RD);
 596
 597          mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 598       }
 599    } else {
 600       data = nouveau_resource_map_offset(&nv50->base,
 601                                          nv04_resource(nv50->idxbuf.buffer),
 602                                          nv50->idxbuf.offset, NOUVEAU_BO_RD);
 603       if (!data)
 604          return;
 605
 606       while (instance_count--) {
 607          BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
 608          OUT_RING  (chan, prim);
 609          switch (index_size) {
 610          case 1:
 611             nv50_draw_elements_inline_u08(chan, data, start, count);
 612             break;
 613          case 2:
 614             nv50_draw_elements_inline_u16(chan, data, start, count);
 615             break;
 616          case 4:
 617             if (shorten)
 618                nv50_draw_elements_inline_u32_short(chan, data, start, count);
 619             else
 620                nv50_draw_elements_inline_u32(chan, data, start, count);
 621             break;
 622          default:
 623             assert(0);
 624             return;
 625          }
 626          BEGIN_RING(chan, RING_3D(VERTEX_END_GL), 1);
 627          OUT_RING  (chan, 0);
 628
 629          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 630       }
 631    }
 632 }
 633
 634 void
 635 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 636 {
 637    struct nv50_context *nv50 = nv50_context(pipe);
 638    struct nouveau_channel *chan = nv50->screen->base.channel;
 639
 640    /* For picking only a few vertices from a large user buffer, push is better,
 641     * if index count is larger and we expect repeated vertices, suggest upload.
 642     */
 643    nv50->vbo_push_hint = /* the 64 is heuristic */
 644       !(info->indexed &&
 645         ((info->max_index - info->min_index + 64) < info->count));
 646
 647    nv50->vbo_min_index = info->min_index;
 648    nv50->vbo_max_index = info->max_index;
 649
 650    if (nv50->vbo_push_hint != !!nv50->vbo_fifo)
 651       nv50->dirty |= NV50_NEW_ARRAYS;
 652
 653    if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_VERTEX | NV50_NEW_ARRAYS)))
 654       nv50_update_user_vbufs(nv50);
 655
 656    nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
 657
 658    chan->flush_notify = nv50_draw_vbo_flush_notify;
 659
 660    if (nv50->vbo_fifo) {
 661       nv50_push_vbo(nv50, info);
 662       chan->flush_notify = nv50_default_flush_notify;
 663       return;
 664    }
 665
 666    if (nv50->state.instance_base != info->start_instance) {
 667       nv50->state.instance_base = info->start_instance;
 668       /* NOTE: this does not affect the shader input, should it ? */
 669       BEGIN_RING(chan, RING_3D(VB_INSTANCE_BASE), 1);
 670       OUT_RING  (chan, info->start_instance);
 671    }
 672
 673    if (nv50->base.vbo_dirty) {
 674       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 1);
 675       OUT_RING  (chan, 0);
 676       nv50->base.vbo_dirty = FALSE;
 677    }
 678
 679    if (!info->indexed) {
 680       nv50_draw_arrays(nv50,
 681                        info->mode, info->start, info->count,
 682                        info->instance_count);
 683    } else {
 684       boolean shorten = info->max_index <= 65535;
 685
 686       assert(nv50->idxbuf.buffer);
 687
 688       if (info->primitive_restart != nv50->state.prim_restart) {
 689          if (info->primitive_restart) {
 690             BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 2);
 691             OUT_RING  (chan, 1);
 692             OUT_RING  (chan, info->restart_index);
 693
 694             if (info->restart_index > 65535)
 695                shorten = FALSE;
 696          } else {
 697             BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 1);
 698             OUT_RING  (chan, 0);
 699          }
 700          nv50->state.prim_restart = info->primitive_restart;
 701       } else
 702       if (info->primitive_restart) {
 703          BEGIN_RING(chan, RING_3D(PRIM_RESTART_INDEX), 1);
 704          OUT_RING  (chan, info->restart_index);
 705
 706          if (info->restart_index > 65535)
 707             shorten = FALSE;
 708       }
 709
 710       nv50_draw_elements(nv50, shorten,
 711                          info->mode, info->start, info->count,
 712                          info->instance_count, info->index_bias);
 713    }
 714    chan->flush_notify = nv50_default_flush_notify;
 715
 716    nv50_release_user_vbufs(nv50);
 717 }