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nv50: move magic 0x142c stuff to after state emission
[mesa.git] / src / gallium / drivers / nv50 / nv50_vbo.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
27
28 #include "nv50_context.h"
29
30 static boolean
31 nv50_push_elements_u08(struct nv50_context *, uint8_t *, unsigned);
32
33 static boolean
34 nv50_push_elements_u16(struct nv50_context *, uint16_t *, unsigned);
35
36 static boolean
37 nv50_push_elements_u32(struct nv50_context *, uint32_t *, unsigned);
38
39 static boolean
40 nv50_push_arrays(struct nv50_context *, unsigned, unsigned);
41
42 #define NV50_USING_LOATHED_EDGEFLAG(ctx) ((ctx)->vertprog->cfg.edgeflag_in < 16)
43
44 static INLINE unsigned
45 nv50_prim(unsigned mode)
46 {
47 switch (mode) {
48 case PIPE_PRIM_POINTS: return NV50TCL_VERTEX_BEGIN_POINTS;
49 case PIPE_PRIM_LINES: return NV50TCL_VERTEX_BEGIN_LINES;
50 case PIPE_PRIM_LINE_LOOP: return NV50TCL_VERTEX_BEGIN_LINE_LOOP;
51 case PIPE_PRIM_LINE_STRIP: return NV50TCL_VERTEX_BEGIN_LINE_STRIP;
52 case PIPE_PRIM_TRIANGLES: return NV50TCL_VERTEX_BEGIN_TRIANGLES;
53 case PIPE_PRIM_TRIANGLE_STRIP:
54 return NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP;
55 case PIPE_PRIM_TRIANGLE_FAN: return NV50TCL_VERTEX_BEGIN_TRIANGLE_FAN;
56 case PIPE_PRIM_QUADS: return NV50TCL_VERTEX_BEGIN_QUADS;
57 case PIPE_PRIM_QUAD_STRIP: return NV50TCL_VERTEX_BEGIN_QUAD_STRIP;
58 case PIPE_PRIM_POLYGON: return NV50TCL_VERTEX_BEGIN_POLYGON;
59 case PIPE_PRIM_LINES_ADJACENCY:
60 return NV50TCL_VERTEX_BEGIN_LINES_ADJACENCY;
61 case PIPE_PRIM_LINE_STRIP_ADJACENCY:
62 return NV50TCL_VERTEX_BEGIN_LINE_STRIP_ADJACENCY;
63 case PIPE_PRIM_TRIANGLES_ADJACENCY:
64 return NV50TCL_VERTEX_BEGIN_TRIANGLES_ADJACENCY;
65 case PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY:
66 return NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP_ADJACENCY;
67 default:
68 break;
69 }
70
71 NOUVEAU_ERR("invalid primitive type %d\n", mode);
72 return NV50TCL_VERTEX_BEGIN_POINTS;
73 }
74
75 static INLINE uint32_t
76 nv50_vbo_type_to_hw(enum pipe_format format)
77 {
78 const struct util_format_description *desc;
79
80 desc = util_format_description(format);
81 assert(desc);
82
83 switch (desc->channel[0].type) {
84 case UTIL_FORMAT_TYPE_FLOAT:
85 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT;
86 case UTIL_FORMAT_TYPE_UNSIGNED:
87 if (desc->channel[0].normalized) {
88 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UNORM;
89 }
90 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_USCALED;
91 case UTIL_FORMAT_TYPE_SIGNED:
92 if (desc->channel[0].normalized) {
93 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SNORM;
94 }
95 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SSCALED;
96 /*
97 case PIPE_FORMAT_TYPE_UINT:
98 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UINT;
99 case PIPE_FORMAT_TYPE_SINT:
100 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SINT; */
101 default:
102 return 0;
103 }
104 }
105
106 static INLINE uint32_t
107 nv50_vbo_size_to_hw(unsigned size, unsigned nr_c)
108 {
109 static const uint32_t hw_values[] = {
110 0, 0, 0, 0,
111 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8,
112 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8,
113 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8,
114 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8_8,
115 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16,
116 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16,
117 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16,
118 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16_16,
119 0, 0, 0, 0,
120 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32,
121 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32,
122 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32,
123 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 };
124
125 /* we'd also have R11G11B10 and R10G10B10A2 */
126
127 assert(nr_c > 0 && nr_c <= 4);
128
129 if (size > 32)
130 return 0;
131 size >>= (3 - 2);
132
133 return hw_values[size + (nr_c - 1)];
134 }
135
136 static INLINE uint32_t
137 nv50_vbo_vtxelt_to_hw(struct pipe_vertex_element *ve)
138 {
139 uint32_t hw_type, hw_size;
140 enum pipe_format pf = ve->src_format;
141 const struct util_format_description *desc;
142 unsigned size, nr_components;
143
144 desc = util_format_description(pf);
145 assert(desc);
146
147 size = util_format_get_component_bits(pf, UTIL_FORMAT_COLORSPACE_RGB, 0);
148 nr_components = util_format_get_nr_components(pf);
149
150 hw_type = nv50_vbo_type_to_hw(pf);
151 hw_size = nv50_vbo_size_to_hw(size, nr_components);
152
153 if (!hw_type || !hw_size) {
154 NOUVEAU_ERR("unsupported vbo format: %s\n", util_format_name(pf));
155 abort();
156 return 0x24e80000;
157 }
158
159 if (desc->swizzle[0] == UTIL_FORMAT_SWIZZLE_Z) /* BGRA */
160 hw_size |= (1 << 31); /* no real swizzle bits :-( */
161
162 return (hw_type | hw_size);
163 }
164
165 /* For instanced drawing from user buffers, hitting the FIFO repeatedly
166 * with the same vertex data is probably worse than uploading all data.
167 */
168 static boolean
169 nv50_upload_vtxbuf(struct nv50_context *nv50, unsigned i)
170 {
171 struct nv50_screen *nscreen = nv50->screen;
172 struct pipe_screen *pscreen = &nscreen->base.base;
173 struct pipe_buffer *buf = nscreen->strm_vbuf[i];
174 struct pipe_vertex_buffer *vb = &nv50->vtxbuf[i];
175 uint8_t *src;
176 unsigned size = align(vb->buffer->size, 4096);
177
178 if (buf && buf->size < size)
179 pipe_buffer_reference(&nscreen->strm_vbuf[i], NULL);
180
181 if (!nscreen->strm_vbuf[i]) {
182 nscreen->strm_vbuf[i] = pipe_buffer_create(
183 pscreen, 0, PIPE_BUFFER_USAGE_VERTEX, size);
184 buf = nscreen->strm_vbuf[i];
185 }
186
187 src = pipe_buffer_map(pscreen, vb->buffer, PIPE_BUFFER_USAGE_CPU_READ);
188 if (!src)
189 return FALSE;
190 src += vb->buffer_offset;
191
192 size = (vb->max_index + 1) * vb->stride + 16; /* + 16 is for stride 0 */
193 if (vb->buffer_offset + size > vb->buffer->size)
194 size = vb->buffer->size - vb->buffer_offset;
195
196 pipe_buffer_write(pscreen, buf, vb->buffer_offset, size, src);
197 pipe_buffer_unmap(pscreen, vb->buffer);
198
199 vb->buffer = buf; /* don't pipe_reference, this is a private copy */
200 return TRUE;
201 }
202
203 static void
204 nv50_upload_user_vbufs(struct nv50_context *nv50)
205 {
206 unsigned i;
207
208 if (nv50->vbo_fifo)
209 nv50->dirty |= NV50_NEW_ARRAYS;
210 if (!(nv50->dirty & NV50_NEW_ARRAYS))
211 return;
212
213 for (i = 0; i < nv50->vtxbuf_nr; ++i) {
214 if (nv50->vtxbuf[i].buffer->usage & PIPE_BUFFER_USAGE_VERTEX)
215 continue;
216 nv50_upload_vtxbuf(nv50, i);
217 }
218 }
219
220 static void
221 nv50_set_static_vtxattr(struct nv50_context *nv50, unsigned i, void *data)
222 {
223 struct nouveau_grobj *tesla = nv50->screen->tesla;
224 struct nouveau_channel *chan = tesla->channel;
225 float v[4];
226 enum pipe_format pf = nv50->vtxelt->pipe[i].src_format;
227 unsigned nr_components = util_format_get_nr_components(pf);
228
229 util_format_read_4f(pf, v, 0, data, 0, 0, 0, 1, 1);
230
231 switch (nr_components) {
232 case 4:
233 BEGIN_RING(chan, tesla, NV50TCL_VTX_ATTR_4F_X(i), 4);
234 OUT_RINGf (chan, v[0]);
235 OUT_RINGf (chan, v[1]);
236 OUT_RINGf (chan, v[2]);
237 OUT_RINGf (chan, v[3]);
238 break;
239 case 3:
240 BEGIN_RING(chan, tesla, NV50TCL_VTX_ATTR_3F_X(i), 3);
241 OUT_RINGf (chan, v[0]);
242 OUT_RINGf (chan, v[1]);
243 OUT_RINGf (chan, v[2]);
244 break;
245 case 2:
246 BEGIN_RING(chan, tesla, NV50TCL_VTX_ATTR_2F_X(i), 2);
247 OUT_RINGf (chan, v[0]);
248 OUT_RINGf (chan, v[1]);
249 break;
250 case 1:
251 BEGIN_RING(chan, tesla, NV50TCL_VTX_ATTR_1F(i), 1);
252 OUT_RINGf (chan, v[0]);
253 break;
254 default:
255 assert(0);
256 break;
257 }
258 }
259
260 static unsigned
261 init_per_instance_arrays_immd(struct nv50_context *nv50,
262 unsigned startInstance,
263 unsigned pos[16], unsigned step[16])
264 {
265 struct nouveau_bo *bo;
266 unsigned i, b, count = 0;
267
268 for (i = 0; i < nv50->vtxelt->num_elements; ++i) {
269 if (!nv50->vtxelt->pipe[i].instance_divisor)
270 continue;
271 ++count;
272 b = nv50->vtxelt->pipe[i].vertex_buffer_index;
273
274 pos[i] = nv50->vtxelt->pipe[i].src_offset +
275 nv50->vtxbuf[b].buffer_offset +
276 startInstance * nv50->vtxbuf[b].stride;
277 step[i] = startInstance %
278 nv50->vtxelt->pipe[i].instance_divisor;
279
280 bo = nouveau_bo(nv50->vtxbuf[b].buffer);
281 if (!bo->map)
282 nouveau_bo_map(bo, NOUVEAU_BO_RD);
283
284 nv50_set_static_vtxattr(nv50, i, (uint8_t *)bo->map + pos[i]);
285 }
286
287 return count;
288 }
289
290 static unsigned
291 init_per_instance_arrays(struct nv50_context *nv50,
292 unsigned startInstance,
293 unsigned pos[16], unsigned step[16])
294 {
295 struct nouveau_grobj *tesla = nv50->screen->tesla;
296 struct nouveau_channel *chan = tesla->channel;
297 struct nouveau_bo *bo;
298 struct nouveau_stateobj *so;
299 unsigned i, b, count = 0, num_elements = nv50->vtxelt->num_elements;
300 const uint32_t rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
301
302 if (nv50->vbo_fifo)
303 return init_per_instance_arrays_immd(nv50, startInstance,
304 pos, step);
305
306 so = so_new(num_elements, num_elements * 2, num_elements * 2);
307
308 for (i = 0; i < nv50->vtxelt->num_elements; ++i) {
309 if (!nv50->vtxelt->pipe[i].instance_divisor)
310 continue;
311 ++count;
312 b = nv50->vtxelt->pipe[i].vertex_buffer_index;
313
314 pos[i] = nv50->vtxelt->pipe[i].src_offset +
315 nv50->vtxbuf[b].buffer_offset +
316 startInstance * nv50->vtxbuf[b].stride;
317
318 if (!startInstance) {
319 step[i] = 0;
320 continue;
321 }
322 step[i] = startInstance %
323 nv50->vtxelt->pipe[i].instance_divisor;
324
325 bo = nouveau_bo(nv50->vtxbuf[b].buffer);
326
327 so_method(so, tesla, NV50TCL_VERTEX_ARRAY_START_HIGH(i), 2);
328 so_reloc (so, bo, pos[i], rl | NOUVEAU_BO_HIGH, 0, 0);
329 so_reloc (so, bo, pos[i], rl | NOUVEAU_BO_LOW, 0, 0);
330 }
331
332 if (count && startInstance) {
333 so_ref (so, &nv50->state.instbuf); /* for flush notify */
334 so_emit(chan, nv50->state.instbuf);
335 }
336 so_ref (NULL, &so);
337
338 return count;
339 }
340
341 static void
342 step_per_instance_arrays_immd(struct nv50_context *nv50,
343 unsigned pos[16], unsigned step[16])
344 {
345 struct nouveau_bo *bo;
346 unsigned i, b;
347
348 for (i = 0; i < nv50->vtxelt->num_elements; ++i) {
349 if (!nv50->vtxelt->pipe[i].instance_divisor)
350 continue;
351 if (++step[i] != nv50->vtxelt->pipe[i].instance_divisor)
352 continue;
353 b = nv50->vtxelt->pipe[i].vertex_buffer_index;
354 bo = nouveau_bo(nv50->vtxbuf[b].buffer);
355
356 step[i] = 0;
357 pos[i] += nv50->vtxbuf[b].stride;
358
359 nv50_set_static_vtxattr(nv50, i, (uint8_t *)bo->map + pos[i]);
360 }
361 }
362
363 static void
364 step_per_instance_arrays(struct nv50_context *nv50,
365 unsigned pos[16], unsigned step[16])
366 {
367 struct nouveau_grobj *tesla = nv50->screen->tesla;
368 struct nouveau_channel *chan = tesla->channel;
369 struct nouveau_bo *bo;
370 struct nouveau_stateobj *so;
371 unsigned i, b, num_elements = nv50->vtxelt->num_elements;
372 const uint32_t rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
373
374 if (nv50->vbo_fifo) {
375 step_per_instance_arrays_immd(nv50, pos, step);
376 return;
377 }
378
379 so = so_new(num_elements, num_elements * 2, num_elements * 2);
380
381 for (i = 0; i < nv50->vtxelt->num_elements; ++i) {
382 if (!nv50->vtxelt->pipe[i].instance_divisor)
383 continue;
384 b = nv50->vtxelt->pipe[i].vertex_buffer_index;
385
386 if (++step[i] == nv50->vtxelt->pipe[i].instance_divisor) {
387 step[i] = 0;
388 pos[i] += nv50->vtxbuf[b].stride;
389 }
390
391 bo = nouveau_bo(nv50->vtxbuf[b].buffer);
392
393 so_method(so, tesla, NV50TCL_VERTEX_ARRAY_START_HIGH(i), 2);
394 so_reloc (so, bo, pos[i], rl | NOUVEAU_BO_HIGH, 0, 0);
395 so_reloc (so, bo, pos[i], rl | NOUVEAU_BO_LOW, 0, 0);
396 }
397
398 so_ref (so, &nv50->state.instbuf); /* for flush notify */
399 so_ref (NULL, &so);
400
401 so_emit(chan, nv50->state.instbuf);
402 }
403
404 static INLINE void
405 nv50_unmap_vbufs(struct nv50_context *nv50)
406 {
407 unsigned i;
408
409 for (i = 0; i < nv50->vtxbuf_nr; ++i)
410 if (nouveau_bo(nv50->vtxbuf[i].buffer)->map)
411 nouveau_bo_unmap(nouveau_bo(nv50->vtxbuf[i].buffer));
412 }
413
414 void
415 nv50_draw_arrays_instanced(struct pipe_context *pipe,
416 unsigned mode, unsigned start, unsigned count,
417 unsigned startInstance, unsigned instanceCount)
418 {
419 struct nv50_context *nv50 = nv50_context(pipe);
420 struct nouveau_channel *chan = nv50->screen->tesla->channel;
421 struct nouveau_grobj *tesla = nv50->screen->tesla;
422 unsigned i, nz_divisors;
423 unsigned step[16], pos[16];
424
425 if (!NV50_USING_LOATHED_EDGEFLAG(nv50))
426 nv50_upload_user_vbufs(nv50);
427
428 if (!nv50_state_validate(nv50, 0))
429 return;
430 chan->flush_notify = nv50_state_flush_notify;
431
432 nz_divisors = init_per_instance_arrays(nv50, startInstance, pos, step);
433
434 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 2);
435 OUT_RING (chan, NV50_CB_AUX | (24 << 8));
436 OUT_RING (chan, startInstance);
437
438 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
439 OUT_RING (chan, nv50_prim(mode));
440
441 if (nv50->vbo_fifo)
442 nv50_push_arrays(nv50, start, count);
443 else {
444 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BUFFER_FIRST, 2);
445 OUT_RING (chan, start);
446 OUT_RING (chan, count);
447 }
448 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
449 OUT_RING (chan, 0);
450
451 for (i = 1; i < instanceCount; i++) {
452 if (nz_divisors) /* any non-zero array divisors ? */
453 step_per_instance_arrays(nv50, pos, step);
454
455 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
456 OUT_RING (chan, nv50_prim(mode) | (1 << 28));
457
458 if (nv50->vbo_fifo)
459 nv50_push_arrays(nv50, start, count);
460 else {
461 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BUFFER_FIRST, 2);
462 OUT_RING (chan, start);
463 OUT_RING (chan, count);
464 }
465 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
466 OUT_RING (chan, 0);
467 }
468
469 chan->flush_notify = NULL;
470 nv50_unmap_vbufs(nv50);
471
472 so_ref(NULL, &nv50->state.instbuf);
473 }
474
475 void
476 nv50_draw_arrays(struct pipe_context *pipe, unsigned mode, unsigned start,
477 unsigned count)
478 {
479 struct nv50_context *nv50 = nv50_context(pipe);
480 struct nouveau_channel *chan = nv50->screen->tesla->channel;
481 struct nouveau_grobj *tesla = nv50->screen->tesla;
482 boolean ret;
483
484 if (!nv50_state_validate(nv50, 11))
485 return;
486 chan->flush_notify = nv50_state_flush_notify;
487
488 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
489 OUT_RING (chan, nv50_prim(mode));
490
491 if (nv50->vbo_fifo)
492 ret = nv50_push_arrays(nv50, start, count);
493 else {
494 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BUFFER_FIRST, 2);
495 OUT_RING (chan, start);
496 OUT_RING (chan, count);
497 ret = TRUE;
498 }
499 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
500 OUT_RING (chan, 0);
501
502 chan->flush_notify = NULL;
503 nv50_unmap_vbufs(nv50);
504
505 /* XXX: not sure what to do if ret != TRUE: flush and retry?
506 */
507 assert(ret);
508 }
509
510 static INLINE boolean
511 nv50_draw_elements_inline_u08(struct nv50_context *nv50, uint8_t *map,
512 unsigned start, unsigned count)
513 {
514 struct nouveau_channel *chan = nv50->screen->tesla->channel;
515 struct nouveau_grobj *tesla = nv50->screen->tesla;
516
517 map += start;
518
519 if (nv50->vbo_fifo)
520 return nv50_push_elements_u08(nv50, map, count);
521
522 if (count & 1) {
523 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U32, 1);
524 OUT_RING (chan, map[0]);
525 map++;
526 count--;
527 }
528
529 while (count) {
530 unsigned nr = count > 2046 ? 2046 : count;
531 int i;
532
533 BEGIN_RING_NI(chan, tesla, NV50TCL_VB_ELEMENT_U16, nr >> 1);
534 for (i = 0; i < nr; i += 2)
535 OUT_RING (chan, (map[i + 1] << 16) | map[i]);
536
537 count -= nr;
538 map += nr;
539 }
540 return TRUE;
541 }
542
543 static INLINE boolean
544 nv50_draw_elements_inline_u16(struct nv50_context *nv50, uint16_t *map,
545 unsigned start, unsigned count)
546 {
547 struct nouveau_channel *chan = nv50->screen->tesla->channel;
548 struct nouveau_grobj *tesla = nv50->screen->tesla;
549
550 map += start;
551
552 if (nv50->vbo_fifo)
553 return nv50_push_elements_u16(nv50, map, count);
554
555 if (count & 1) {
556 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U32, 1);
557 OUT_RING (chan, map[0]);
558 map++;
559 count--;
560 }
561
562 while (count) {
563 unsigned nr = count > 2046 ? 2046 : count;
564 int i;
565
566 BEGIN_RING_NI(chan, tesla, NV50TCL_VB_ELEMENT_U16, nr >> 1);
567 for (i = 0; i < nr; i += 2)
568 OUT_RING (chan, (map[i + 1] << 16) | map[i]);
569
570 count -= nr;
571 map += nr;
572 }
573 return TRUE;
574 }
575
576 static INLINE boolean
577 nv50_draw_elements_inline_u32(struct nv50_context *nv50, uint32_t *map,
578 unsigned start, unsigned count)
579 {
580 struct nouveau_channel *chan = nv50->screen->tesla->channel;
581 struct nouveau_grobj *tesla = nv50->screen->tesla;
582
583 map += start;
584
585 if (nv50->vbo_fifo)
586 return nv50_push_elements_u32(nv50, map, count);
587
588 while (count) {
589 unsigned nr = count > 2047 ? 2047 : count;
590
591 BEGIN_RING_NI(chan, tesla, NV50TCL_VB_ELEMENT_U32, nr);
592 OUT_RINGp (chan, map, nr);
593
594 count -= nr;
595 map += nr;
596 }
597 return TRUE;
598 }
599
600 static INLINE void
601 nv50_draw_elements_inline(struct nv50_context *nv50,
602 void *map, unsigned indexSize,
603 unsigned start, unsigned count)
604 {
605 switch (indexSize) {
606 case 1:
607 nv50_draw_elements_inline_u08(nv50, map, start, count);
608 break;
609 case 2:
610 nv50_draw_elements_inline_u16(nv50, map, start, count);
611 break;
612 case 4:
613 nv50_draw_elements_inline_u32(nv50, map, start, count);
614 break;
615 }
616 }
617
618 void
619 nv50_draw_elements_instanced(struct pipe_context *pipe,
620 struct pipe_buffer *indexBuffer,
621 unsigned indexSize,
622 unsigned mode, unsigned start, unsigned count,
623 unsigned startInstance, unsigned instanceCount)
624 {
625 struct nv50_context *nv50 = nv50_context(pipe);
626 struct nouveau_grobj *tesla = nv50->screen->tesla;
627 struct nouveau_channel *chan = tesla->channel;
628 struct pipe_screen *pscreen = pipe->screen;
629 void *map;
630 unsigned i, nz_divisors;
631 unsigned step[16], pos[16];
632
633 map = pipe_buffer_map(pscreen, indexBuffer, PIPE_BUFFER_USAGE_CPU_READ);
634
635 if (!NV50_USING_LOATHED_EDGEFLAG(nv50))
636 nv50_upload_user_vbufs(nv50);
637
638 if (!nv50_state_validate(nv50, 0))
639 return;
640 chan->flush_notify = nv50_state_flush_notify;
641
642 nz_divisors = init_per_instance_arrays(nv50, startInstance, pos, step);
643
644 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 2);
645 OUT_RING (chan, NV50_CB_AUX | (24 << 8));
646 OUT_RING (chan, startInstance);
647
648 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
649 OUT_RING (chan, nv50_prim(mode));
650
651 nv50_draw_elements_inline(nv50, map, indexSize, start, count);
652
653 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
654 OUT_RING (chan, 0);
655
656 for (i = 1; i < instanceCount; ++i) {
657 if (nz_divisors) /* any non-zero array divisors ? */
658 step_per_instance_arrays(nv50, pos, step);
659
660 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
661 OUT_RING (chan, nv50_prim(mode) | (1 << 28));
662
663 nv50_draw_elements_inline(nv50, map, indexSize, start, count);
664
665 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
666 OUT_RING (chan, 0);
667 }
668
669 chan->flush_notify = NULL;
670 nv50_unmap_vbufs(nv50);
671
672 so_ref(NULL, &nv50->state.instbuf);
673 }
674
675 void
676 nv50_draw_elements(struct pipe_context *pipe,
677 struct pipe_buffer *indexBuffer, unsigned indexSize,
678 unsigned mode, unsigned start, unsigned count)
679 {
680 struct nv50_context *nv50 = nv50_context(pipe);
681 struct nouveau_channel *chan = nv50->screen->tesla->channel;
682 struct nouveau_grobj *tesla = nv50->screen->tesla;
683 struct pipe_screen *pscreen = pipe->screen;
684 void *map;
685
686 if (!nv50_state_validate(nv50, 14))
687 return;
688 chan->flush_notify = nv50_state_flush_notify;
689
690 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_BEGIN, 1);
691 OUT_RING (chan, nv50_prim(mode));
692
693 if (!nv50->vbo_fifo && indexSize == 4) {
694 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U32 | 0x30000, 0);
695 OUT_RING (chan, count);
696 nouveau_pushbuf_submit(chan, nouveau_bo(indexBuffer),
697 start << 2, count << 2);
698 } else
699 if (!nv50->vbo_fifo && indexSize == 2) {
700 unsigned vb_start = (start & ~1);
701 unsigned vb_end = (start + count + 1) & ~1;
702 unsigned dwords = (vb_end - vb_start) >> 1;
703
704 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U16_SETUP, 1);
705 OUT_RING (chan, ((start & 1) << 31) | count);
706 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U16 | 0x30000, 0);
707 OUT_RING (chan, dwords);
708 nouveau_pushbuf_submit(chan, nouveau_bo(indexBuffer),
709 vb_start << 1, dwords << 2);
710 BEGIN_RING(chan, tesla, NV50TCL_VB_ELEMENT_U16_SETUP, 1);
711 OUT_RING (chan, 0);
712 } else {
713 map = pipe_buffer_map(pscreen, indexBuffer,
714 PIPE_BUFFER_USAGE_CPU_READ);
715 nv50_draw_elements_inline(nv50, map, indexSize, start, count);
716 nv50_unmap_vbufs(nv50);
717 pipe_buffer_unmap(pscreen, indexBuffer);
718 }
719
720 BEGIN_RING(chan, tesla, NV50TCL_VERTEX_END, 1);
721 OUT_RING (chan, 0);
722 chan->flush_notify = NULL;
723 }
724
725 static INLINE boolean
726 nv50_vbo_static_attrib(struct nv50_context *nv50, unsigned attrib,
727 struct nouveau_stateobj **pso,
728 struct pipe_vertex_element *ve,
729 struct pipe_vertex_buffer *vb)
730
731 {
732 struct nouveau_stateobj *so;
733 struct nouveau_grobj *tesla = nv50->screen->tesla;
734 struct nouveau_bo *bo = nouveau_bo(vb->buffer);
735 float v[4];
736 int ret;
737 unsigned nr_components = util_format_get_nr_components(ve->src_format);
738
739 ret = nouveau_bo_map(bo, NOUVEAU_BO_RD);
740 if (ret)
741 return FALSE;
742
743 util_format_read_4f(ve->src_format, v, 0, (uint8_t *)bo->map +
744 (vb->buffer_offset + ve->src_offset), 0,
745 0, 0, 1, 1);
746 so = *pso;
747 if (!so)
748 *pso = so = so_new(nv50->vtxelt->num_elements,
749 nv50->vtxelt->num_elements * 4, 0);
750
751 switch (nr_components) {
752 case 4:
753 so_method(so, tesla, NV50TCL_VTX_ATTR_4F_X(attrib), 4);
754 so_data (so, fui(v[0]));
755 so_data (so, fui(v[1]));
756 so_data (so, fui(v[2]));
757 so_data (so, fui(v[3]));
758 break;
759 case 3:
760 so_method(so, tesla, NV50TCL_VTX_ATTR_3F_X(attrib), 3);
761 so_data (so, fui(v[0]));
762 so_data (so, fui(v[1]));
763 so_data (so, fui(v[2]));
764 break;
765 case 2:
766 so_method(so, tesla, NV50TCL_VTX_ATTR_2F_X(attrib), 2);
767 so_data (so, fui(v[0]));
768 so_data (so, fui(v[1]));
769 break;
770 case 1:
771 if (attrib == nv50->vertprog->cfg.edgeflag_in) {
772 so_method(so, tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
773 so_data (so, v[0] ? 1 : 0);
774 }
775 so_method(so, tesla, NV50TCL_VTX_ATTR_1F(attrib), 1);
776 so_data (so, fui(v[0]));
777 break;
778 default:
779 nouveau_bo_unmap(bo);
780 return FALSE;
781 }
782
783 nouveau_bo_unmap(bo);
784 return TRUE;
785 }
786
787 void
788 nv50_vtxelt_construct(struct nv50_vtxelt_stateobj *cso)
789 {
790 unsigned i;
791
792 for (i = 0; i < cso->num_elements; ++i) {
793 struct pipe_vertex_element *ve = &cso->pipe[i];
794
795 cso->hw[i] = nv50_vbo_vtxelt_to_hw(ve);
796 }
797 }
798
799 struct nouveau_stateobj *
800 nv50_vbo_validate(struct nv50_context *nv50)
801 {
802 struct nouveau_grobj *tesla = nv50->screen->tesla;
803 struct nouveau_stateobj *vtxbuf, *vtxfmt, *vtxattr;
804 unsigned i, n_ve;
805
806 /* don't validate if Gallium took away our buffers */
807 if (nv50->vtxbuf_nr == 0)
808 return NULL;
809 nv50->vbo_fifo = 0;
810
811 for (i = 0; i < nv50->vtxbuf_nr; ++i)
812 if (nv50->vtxbuf[i].stride &&
813 !(nv50->vtxbuf[i].buffer->usage & PIPE_BUFFER_USAGE_VERTEX))
814 nv50->vbo_fifo = 0xffff;
815
816 if (NV50_USING_LOATHED_EDGEFLAG(nv50))
817 nv50->vbo_fifo = 0xffff; /* vertprog can't set edgeflag */
818
819 n_ve = MAX2(nv50->vtxelt->num_elements, nv50->state.vtxelt_nr);
820
821 vtxattr = NULL;
822 vtxbuf = so_new(n_ve * 2, n_ve * 5, nv50->vtxelt->num_elements * 4);
823 vtxfmt = so_new(1, n_ve, 0);
824 so_method(vtxfmt, tesla, NV50TCL_VERTEX_ARRAY_ATTRIB(0), n_ve);
825
826 for (i = 0; i < nv50->vtxelt->num_elements; i++) {
827 struct pipe_vertex_element *ve = &nv50->vtxelt->pipe[i];
828 struct pipe_vertex_buffer *vb =
829 &nv50->vtxbuf[ve->vertex_buffer_index];
830 struct nouveau_bo *bo = nouveau_bo(vb->buffer);
831 uint32_t hw = nv50->vtxelt->hw[i];
832
833 if (!vb->stride &&
834 nv50_vbo_static_attrib(nv50, i, &vtxattr, ve, vb)) {
835 so_data(vtxfmt, hw | (1 << 4));
836
837 so_method(vtxbuf, tesla,
838 NV50TCL_VERTEX_ARRAY_FORMAT(i), 1);
839 so_data (vtxbuf, 0);
840
841 nv50->vbo_fifo &= ~(1 << i);
842 continue;
843 }
844
845 if (nv50->vbo_fifo) {
846 so_data (vtxfmt, hw |
847 (ve->instance_divisor ? (1 << 4) : i));
848 so_method(vtxbuf, tesla,
849 NV50TCL_VERTEX_ARRAY_FORMAT(i), 1);
850 so_data (vtxbuf, 0);
851 continue;
852 }
853 so_data(vtxfmt, hw | i);
854
855 so_method(vtxbuf, tesla, NV50TCL_VERTEX_ARRAY_FORMAT(i), 3);
856 so_data (vtxbuf, 0x20000000 |
857 (ve->instance_divisor ? 0 : vb->stride));
858 so_reloc (vtxbuf, bo, vb->buffer_offset +
859 ve->src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
860 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
861 so_reloc (vtxbuf, bo, vb->buffer_offset +
862 ve->src_offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART |
863 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
864
865 /* vertex array limits */
866 so_method(vtxbuf, tesla, NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
867 so_reloc (vtxbuf, bo, vb->buffer->size - 1,
868 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
869 NOUVEAU_BO_HIGH, 0, 0);
870 so_reloc (vtxbuf, bo, vb->buffer->size - 1,
871 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD |
872 NOUVEAU_BO_LOW, 0, 0);
873 }
874 for (; i < n_ve; ++i) {
875 so_data (vtxfmt, 0x7e080010);
876
877 so_method(vtxbuf, tesla, NV50TCL_VERTEX_ARRAY_FORMAT(i), 1);
878 so_data (vtxbuf, 0);
879 }
880 nv50->state.vtxelt_nr = nv50->vtxelt->num_elements;
881
882 so_ref (vtxbuf, &nv50->state.vtxbuf);
883 so_ref (vtxattr, &nv50->state.vtxattr);
884 so_ref (NULL, &vtxbuf);
885 so_ref (NULL, &vtxattr);
886 return vtxfmt;
887 }
888
889 typedef void (*pfn_push)(struct nouveau_channel *, void *);
890
891 struct nv50_vbo_emitctx
892 {
893 pfn_push push[16];
894 uint8_t *map[16];
895 unsigned stride[16];
896 unsigned nr_ve;
897 unsigned vtx_dwords;
898 unsigned vtx_max;
899
900 float edgeflag;
901 unsigned ve_edgeflag;
902 };
903
904 static INLINE void
905 emit_vtx_next(struct nouveau_channel *chan, struct nv50_vbo_emitctx *emit)
906 {
907 unsigned i;
908
909 for (i = 0; i < emit->nr_ve; ++i) {
910 emit->push[i](chan, emit->map[i]);
911 emit->map[i] += emit->stride[i];
912 }
913 }
914
915 static INLINE void
916 emit_vtx(struct nouveau_channel *chan, struct nv50_vbo_emitctx *emit,
917 uint32_t vi)
918 {
919 unsigned i;
920
921 for (i = 0; i < emit->nr_ve; ++i)
922 emit->push[i](chan, emit->map[i] + emit->stride[i] * vi);
923 }
924
925 static INLINE boolean
926 nv50_map_vbufs(struct nv50_context *nv50)
927 {
928 int i;
929
930 for (i = 0; i < nv50->vtxbuf_nr; ++i) {
931 struct pipe_vertex_buffer *vb = &nv50->vtxbuf[i];
932 unsigned size = vb->stride * (vb->max_index + 1) + 16;
933
934 if (nouveau_bo(vb->buffer)->map)
935 continue;
936
937 size = vb->stride * (vb->max_index + 1) + 16;
938 size = MIN2(size, vb->buffer->size);
939 if (!size)
940 size = vb->buffer->size;
941
942 if (nouveau_bo_map_range(nouveau_bo(vb->buffer),
943 0, size, NOUVEAU_BO_RD))
944 break;
945 }
946
947 if (i == nv50->vtxbuf_nr)
948 return TRUE;
949 for (; i >= 0; --i)
950 nouveau_bo_unmap(nouveau_bo(nv50->vtxbuf[i].buffer));
951 return FALSE;
952 }
953
954 static void
955 emit_b32_1(struct nouveau_channel *chan, void *data)
956 {
957 uint32_t *v = data;
958
959 OUT_RING(chan, v[0]);
960 }
961
962 static void
963 emit_b32_2(struct nouveau_channel *chan, void *data)
964 {
965 uint32_t *v = data;
966
967 OUT_RING(chan, v[0]);
968 OUT_RING(chan, v[1]);
969 }
970
971 static void
972 emit_b32_3(struct nouveau_channel *chan, void *data)
973 {
974 uint32_t *v = data;
975
976 OUT_RING(chan, v[0]);
977 OUT_RING(chan, v[1]);
978 OUT_RING(chan, v[2]);
979 }
980
981 static void
982 emit_b32_4(struct nouveau_channel *chan, void *data)
983 {
984 uint32_t *v = data;
985
986 OUT_RING(chan, v[0]);
987 OUT_RING(chan, v[1]);
988 OUT_RING(chan, v[2]);
989 OUT_RING(chan, v[3]);
990 }
991
992 static void
993 emit_b16_1(struct nouveau_channel *chan, void *data)
994 {
995 uint16_t *v = data;
996
997 OUT_RING(chan, v[0]);
998 }
999
1000 static void
1001 emit_b16_3(struct nouveau_channel *chan, void *data)
1002 {
1003 uint16_t *v = data;
1004
1005 OUT_RING(chan, (v[1] << 16) | v[0]);
1006 OUT_RING(chan, v[2]);
1007 }
1008
1009 static void
1010 emit_b08_1(struct nouveau_channel *chan, void *data)
1011 {
1012 uint8_t *v = data;
1013
1014 OUT_RING(chan, v[0]);
1015 }
1016
1017 static void
1018 emit_b08_3(struct nouveau_channel *chan, void *data)
1019 {
1020 uint8_t *v = data;
1021
1022 OUT_RING(chan, (v[2] << 16) | (v[1] << 8) | v[0]);
1023 }
1024
1025 static boolean
1026 emit_prepare(struct nv50_context *nv50, struct nv50_vbo_emitctx *emit,
1027 unsigned start)
1028 {
1029 unsigned i;
1030
1031 if (nv50_map_vbufs(nv50) == FALSE)
1032 return FALSE;
1033
1034 emit->ve_edgeflag = nv50->vertprog->cfg.edgeflag_in;
1035
1036 emit->edgeflag = 0.5f;
1037 emit->nr_ve = 0;
1038 emit->vtx_dwords = 0;
1039
1040 for (i = 0; i < nv50->vtxelt->num_elements; ++i) {
1041 struct pipe_vertex_element *ve;
1042 struct pipe_vertex_buffer *vb;
1043 unsigned n, size, nr_components;
1044 const struct util_format_description *desc;
1045
1046 ve = &nv50->vtxelt->pipe[i];
1047 vb = &nv50->vtxbuf[ve->vertex_buffer_index];
1048 if (!(nv50->vbo_fifo & (1 << i)) || ve->instance_divisor)
1049 continue;
1050 n = emit->nr_ve++;
1051
1052 emit->stride[n] = vb->stride;
1053 emit->map[n] = (uint8_t *)nouveau_bo(vb->buffer)->map +
1054 vb->buffer_offset +
1055 (start * vb->stride + ve->src_offset);
1056
1057 desc = util_format_description(ve->src_format);
1058 assert(desc);
1059
1060 size = util_format_get_component_bits(
1061 ve->src_format, UTIL_FORMAT_COLORSPACE_RGB, 0);
1062 nr_components = util_format_get_nr_components(ve->src_format);
1063
1064 assert(nr_components > 0 && nr_components <= 4);
1065
1066 /* It shouldn't be necessary to push the implicit 1s
1067 * for case 3 and size 8 cases 1, 2, 3.
1068 */
1069 switch (size) {
1070 default:
1071 NOUVEAU_ERR("unsupported vtxelt size: %u\n", size);
1072 return FALSE;
1073 case 32:
1074 switch (nr_components) {
1075 case 1: emit->push[n] = emit_b32_1; break;
1076 case 2: emit->push[n] = emit_b32_2; break;
1077 case 3: emit->push[n] = emit_b32_3; break;
1078 case 4: emit->push[n] = emit_b32_4; break;
1079 }
1080 emit->vtx_dwords += nr_components;
1081 break;
1082 case 16:
1083 switch (nr_components) {
1084 case 1: emit->push[n] = emit_b16_1; break;
1085 case 2: emit->push[n] = emit_b32_1; break;
1086 case 3: emit->push[n] = emit_b16_3; break;
1087 case 4: emit->push[n] = emit_b32_2; break;
1088 }
1089 emit->vtx_dwords += (nr_components + 1) >> 1;
1090 break;
1091 case 8:
1092 switch (nr_components) {
1093 case 1: emit->push[n] = emit_b08_1; break;
1094 case 2: emit->push[n] = emit_b16_1; break;
1095 case 3: emit->push[n] = emit_b08_3; break;
1096 case 4: emit->push[n] = emit_b32_1; break;
1097 }
1098 emit->vtx_dwords += 1;
1099 break;
1100 }
1101 }
1102
1103 emit->vtx_max = 512 / emit->vtx_dwords;
1104 if (emit->ve_edgeflag < 16)
1105 emit->vtx_max = 1;
1106
1107 return TRUE;
1108 }
1109
1110 static INLINE void
1111 set_edgeflag(struct nouveau_channel *chan,
1112 struct nouveau_grobj *tesla,
1113 struct nv50_vbo_emitctx *emit, uint32_t index)
1114 {
1115 unsigned i = emit->ve_edgeflag;
1116
1117 if (i < 16) {
1118 float f = *((float *)(emit->map[i] + index * emit->stride[i]));
1119
1120 if (emit->edgeflag != f) {
1121 emit->edgeflag = f;
1122
1123 BEGIN_RING(chan, tesla, 0x15e4, 1);
1124 OUT_RING (chan, f ? 1 : 0);
1125 }
1126 }
1127 }
1128
1129 static boolean
1130 nv50_push_arrays(struct nv50_context *nv50, unsigned start, unsigned count)
1131 {
1132 struct nouveau_channel *chan = nv50->screen->base.channel;
1133 struct nouveau_grobj *tesla = nv50->screen->tesla;
1134 struct nv50_vbo_emitctx emit;
1135
1136 if (emit_prepare(nv50, &emit, start) == FALSE)
1137 return FALSE;
1138
1139 while (count) {
1140 unsigned i, dw, nr = MIN2(count, emit.vtx_max);
1141 dw = nr * emit.vtx_dwords;
1142
1143 set_edgeflag(chan, tesla, &emit, 0); /* nr will be 1 */
1144
1145 BEGIN_RING_NI(chan, tesla, NV50TCL_VERTEX_DATA, dw);
1146 for (i = 0; i < nr; ++i)
1147 emit_vtx_next(chan, &emit);
1148
1149 count -= nr;
1150 }
1151
1152 return TRUE;
1153 }
1154
1155 static boolean
1156 nv50_push_elements_u32(struct nv50_context *nv50, uint32_t *map, unsigned count)
1157 {
1158 struct nouveau_channel *chan = nv50->screen->base.channel;
1159 struct nouveau_grobj *tesla = nv50->screen->tesla;
1160 struct nv50_vbo_emitctx emit;
1161
1162 if (emit_prepare(nv50, &emit, 0) == FALSE)
1163 return FALSE;
1164
1165 while (count) {
1166 unsigned i, dw, nr = MIN2(count, emit.vtx_max);
1167 dw = nr * emit.vtx_dwords;
1168
1169 set_edgeflag(chan, tesla, &emit, *map);
1170
1171 BEGIN_RING_NI(chan, tesla, NV50TCL_VERTEX_DATA, dw);
1172 for (i = 0; i < nr; ++i)
1173 emit_vtx(chan, &emit, *map++);
1174
1175 count -= nr;
1176 }
1177
1178 return TRUE;
1179 }
1180
1181 static boolean
1182 nv50_push_elements_u16(struct nv50_context *nv50, uint16_t *map, unsigned count)
1183 {
1184 struct nouveau_channel *chan = nv50->screen->base.channel;
1185 struct nouveau_grobj *tesla = nv50->screen->tesla;
1186 struct nv50_vbo_emitctx emit;
1187
1188 if (emit_prepare(nv50, &emit, 0) == FALSE)
1189 return FALSE;
1190
1191 while (count) {
1192 unsigned i, dw, nr = MIN2(count, emit.vtx_max);
1193 dw = nr * emit.vtx_dwords;
1194
1195 set_edgeflag(chan, tesla, &emit, *map);
1196
1197 BEGIN_RING_NI(chan, tesla, NV50TCL_VERTEX_DATA, dw);
1198 for (i = 0; i < nr; ++i)
1199 emit_vtx(chan, &emit, *map++);
1200
1201 count -= nr;
1202 }
1203
1204 return TRUE;
1205 }
1206
1207 static boolean
1208 nv50_push_elements_u08(struct nv50_context *nv50, uint8_t *map, unsigned count)
1209 {
1210 struct nouveau_channel *chan = nv50->screen->base.channel;
1211 struct nouveau_grobj *tesla = nv50->screen->tesla;
1212 struct nv50_vbo_emitctx emit;
1213
1214 if (emit_prepare(nv50, &emit, 0) == FALSE)
1215 return FALSE;
1216
1217 while (count) {
1218 unsigned i, dw, nr = MIN2(count, emit.vtx_max);
1219 dw = nr * emit.vtx_dwords;
1220
1221 set_edgeflag(chan, tesla, &emit, *map);
1222
1223 BEGIN_RING_NI(chan, tesla, NV50TCL_VERTEX_DATA, dw);
1224 for (i = 0; i < nr; ++i)
1225 emit_vtx(chan, &emit, *map++);
1226
1227 count -= nr;
1228 }
1229
1230 return TRUE;
1231 }