2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
28 #include "nv50_context.h"
30 #define NV50_USING_LOATHED_EDGEFLAG(ctx) ((ctx)->vertprog->cfg.edgeflag_in < 16)
32 static INLINE
unsigned
33 nv50_prim(unsigned mode
)
36 case PIPE_PRIM_POINTS
: return NV50TCL_VERTEX_BEGIN_POINTS
;
37 case PIPE_PRIM_LINES
: return NV50TCL_VERTEX_BEGIN_LINES
;
38 case PIPE_PRIM_LINE_LOOP
: return NV50TCL_VERTEX_BEGIN_LINE_LOOP
;
39 case PIPE_PRIM_LINE_STRIP
: return NV50TCL_VERTEX_BEGIN_LINE_STRIP
;
40 case PIPE_PRIM_TRIANGLES
: return NV50TCL_VERTEX_BEGIN_TRIANGLES
;
41 case PIPE_PRIM_TRIANGLE_STRIP
:
42 return NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP
;
43 case PIPE_PRIM_TRIANGLE_FAN
: return NV50TCL_VERTEX_BEGIN_TRIANGLE_FAN
;
44 case PIPE_PRIM_QUADS
: return NV50TCL_VERTEX_BEGIN_QUADS
;
45 case PIPE_PRIM_QUAD_STRIP
: return NV50TCL_VERTEX_BEGIN_QUAD_STRIP
;
46 case PIPE_PRIM_POLYGON
: return NV50TCL_VERTEX_BEGIN_POLYGON
;
47 case PIPE_PRIM_LINES_ADJACENCY
:
48 return NV50TCL_VERTEX_BEGIN_LINES_ADJACENCY
;
49 case PIPE_PRIM_LINE_STRIP_ADJACENCY
:
50 return NV50TCL_VERTEX_BEGIN_LINE_STRIP_ADJACENCY
;
51 case PIPE_PRIM_TRIANGLES_ADJACENCY
:
52 return NV50TCL_VERTEX_BEGIN_TRIANGLES_ADJACENCY
;
53 case PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
:
54 return NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP_ADJACENCY
;
59 NOUVEAU_ERR("invalid primitive type %d\n", mode
);
60 return NV50TCL_VERTEX_BEGIN_POINTS
;
63 static INLINE
uint32_t
64 nv50_vbo_type_to_hw(enum pipe_format format
)
66 const struct util_format_description
*desc
;
68 desc
= util_format_description(format
);
71 switch (desc
->channel
[0].type
) {
72 case UTIL_FORMAT_TYPE_FLOAT
:
73 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT
;
74 case UTIL_FORMAT_TYPE_UNSIGNED
:
75 if (desc
->channel
[0].normalized
) {
76 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UNORM
;
78 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_USCALED
;
79 case UTIL_FORMAT_TYPE_SIGNED
:
80 if (desc
->channel
[0].normalized
) {
81 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SNORM
;
83 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SSCALED
;
85 case PIPE_FORMAT_TYPE_UINT:
86 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UINT;
87 case PIPE_FORMAT_TYPE_SINT:
88 return NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SINT; */
94 static INLINE
uint32_t
95 nv50_vbo_size_to_hw(unsigned size
, unsigned nr_c
)
97 static const uint32_t hw_values
[] = {
99 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8
,
100 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8
,
101 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8
,
102 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8_8
,
103 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16
,
104 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16
,
105 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16
,
106 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16_16
,
108 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32
,
109 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32
,
110 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32
,
111 NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32
};
113 /* we'd also have R11G11B10 and R10G10B10A2 */
115 assert(nr_c
> 0 && nr_c
<= 4);
121 return hw_values
[size
+ (nr_c
- 1)];
124 static INLINE
uint32_t
125 nv50_vbo_vtxelt_to_hw(struct pipe_vertex_element
*ve
)
127 uint32_t hw_type
, hw_size
;
128 enum pipe_format pf
= ve
->src_format
;
129 const struct util_format_description
*desc
;
130 unsigned size
, nr_components
;
132 desc
= util_format_description(pf
);
135 size
= util_format_get_component_bits(pf
, UTIL_FORMAT_COLORSPACE_RGB
, 0);
136 nr_components
= util_format_get_nr_components(pf
);
138 hw_type
= nv50_vbo_type_to_hw(pf
);
139 hw_size
= nv50_vbo_size_to_hw(size
, nr_components
);
141 if (!hw_type
|| !hw_size
) {
142 NOUVEAU_ERR("unsupported vbo format: %s\n", util_format_name(pf
));
147 if (desc
->swizzle
[0] == UTIL_FORMAT_SWIZZLE_Z
) /* BGRA */
148 hw_size
|= (1 << 31); /* no real swizzle bits :-( */
150 return (hw_type
| hw_size
);
154 nv50_set_static_vtxattr(struct nv50_context
*nv50
, unsigned i
, void *data
)
156 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
157 struct nouveau_channel
*chan
= tesla
->channel
;
159 enum pipe_format pf
= nv50
->vtxelt
->pipe
[i
].src_format
;
160 unsigned nr_components
= util_format_get_nr_components(pf
);
162 util_format_read_4f(pf
, v
, 0, data
, 0, 0, 0, 1, 1);
164 switch (nr_components
) {
166 BEGIN_RING(chan
, tesla
, NV50TCL_VTX_ATTR_4F_X(i
), 4);
167 OUT_RINGf (chan
, v
[0]);
168 OUT_RINGf (chan
, v
[1]);
169 OUT_RINGf (chan
, v
[2]);
170 OUT_RINGf (chan
, v
[3]);
173 BEGIN_RING(chan
, tesla
, NV50TCL_VTX_ATTR_3F_X(i
), 3);
174 OUT_RINGf (chan
, v
[0]);
175 OUT_RINGf (chan
, v
[1]);
176 OUT_RINGf (chan
, v
[2]);
179 BEGIN_RING(chan
, tesla
, NV50TCL_VTX_ATTR_2F_X(i
), 2);
180 OUT_RINGf (chan
, v
[0]);
181 OUT_RINGf (chan
, v
[1]);
184 BEGIN_RING(chan
, tesla
, NV50TCL_VTX_ATTR_1F(i
), 1);
185 OUT_RINGf (chan
, v
[0]);
194 init_per_instance_arrays(struct nv50_context
*nv50
,
195 unsigned startInstance
,
196 unsigned pos
[16], unsigned step
[16])
198 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
199 struct nouveau_channel
*chan
= tesla
->channel
;
200 struct nouveau_bo
*bo
;
201 struct nouveau_stateobj
*so
;
202 unsigned i
, b
, count
= 0, num_elements
= nv50
->vtxelt
->num_elements
;
203 const uint32_t rl
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
;
205 so
= so_new(num_elements
, num_elements
* 2, num_elements
* 2);
207 for (i
= 0; i
< nv50
->vtxelt
->num_elements
; ++i
) {
208 if (!nv50
->vtxelt
->pipe
[i
].instance_divisor
)
211 b
= nv50
->vtxelt
->pipe
[i
].vertex_buffer_index
;
213 pos
[i
] = nv50
->vtxelt
->pipe
[i
].src_offset
+
214 nv50
->vtxbuf
[b
].buffer_offset
+
215 startInstance
* nv50
->vtxbuf
[b
].stride
;
217 if (!startInstance
) {
221 step
[i
] = startInstance
%
222 nv50
->vtxelt
->pipe
[i
].instance_divisor
;
224 bo
= nouveau_bo(nv50
->vtxbuf
[b
].buffer
);
226 so_method(so
, tesla
, NV50TCL_VERTEX_ARRAY_START_HIGH(i
), 2);
227 so_reloc (so
, bo
, pos
[i
], rl
| NOUVEAU_BO_HIGH
, 0, 0);
228 so_reloc (so
, bo
, pos
[i
], rl
| NOUVEAU_BO_LOW
, 0, 0);
231 if (count
&& startInstance
) {
232 so_ref (so
, &nv50
->state
.instbuf
); /* for flush notify */
233 so_emit(chan
, nv50
->state
.instbuf
);
241 step_per_instance_arrays(struct nv50_context
*nv50
,
242 unsigned pos
[16], unsigned step
[16])
244 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
245 struct nouveau_channel
*chan
= tesla
->channel
;
246 struct nouveau_bo
*bo
;
247 struct nouveau_stateobj
*so
;
248 unsigned i
, b
, num_elements
= nv50
->vtxelt
->num_elements
;
249 const uint32_t rl
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
;
251 so
= so_new(num_elements
, num_elements
* 2, num_elements
* 2);
253 for (i
= 0; i
< nv50
->vtxelt
->num_elements
; ++i
) {
254 if (!nv50
->vtxelt
->pipe
[i
].instance_divisor
)
256 b
= nv50
->vtxelt
->pipe
[i
].vertex_buffer_index
;
258 if (++step
[i
] == nv50
->vtxelt
->pipe
[i
].instance_divisor
) {
260 pos
[i
] += nv50
->vtxbuf
[b
].stride
;
263 bo
= nouveau_bo(nv50
->vtxbuf
[b
].buffer
);
265 so_method(so
, tesla
, NV50TCL_VERTEX_ARRAY_START_HIGH(i
), 2);
266 so_reloc (so
, bo
, pos
[i
], rl
| NOUVEAU_BO_HIGH
, 0, 0);
267 so_reloc (so
, bo
, pos
[i
], rl
| NOUVEAU_BO_LOW
, 0, 0);
270 so_ref (so
, &nv50
->state
.instbuf
); /* for flush notify */
273 so_emit(chan
, nv50
->state
.instbuf
);
277 nv50_draw_arrays_instanced(struct pipe_context
*pipe
,
278 unsigned mode
, unsigned start
, unsigned count
,
279 unsigned startInstance
, unsigned instanceCount
)
281 struct nv50_context
*nv50
= nv50_context(pipe
);
282 struct nouveau_channel
*chan
= nv50
->screen
->tesla
->channel
;
283 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
284 unsigned i
, nz_divisors
;
285 unsigned step
[16], pos
[16];
287 if (!nv50_state_validate(nv50
, 0))
289 chan
->flush_notify
= nv50_state_flush_notify
;
291 nz_divisors
= init_per_instance_arrays(nv50
, startInstance
, pos
, step
);
293 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 2);
294 OUT_RING (chan
, NV50_CB_AUX
| (24 << 8));
295 OUT_RING (chan
, startInstance
);
297 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BEGIN
, 1);
298 OUT_RING (chan
, nv50_prim(mode
));
299 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BUFFER_FIRST
, 2);
300 OUT_RING (chan
, start
);
301 OUT_RING (chan
, count
);
302 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_END
, 1);
305 for (i
= 1; i
< instanceCount
; i
++) {
306 if (nz_divisors
) /* any non-zero array divisors ? */
307 step_per_instance_arrays(nv50
, pos
, step
);
309 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BEGIN
, 1);
310 OUT_RING (chan
, nv50_prim(mode
) | (1 << 28));
311 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BUFFER_FIRST
, 2);
312 OUT_RING (chan
, start
);
313 OUT_RING (chan
, count
);
314 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_END
, 1);
318 chan
->flush_notify
= NULL
;
320 so_ref(NULL
, &nv50
->state
.instbuf
);
324 nv50_draw_arrays(struct pipe_context
*pipe
, unsigned mode
, unsigned start
,
327 struct nv50_context
*nv50
= nv50_context(pipe
);
328 struct nouveau_channel
*chan
= nv50
->screen
->tesla
->channel
;
329 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
331 if (!nv50_state_validate(nv50
, 11))
333 chan
->flush_notify
= nv50_state_flush_notify
;
335 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BEGIN
, 1);
336 OUT_RING (chan
, nv50_prim(mode
));
337 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BUFFER_FIRST
, 2);
338 OUT_RING (chan
, start
);
339 OUT_RING (chan
, count
);
340 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_END
, 1);
343 chan
->flush_notify
= NULL
;
346 static INLINE boolean
347 nv50_draw_elements_inline_u08(struct nv50_context
*nv50
, uint8_t *map
,
348 unsigned start
, unsigned count
)
350 struct nouveau_channel
*chan
= nv50
->screen
->tesla
->channel
;
351 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
356 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U32
, 1);
357 OUT_RING (chan
, map
[0]);
363 unsigned nr
= count
> 2046 ? 2046 : count
;
366 BEGIN_RING_NI(chan
, tesla
, NV50TCL_VB_ELEMENT_U16
, nr
>> 1);
367 for (i
= 0; i
< nr
; i
+= 2)
368 OUT_RING (chan
, (map
[i
+ 1] << 16) | map
[i
]);
376 static INLINE boolean
377 nv50_draw_elements_inline_u16(struct nv50_context
*nv50
, uint16_t *map
,
378 unsigned start
, unsigned count
)
380 struct nouveau_channel
*chan
= nv50
->screen
->tesla
->channel
;
381 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
386 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U32
, 1);
387 OUT_RING (chan
, map
[0]);
393 unsigned nr
= count
> 2046 ? 2046 : count
;
396 BEGIN_RING_NI(chan
, tesla
, NV50TCL_VB_ELEMENT_U16
, nr
>> 1);
397 for (i
= 0; i
< nr
; i
+= 2)
398 OUT_RING (chan
, (map
[i
+ 1] << 16) | map
[i
]);
406 static INLINE boolean
407 nv50_draw_elements_inline_u32(struct nv50_context
*nv50
, uint32_t *map
,
408 unsigned start
, unsigned count
)
410 struct nouveau_channel
*chan
= nv50
->screen
->tesla
->channel
;
411 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
416 unsigned nr
= count
> 2047 ? 2047 : count
;
418 BEGIN_RING_NI(chan
, tesla
, NV50TCL_VB_ELEMENT_U32
, nr
);
419 OUT_RINGp (chan
, map
, nr
);
428 nv50_draw_elements_inline(struct nv50_context
*nv50
,
429 void *map
, unsigned indexSize
,
430 unsigned start
, unsigned count
)
434 nv50_draw_elements_inline_u08(nv50
, map
, start
, count
);
437 nv50_draw_elements_inline_u16(nv50
, map
, start
, count
);
440 nv50_draw_elements_inline_u32(nv50
, map
, start
, count
);
446 nv50_draw_elements_instanced(struct pipe_context
*pipe
,
447 struct pipe_buffer
*indexBuffer
,
449 unsigned mode
, unsigned start
, unsigned count
,
450 unsigned startInstance
, unsigned instanceCount
)
452 struct nv50_context
*nv50
= nv50_context(pipe
);
453 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
454 struct nouveau_channel
*chan
= tesla
->channel
;
455 struct pipe_screen
*pscreen
= pipe
->screen
;
457 unsigned i
, nz_divisors
;
458 unsigned step
[16], pos
[16];
460 map
= pipe_buffer_map(pscreen
, indexBuffer
, PIPE_BUFFER_USAGE_CPU_READ
);
462 if (!nv50_state_validate(nv50
, 0))
464 chan
->flush_notify
= nv50_state_flush_notify
;
466 nz_divisors
= init_per_instance_arrays(nv50
, startInstance
, pos
, step
);
468 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 2);
469 OUT_RING (chan
, NV50_CB_AUX
| (24 << 8));
470 OUT_RING (chan
, startInstance
);
472 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BEGIN
, 1);
473 OUT_RING (chan
, nv50_prim(mode
));
475 nv50_draw_elements_inline(nv50
, map
, indexSize
, start
, count
);
477 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_END
, 1);
480 for (i
= 1; i
< instanceCount
; ++i
) {
481 if (nz_divisors
) /* any non-zero array divisors ? */
482 step_per_instance_arrays(nv50
, pos
, step
);
484 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BEGIN
, 1);
485 OUT_RING (chan
, nv50_prim(mode
) | (1 << 28));
487 nv50_draw_elements_inline(nv50
, map
, indexSize
, start
, count
);
489 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_END
, 1);
493 chan
->flush_notify
= NULL
;
495 so_ref(NULL
, &nv50
->state
.instbuf
);
499 nv50_draw_elements(struct pipe_context
*pipe
,
500 struct pipe_buffer
*indexBuffer
, unsigned indexSize
,
501 unsigned mode
, unsigned start
, unsigned count
)
503 struct nv50_context
*nv50
= nv50_context(pipe
);
504 struct nouveau_channel
*chan
= nv50
->screen
->tesla
->channel
;
505 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
506 struct pipe_screen
*pscreen
= pipe
->screen
;
509 if (!nv50_state_validate(nv50
, 14))
511 chan
->flush_notify
= nv50_state_flush_notify
;
513 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_BEGIN
, 1);
514 OUT_RING (chan
, nv50_prim(mode
));
516 if (indexSize
== 4) {
517 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U32
| 0x30000, 0);
518 OUT_RING (chan
, count
);
519 nouveau_pushbuf_submit(chan
, nouveau_bo(indexBuffer
),
520 start
<< 2, count
<< 2);
522 if (indexSize
== 2) {
523 unsigned vb_start
= (start
& ~1);
524 unsigned vb_end
= (start
+ count
+ 1) & ~1;
525 unsigned dwords
= (vb_end
- vb_start
) >> 1;
527 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U16_SETUP
, 1);
528 OUT_RING (chan
, ((start
& 1) << 31) | count
);
529 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U16
| 0x30000, 0);
530 OUT_RING (chan
, dwords
);
531 nouveau_pushbuf_submit(chan
, nouveau_bo(indexBuffer
),
532 vb_start
<< 1, dwords
<< 2);
533 BEGIN_RING(chan
, tesla
, NV50TCL_VB_ELEMENT_U16_SETUP
, 1);
536 map
= pipe_buffer_map(pscreen
, indexBuffer
,
537 PIPE_BUFFER_USAGE_CPU_READ
);
538 nv50_draw_elements_inline(nv50
, map
, indexSize
, start
, count
);
539 pipe_buffer_unmap(pscreen
, indexBuffer
);
542 BEGIN_RING(chan
, tesla
, NV50TCL_VERTEX_END
, 1);
544 chan
->flush_notify
= NULL
;
547 static INLINE boolean
548 nv50_vbo_static_attrib(struct nv50_context
*nv50
, unsigned attrib
,
549 struct nouveau_stateobj
**pso
,
550 struct pipe_vertex_element
*ve
,
551 struct pipe_vertex_buffer
*vb
)
554 struct nouveau_stateobj
*so
;
555 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
556 struct nouveau_bo
*bo
= nouveau_bo(vb
->buffer
);
559 unsigned nr_components
= util_format_get_nr_components(ve
->src_format
);
561 ret
= nouveau_bo_map(bo
, NOUVEAU_BO_RD
);
565 util_format_read_4f(ve
->src_format
, v
, 0, (uint8_t *)bo
->map
+
566 (vb
->buffer_offset
+ ve
->src_offset
), 0,
570 *pso
= so
= so_new(nv50
->vtxelt
->num_elements
,
571 nv50
->vtxelt
->num_elements
* 4, 0);
573 switch (nr_components
) {
575 so_method(so
, tesla
, NV50TCL_VTX_ATTR_4F_X(attrib
), 4);
576 so_data (so
, fui(v
[0]));
577 so_data (so
, fui(v
[1]));
578 so_data (so
, fui(v
[2]));
579 so_data (so
, fui(v
[3]));
582 so_method(so
, tesla
, NV50TCL_VTX_ATTR_3F_X(attrib
), 3);
583 so_data (so
, fui(v
[0]));
584 so_data (so
, fui(v
[1]));
585 so_data (so
, fui(v
[2]));
588 so_method(so
, tesla
, NV50TCL_VTX_ATTR_2F_X(attrib
), 2);
589 so_data (so
, fui(v
[0]));
590 so_data (so
, fui(v
[1]));
593 if (attrib
== nv50
->vertprog
->cfg
.edgeflag_in
) {
594 so_method(so
, tesla
, NV50TCL_EDGEFLAG_ENABLE
, 1);
595 so_data (so
, v
[0] ? 1 : 0);
597 so_method(so
, tesla
, NV50TCL_VTX_ATTR_1F(attrib
), 1);
598 so_data (so
, fui(v
[0]));
601 nouveau_bo_unmap(bo
);
605 nouveau_bo_unmap(bo
);
610 nv50_vtxelt_construct(struct nv50_vtxelt_stateobj
*cso
)
614 for (i
= 0; i
< cso
->num_elements
; ++i
) {
615 struct pipe_vertex_element
*ve
= &cso
->pipe
[i
];
617 cso
->hw
[i
] = nv50_vbo_vtxelt_to_hw(ve
);
621 struct nouveau_stateobj
*
622 nv50_vbo_validate(struct nv50_context
*nv50
)
624 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
625 struct nouveau_stateobj
*vtxbuf
, *vtxfmt
, *vtxattr
;
628 /* don't validate if Gallium took away our buffers */
629 if (nv50
->vtxbuf_nr
== 0)
632 assert(!NV50_USING_LOATHED_EDGEFLAG(nv50
));
634 n_ve
= MAX2(nv50
->vtxelt
->num_elements
, nv50
->state
.vtxelt_nr
);
637 vtxbuf
= so_new(n_ve
* 2, n_ve
* 5, nv50
->vtxelt
->num_elements
* 4);
638 vtxfmt
= so_new(1, n_ve
, 0);
639 so_method(vtxfmt
, tesla
, NV50TCL_VERTEX_ARRAY_ATTRIB(0), n_ve
);
641 for (i
= 0; i
< nv50
->vtxelt
->num_elements
; i
++) {
642 struct pipe_vertex_element
*ve
= &nv50
->vtxelt
->pipe
[i
];
643 struct pipe_vertex_buffer
*vb
=
644 &nv50
->vtxbuf
[ve
->vertex_buffer_index
];
645 struct nouveau_bo
*bo
= nouveau_bo(vb
->buffer
);
646 uint32_t hw
= nv50
->vtxelt
->hw
[i
];
649 nv50_vbo_static_attrib(nv50
, i
, &vtxattr
, ve
, vb
)) {
650 so_data(vtxfmt
, hw
| (1 << 4));
652 so_method(vtxbuf
, tesla
,
653 NV50TCL_VERTEX_ARRAY_FORMAT(i
), 1);
658 so_data(vtxfmt
, hw
| i
);
660 so_method(vtxbuf
, tesla
, NV50TCL_VERTEX_ARRAY_FORMAT(i
), 3);
661 so_data (vtxbuf
, 0x20000000 |
662 (ve
->instance_divisor
? 0 : vb
->stride
));
663 so_reloc (vtxbuf
, bo
, vb
->buffer_offset
+
664 ve
->src_offset
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
|
665 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
666 so_reloc (vtxbuf
, bo
, vb
->buffer_offset
+
667 ve
->src_offset
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
|
668 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
670 /* vertex array limits */
671 so_method(vtxbuf
, tesla
, NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i
), 2);
672 so_reloc (vtxbuf
, bo
, vb
->buffer
->size
- 1,
673 NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
|
674 NOUVEAU_BO_HIGH
, 0, 0);
675 so_reloc (vtxbuf
, bo
, vb
->buffer
->size
- 1,
676 NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
|
677 NOUVEAU_BO_LOW
, 0, 0);
679 for (; i
< n_ve
; ++i
) {
680 so_data (vtxfmt
, 0x7e080010);
682 so_method(vtxbuf
, tesla
, NV50TCL_VERTEX_ARRAY_FORMAT(i
), 1);
685 nv50
->state
.vtxelt_nr
= nv50
->vtxelt
->num_elements
;
687 so_ref (vtxbuf
, &nv50
->state
.vtxbuf
);
688 so_ref (vtxattr
, &nv50
->state
.vtxattr
);
689 so_ref (NULL
, &vtxbuf
);
690 so_ref (NULL
, &vtxattr
);