src/gallium/drivers/nv50/nv50_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "pipe/p_context.h"
  24 #include "pipe/p_state.h"
  25 #include "util/u_inlines.h"
  26 #include "util/u_format.h"
  27 #include "translate/translate.h"
  28
  29 #include "nv50_context.h"
  30 #include "nv50_resource.h"
  31
  32 #include "nv50_3d.xml.h"
  33
  34 void
  35 nv50_vertex_state_delete(struct pipe_context *pipe,
  36                          void *hwcso)
  37 {
  38    struct nv50_vertex_stateobj *so = hwcso;
  39
  40    if (so->translate)
  41       so->translate->release(so->translate);
  42    FREE(hwcso);
  43 }
  44
  45 void *
  46 nv50_vertex_state_create(struct pipe_context *pipe,
  47                          unsigned num_elements,
  48                          const struct pipe_vertex_element *elements)
  49 {
  50     struct nv50_vertex_stateobj *so;
  51     struct translate_key transkey;
  52     unsigned i;
  53
  54     so = MALLOC(sizeof(*so) +
  55                 num_elements * sizeof(struct nv50_vertex_element));
  56     if (!so)
  57         return NULL;
  58     so->num_elements = num_elements;
  59     so->instance_elts = 0;
  60     so->instance_bufs = 0;
  61     so->need_conversion = FALSE;
  62
  63     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  64
  65     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  66        so->min_instance_div[i] = 0xffffffff;
  67
  68     transkey.nr_elements = 0;
  69     transkey.output_stride = 0;
  70
  71     for (i = 0; i < num_elements; ++i) {
  72         const struct pipe_vertex_element *ve = &elements[i];
  73         const unsigned vbi = ve->vertex_buffer_index;
  74         unsigned size;
  75         enum pipe_format fmt = ve->src_format;
  76
  77         so->element[i].pipe = elements[i];
  78         so->element[i].state = nv50_format_table[fmt].vtx;
  79
  80         if (!so->element[i].state) {
  81             switch (util_format_get_nr_components(fmt)) {
  82             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  83             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  84             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  85             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  86             default:
  87                 assert(0);
  88                 return NULL;
  89             }
  90             so->element[i].state = nv50_format_table[fmt].vtx;
  91             so->need_conversion = TRUE;
  92         }
  93         so->element[i].state |= i;
  94
  95         size = util_format_get_blocksize(fmt);
  96         if (so->vb_access_size[vbi] < (ve->src_offset + size))
  97            so->vb_access_size[vbi] = ve->src_offset + size;
  98
  99         if (1) {
 100             unsigned j = transkey.nr_elements++;
 101
 102             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
 103             transkey.element[j].input_format = ve->src_format;
 104             transkey.element[j].input_buffer = vbi;
 105             transkey.element[j].input_offset = ve->src_offset;
 106             transkey.element[j].instance_divisor = ve->instance_divisor;
 107
 108             transkey.element[j].output_format = fmt;
 109             transkey.element[j].output_offset = transkey.output_stride;
 110             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
 111
 112             if (unlikely(ve->instance_divisor)) {
 113                so->instance_elts |= 1 << i;
 114                so->instance_bufs |= 1 << vbi;
 115                if (ve->instance_divisor < so->min_instance_div[vbi])
 116                   so->min_instance_div[vbi] = ve->instance_divisor;
 117             }
 118         }
 119     }
 120
 121     so->translate = translate_create(&transkey);
 122     so->vertex_size = transkey.output_stride / 4;
 123     so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
 124        MAX2(so->vertex_size, 1);
 125
 126     return so;
 127 }
 128
 129 #define NV50_3D_VERTEX_ATTRIB_INACTIVE              \
 130    NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT |         \
 131    NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
 132    NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
 133
 134 static void
 135 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
 136                   struct pipe_vertex_element *ve, unsigned attr)
 137 {
 138    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 139    const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset;
 140    float v[4];
 141    const unsigned nc = util_format_get_nr_components(ve->src_format);
 142
 143    assert(vb->user_buffer);
 144
 145    util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
 146
 147    switch (nc) {
 148    case 4:
 149       BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
 150       PUSH_DATAf(push, v[0]);
 151       PUSH_DATAf(push, v[1]);
 152       PUSH_DATAf(push, v[2]);
 153       PUSH_DATAf(push, v[3]);
 154       break;
 155    case 3:
 156       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
 157       PUSH_DATAf(push, v[0]);
 158       PUSH_DATAf(push, v[1]);
 159       PUSH_DATAf(push, v[2]);
 160       break;
 161    case 2:
 162       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
 163       PUSH_DATAf(push, v[0]);
 164       PUSH_DATAf(push, v[1]);
 165       break;
 166    case 1:
 167       if (attr == nv50->vertprog->vp.edgeflag) {
 168          BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 169          PUSH_DATA (push, v[0] ? 1 : 0);
 170       }
 171       BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
 172       PUSH_DATAf(push, v[0]);
 173       break;
 174    default:
 175       assert(0);
 176       break;
 177    }
 178 }
 179
 180 static INLINE void
 181 nv50_user_vbuf_range(struct nv50_context *nv50, int vbi,
 182                      uint32_t *base, uint32_t *size)
 183 {
 184    if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
 185       /* TODO: use min and max instance divisor to get a proper range */
 186       *base = 0;
 187       *size = nv50->vtxbuf[vbi].buffer->width0;
 188    } else {
 189       /* NOTE: if there are user buffers, we *must* have index bounds */
 190       assert(nv50->vb_elt_limit != ~0);
 191       *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
 192       *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
 193          nv50->vertex->vb_access_size[vbi];
 194    }
 195 }
 196
 197 static void
 198 nv50_upload_user_buffers(struct nv50_context *nv50,
 199                          uint64_t addrs[], uint32_t limits[])
 200 {
 201    unsigned b;
 202
 203    for (b = 0; b < nv50->num_vtxbufs; ++b) {
 204       struct nouveau_bo *bo;
 205       const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
 206       uint32_t base, size;
 207
 208       if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
 209          continue;
 210       nv50_user_vbuf_range(nv50, b, &base, &size);
 211
 212       limits[b] = base + size - 1;
 213       addrs[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, base, size,
 214                                       &bo);
 215       if (addrs[b])
 216          BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, NOUVEAU_BO_GART |
 217                       NOUVEAU_BO_RD, bo);
 218    }
 219    nv50->base.vbo_dirty = TRUE;
 220 }
 221
 222 static void
 223 nv50_update_user_vbufs(struct nv50_context *nv50)
 224 {
 225    uint64_t address[PIPE_MAX_ATTRIBS];
 226    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 227    unsigned i;
 228    uint32_t written = 0;
 229
 230    for (i = 0; i < nv50->vertex->num_elements; ++i) {
 231       struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
 232       const unsigned b = ve->vertex_buffer_index;
 233       struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
 234       uint32_t base, size;
 235
 236       if (!(nv50->vbo_user & (1 << b)))
 237          continue;
 238
 239       if (!vb->stride) {
 240          nv50_emit_vtxattr(nv50, vb, ve, i);
 241          continue;
 242       }
 243       nv50_user_vbuf_range(nv50, b, &base, &size);
 244
 245       if (!(written & (1 << b))) {
 246          struct nouveau_bo *bo;
 247          const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 248          written |= 1 << b;
 249          address[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer,
 250                                            base, size, &bo);
 251          if (address[b])
 252             BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, bo_flags, bo);
 253       }
 254
 255       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 256       PUSH_DATAh(push, address[b] + base + size - 1);
 257       PUSH_DATA (push, address[b] + base + size - 1);
 258       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
 259       PUSH_DATAh(push, address[b] + ve->src_offset);
 260       PUSH_DATA (push, address[b] + ve->src_offset);
 261    }
 262    nv50->base.vbo_dirty = TRUE;
 263 }
 264
 265 static INLINE void
 266 nv50_release_user_vbufs(struct nv50_context *nv50)
 267 {
 268    if (nv50->vbo_user) {
 269       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX_TMP);
 270       nouveau_scratch_done(&nv50->base);
 271    }
 272 }
 273
 274 void
 275 nv50_vertex_arrays_validate(struct nv50_context *nv50)
 276 {
 277    uint64_t addrs[PIPE_MAX_ATTRIBS];
 278    uint32_t limits[PIPE_MAX_ATTRIBS];
 279    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 280    struct nv50_vertex_stateobj *vertex = nv50->vertex;
 281    struct pipe_vertex_buffer *vb;
 282    struct nv50_vertex_element *ve;
 283    uint32_t mask;
 284    uint32_t refd = 0;
 285    unsigned i;
 286    const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
 287
 288    if (unlikely(vertex->need_conversion))
 289       nv50->vbo_fifo = ~0;
 290    else
 291    if (nv50->vbo_user & ~nv50->vbo_constant)
 292       nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
 293    else
 294       nv50->vbo_fifo = 0;
 295
 296    /* update vertex format state */
 297    BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
 298    if (nv50->vbo_fifo) {
 299       nv50->state.num_vtxelts = vertex->num_elements;
 300       for (i = 0; i < vertex->num_elements; ++i)
 301          PUSH_DATA (push, vertex->element[i].state);
 302       for (; i < n; ++i)
 303          PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 304       for (i = 0; i < n; ++i) {
 305          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 306          PUSH_DATA (push, 0);
 307       }
 308       return;
 309    }
 310    for (i = 0; i < vertex->num_elements; ++i) {
 311       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 312       ve = &vertex->element[i];
 313       vb = &nv50->vtxbuf[b];
 314
 315       if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
 316          PUSH_DATA(push, ve->state);
 317       else
 318          PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
 319    }
 320    for (; i < n; ++i)
 321       PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 322
 323    /* update per-instance enables */
 324    mask = vertex->instance_elts ^ nv50->state.instance_elts;
 325    while (mask) {
 326       const int i = ffs(mask) - 1;
 327       mask &= ~(1 << i);
 328       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 329       PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
 330    }
 331    nv50->state.instance_elts = vertex->instance_elts;
 332
 333    if (nv50->vbo_user & ~nv50->vbo_constant)
 334       nv50_upload_user_buffers(nv50, addrs, limits);
 335
 336    /* update buffers and set constant attributes */
 337    for (i = 0; i < vertex->num_elements; ++i) {
 338       uint64_t address, limit;
 339       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 340       ve = &vertex->element[i];
 341       vb = &nv50->vtxbuf[b];
 342
 343       if (unlikely(nv50->vbo_constant & (1 << b))) {
 344          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 345          PUSH_DATA (push, 0);
 346          nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
 347          continue;
 348       } else
 349       if (nv50->vbo_user & (1 << b)) {
 350          address = addrs[b] + ve->pipe.src_offset;
 351          limit = addrs[b] + limits[b];
 352       } else {
 353          struct nv04_resource *buf = nv04_resource(vb->buffer);
 354          if (!(refd & (1 << b))) {
 355             refd |= 1 << b;
 356             BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
 357          }
 358          address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
 359          limit = buf->address + buf->base.width0 - 1;
 360       }
 361
 362       if (unlikely(ve->pipe.instance_divisor)) {
 363          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
 364          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 365          PUSH_DATAh(push, address);
 366          PUSH_DATA (push, address);
 367          PUSH_DATA (push, ve->pipe.instance_divisor);
 368       } else {
 369          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
 370          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 371          PUSH_DATAh(push, address);
 372          PUSH_DATA (push, address);
 373       }
 374       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 375       PUSH_DATAh(push, limit);
 376       PUSH_DATA (push, limit);
 377    }
 378    for (; i < nv50->state.num_vtxelts; ++i) {
 379       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 380       PUSH_DATA (push, 0);
 381    }
 382    nv50->state.num_vtxelts = vertex->num_elements;
 383 }
 384
 385 #define NV50_PRIM_GL_CASE(n) \
 386    case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 387
 388 static INLINE unsigned
 389 nv50_prim_gl(unsigned prim)
 390 {
 391    switch (prim) {
 392    NV50_PRIM_GL_CASE(POINTS);
 393    NV50_PRIM_GL_CASE(LINES);
 394    NV50_PRIM_GL_CASE(LINE_LOOP);
 395    NV50_PRIM_GL_CASE(LINE_STRIP);
 396    NV50_PRIM_GL_CASE(TRIANGLES);
 397    NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
 398    NV50_PRIM_GL_CASE(TRIANGLE_FAN);
 399    NV50_PRIM_GL_CASE(QUADS);
 400    NV50_PRIM_GL_CASE(QUAD_STRIP);
 401    NV50_PRIM_GL_CASE(POLYGON);
 402    NV50_PRIM_GL_CASE(LINES_ADJACENCY);
 403    NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 404    NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 405    NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 406    default:
 407       return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 408       break;
 409    }
 410 }
 411
 412 /* For pre-nva0 transform feedback. */
 413 static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
 414 {
 415    [PIPE_PRIM_POINTS] = 1,
 416    [PIPE_PRIM_LINES] = 2,
 417    [PIPE_PRIM_LINE_LOOP] = 2,
 418    [PIPE_PRIM_LINE_STRIP] = 2,
 419    [PIPE_PRIM_TRIANGLES] = 3,
 420    [PIPE_PRIM_TRIANGLE_STRIP] = 3,
 421    [PIPE_PRIM_TRIANGLE_FAN] = 3,
 422    [PIPE_PRIM_QUADS] = 3,
 423    [PIPE_PRIM_QUAD_STRIP] = 3,
 424    [PIPE_PRIM_POLYGON] = 3,
 425    [PIPE_PRIM_LINES_ADJACENCY] = 2,
 426    [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
 427    [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
 428    [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
 429 };
 430
 431 static void
 432 nv50_draw_arrays(struct nv50_context *nv50,
 433                  unsigned mode, unsigned start, unsigned count,
 434                  unsigned instance_count)
 435 {
 436    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 437    unsigned prim;
 438
 439    if (nv50->state.index_bias) {
 440       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 441       PUSH_DATA (push, 0);
 442       nv50->state.index_bias = 0;
 443    }
 444
 445    prim = nv50_prim_gl(mode);
 446
 447    while (instance_count--) {
 448       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 449       PUSH_DATA (push, prim);
 450       BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
 451       PUSH_DATA (push, start);
 452       PUSH_DATA (push, count);
 453       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 454       PUSH_DATA (push, 0);
 455
 456       prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 457    }
 458 }
 459
 460 static void
 461 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
 462                               unsigned start, unsigned count)
 463 {
 464    map += start;
 465
 466    if (count & 3) {
 467       unsigned i;
 468       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
 469       for (i = 0; i < (count & 3); ++i)
 470          PUSH_DATA(push, *map++);
 471       count &= ~3;
 472    }
 473    while (count) {
 474       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 475
 476       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
 477       for (i = 0; i < nr; ++i) {
 478          PUSH_DATA(push,
 479                    (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 480          map += 4;
 481       }
 482       count -= nr * 4;
 483    }
 484 }
 485
 486 static void
 487 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
 488                               unsigned start, unsigned count)
 489 {
 490    map += start;
 491
 492    if (count & 1) {
 493       count &= ~1;
 494       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 495       PUSH_DATA (push, *map++);
 496    }
 497    while (count) {
 498       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 499
 500       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 501       for (i = 0; i < nr; ++i) {
 502          PUSH_DATA(push, (map[1] << 16) | map[0]);
 503          map += 2;
 504       }
 505       count -= nr * 2;
 506    }
 507 }
 508
 509 static void
 510 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
 511                               unsigned start, unsigned count)
 512 {
 513    map += start;
 514
 515    while (count) {
 516       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 517
 518       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
 519       PUSH_DATAp(push, map, nr);
 520
 521       map += nr;
 522       count -= nr;
 523    }
 524 }
 525
 526 static void
 527 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
 528                                     const uint32_t *map,
 529                                     unsigned start, unsigned count)
 530 {
 531    map += start;
 532
 533    if (count & 1) {
 534       count--;
 535       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 536       PUSH_DATA (push, *map++);
 537    }
 538    while (count) {
 539       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 540
 541       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 542       for (i = 0; i < nr; ++i) {
 543          PUSH_DATA(push, (map[1] << 16) | map[0]);
 544          map += 2;
 545       }
 546       count -= nr * 2;
 547    }
 548 }
 549
 550 static void
 551 nv50_draw_elements(struct nv50_context *nv50, boolean shorten,
 552                    unsigned mode, unsigned start, unsigned count,
 553                    unsigned instance_count, int32_t index_bias)
 554 {
 555    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 556    unsigned prim;
 557    const unsigned index_size = nv50->idxbuf.index_size;
 558
 559    prim = nv50_prim_gl(mode);
 560
 561    if (index_bias != nv50->state.index_bias) {
 562       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 563       PUSH_DATA (push, index_bias);
 564       nv50->state.index_bias = index_bias;
 565    }
 566
 567    if (nv50->idxbuf.buffer) {
 568       struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
 569       unsigned pb_start;
 570       unsigned pb_bytes;
 571       const unsigned base = buf->offset + nv50->idxbuf.offset;
 572
 573       assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
 574
 575       while (instance_count--) {
 576          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 577          PUSH_DATA (push, prim);
 578
 579          nouveau_pushbuf_space(push, 8, 0, 1);
 580
 581          switch (index_size) {
 582          case 4:
 583             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
 584             nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
 585             break;
 586          case 2:
 587             pb_start = (start & ~1) * 2;
 588             pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
 589
 590             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 591             PUSH_DATA (push, (start << 31) | count);
 592             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
 593             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 594             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 595             PUSH_DATA (push, 0);
 596             break;
 597          default:
 598             assert(index_size == 1);
 599             pb_start = start & ~3;
 600             pb_bytes = ((start + count + 3) & ~3) - pb_start;
 601
 602             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 603             PUSH_DATA (push, (start << 30) | count);
 604             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
 605             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 606             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 607             PUSH_DATA (push, 0);
 608             break;
 609          }
 610          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 611          PUSH_DATA (push, 0);
 612
 613          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 614       }
 615    } else {
 616       const void *data = nv50->idxbuf.user_buffer;
 617
 618       while (instance_count--) {
 619          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 620          PUSH_DATA (push, prim);
 621          switch (index_size) {
 622          case 1:
 623             nv50_draw_elements_inline_u08(push, data, start, count);
 624             break;
 625          case 2:
 626             nv50_draw_elements_inline_u16(push, data, start, count);
 627             break;
 628          case 4:
 629             if (shorten)
 630                nv50_draw_elements_inline_u32_short(push, data, start, count);
 631             else
 632                nv50_draw_elements_inline_u32(push, data, start, count);
 633             break;
 634          default:
 635             assert(0);
 636             return;
 637          }
 638          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 639          PUSH_DATA (push, 0);
 640
 641          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 642       }
 643    }
 644 }
 645
 646 static void
 647 nva0_draw_stream_output(struct nv50_context *nv50,
 648                         const struct pipe_draw_info *info)
 649 {
 650    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 651    struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
 652    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
 653    unsigned num_instances = info->instance_count;
 654    unsigned mode = nv50_prim_gl(info->mode);
 655
 656    if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
 657       /* A proper implementation without waiting doesn't seem possible,
 658        * so don't bother.
 659        */
 660       NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
 661       return;
 662    }
 663
 664    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 665       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 666       PUSH_SPACE(push, 4);
 667       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
 668       PUSH_DATA (push, 0);
 669       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 670       PUSH_DATA (push, 0);
 671    }
 672
 673    assert(num_instances);
 674    do {
 675       PUSH_SPACE(push, 8);
 676       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 677       PUSH_DATA (push, mode);
 678       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
 679       PUSH_DATA (push, 0);
 680       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
 681       PUSH_DATA (push, 0);
 682       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BYTES), 1);
 683       nv50_query_pushbuf_submit(push, so->pq, 0x4);
 684       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 685       PUSH_DATA (push, 0);
 686
 687       mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 688    } while (--num_instances);
 689 }
 690
 691 static void
 692 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
 693 {
 694    struct nv50_screen *screen = chan->user_priv;
 695
 696    nouveau_fence_update(&screen->base, TRUE);
 697
 698    nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, TRUE);
 699 }
 700
 701 void
 702 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 703 {
 704    struct nv50_context *nv50 = nv50_context(pipe);
 705    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 706
 707    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
 708    nv50->vb_elt_first = info->min_index + info->index_bias;
 709    nv50->vb_elt_limit = info->max_index - info->min_index;
 710    nv50->instance_off = info->start_instance;
 711    nv50->instance_max = info->instance_count - 1;
 712
 713    /* For picking only a few vertices from a large user buffer, push is better,
 714     * if index count is larger and we expect repeated vertices, suggest upload.
 715     */
 716    nv50->vbo_push_hint = /* the 64 is heuristic */
 717       !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count));
 718
 719    if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_ARRAYS | NV50_NEW_VERTEX))) {
 720       if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
 721          nv50->dirty |= NV50_NEW_ARRAYS;
 722       else
 723       if (!nv50->vbo_fifo)
 724          nv50_update_user_vbufs(nv50);
 725    }
 726
 727    if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
 728       nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
 729
 730    nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
 731
 732    push->kick_notify = nv50_draw_vbo_kick_notify;
 733
 734    if (nv50->vbo_fifo) {
 735       nv50_push_vbo(nv50, info);
 736       push->kick_notify = nv50_default_kick_notify;
 737       nouveau_pushbuf_bufctx(push, NULL);
 738       return;
 739    }
 740
 741    if (nv50->state.instance_base != info->start_instance) {
 742       nv50->state.instance_base = info->start_instance;
 743       /* NOTE: this does not affect the shader input, should it ? */
 744       BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
 745       PUSH_DATA (push, info->start_instance);
 746    }
 747
 748    if (nv50->base.vbo_dirty) {
 749       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 750       PUSH_DATA (push, 0);
 751       nv50->base.vbo_dirty = FALSE;
 752    }
 753
 754    if (info->indexed) {
 755       boolean shorten = info->max_index <= 65535;
 756
 757       if (info->primitive_restart != nv50->state.prim_restart) {
 758          if (info->primitive_restart) {
 759             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
 760             PUSH_DATA (push, 1);
 761             PUSH_DATA (push, info->restart_index);
 762
 763             if (info->restart_index > 65535)
 764                shorten = FALSE;
 765          } else {
 766             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
 767             PUSH_DATA (push, 0);
 768          }
 769          nv50->state.prim_restart = info->primitive_restart;
 770       } else
 771       if (info->primitive_restart) {
 772          BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
 773          PUSH_DATA (push, info->restart_index);
 774
 775          if (info->restart_index > 65535)
 776             shorten = FALSE;
 777       }
 778
 779       nv50_draw_elements(nv50, shorten,
 780                          info->mode, info->start, info->count,
 781                          info->instance_count, info->index_bias);
 782    } else
 783    if (unlikely(info->count_from_stream_output)) {
 784       nva0_draw_stream_output(nv50, info);
 785    } else {
 786       nv50_draw_arrays(nv50,
 787                        info->mode, info->start, info->count,
 788                        info->instance_count);
 789    }
 790    push->kick_notify = nv50_default_kick_notify;
 791
 792    nv50_release_user_vbufs(nv50);
 793
 794    nouveau_pushbuf_bufctx(push, NULL);
 795 }