src/gallium/drivers/nvc0/nvc0_pc_emit.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "nvc0_pc.h"
  24 #include "nvc0_program.h"
  25
  26 #define NVC0_FIXUP_CODE_RELOC 0
  27 #define NVC0_FIXUP_DATA_RELOC 1
  28
  29 struct nvc0_fixup {
  30    uint8_t type;
  31    int8_t shift;
  32    uint32_t mask;
  33    uint32_t data;
  34    uint32_t ofst;
  35 };
  36
  37 void
  38 nvc0_relocate_program(struct nvc0_program *prog,
  39                       uint32_t code_base,
  40                       uint32_t data_base)
  41 {
  42    struct nvc0_fixup *f = (struct nvc0_fixup *)prog->relocs;
  43    unsigned i;
  44
  45    for (i = 0; i < prog->num_relocs; ++i) {
  46       uint32_t data;
  47
  48       switch (f[i].type) {
  49       case NVC0_FIXUP_CODE_RELOC: data = code_base + f[i].data; break;
  50       case NVC0_FIXUP_DATA_RELOC: data = data_base + f[i].data; break;
  51       default:
  52          data = f[i].data;
  53          break;
  54       }
  55       data = (f[i].shift < 0) ? (data >> -f[i].shift) : (data << f[i].shift);
  56
  57       prog->code[f[i].ofst / 4] &= ~f[i].mask;
  58       prog->code[f[i].ofst / 4] |= data & f[i].mask;
  59    }
  60 }
  61
  62 static void
  63 create_fixup(struct nv_pc *pc, uint8_t ty,
  64              int w, uint32_t data, uint32_t m, int s)
  65 {
  66    struct nvc0_fixup *f;
  67
  68    const unsigned size = sizeof(struct nvc0_fixup);
  69    const unsigned n = pc->num_relocs;
  70
  71    if (!(n % 8))
  72       pc->reloc_entries = REALLOC(pc->reloc_entries, n * size, (n + 8) * size);
  73
  74    f = (struct nvc0_fixup *)pc->reloc_entries;
  75
  76    f[n].ofst = pc->emit_pos + w * 4;
  77    f[n].type = ty;
  78    f[n].data = data;
  79    f[n].mask = m;
  80    f[n].shift = s;
  81
  82    ++pc->num_relocs;
  83 }
  84
  85 static INLINE ubyte
  86 SSIZE(struct nv_instruction *nvi, int s)
  87 {
  88    return nvi->src[s]->value->reg.size;
  89 }
  90
  91 static INLINE ubyte
  92 DSIZE(struct nv_instruction *nvi, int d)
  93 {
  94    return nvi->def[d]->reg.size;
  95 }
  96
  97 static INLINE struct nv_reg *
  98 SREG(struct nv_ref *ref)
  99 {
 100    if (!ref)
 101       return NULL;
 102    return &ref->value->join->reg;
 103 }
 104
 105 static INLINE struct nv_reg *
 106 DREG(struct nv_value *val)
 107 {
 108    if (!val)
 109       return NULL;
 110    return &val->join->reg;
 111 }
 112
 113 static INLINE ubyte
 114 SFILE(struct nv_instruction *nvi, int s)
 115 {
 116    return nvi->src[s]->value->reg.file;
 117 }
 118
 119 static INLINE ubyte
 120 DFILE(struct nv_instruction *nvi, int d)
 121 {
 122    return nvi->def[0]->reg.file;
 123 }
 124
 125 static INLINE void
 126 SID(struct nv_pc *pc, struct nv_ref *ref, int pos)
 127 {
 128    pc->emit[pos / 32] |= (SREG(ref) ? SREG(ref)->id : 63) << (pos % 32);
 129 }
 130
 131 static INLINE void
 132 DID(struct nv_pc *pc, struct nv_value *val, int pos)
 133 {
 134    pc->emit[pos / 32] |= (DREG(val) ? DREG(val)->id : 63) << (pos % 32);
 135 }
 136
 137 static INLINE uint32_t
 138 get_immd_u32(struct nv_ref *ref) /* XXX: dependent on [0]:2 */
 139 {
 140    assert(ref->value->reg.file == NV_FILE_IMM);
 141    return ref->value->reg.imm.u32;
 142 }
 143
 144 static INLINE void
 145 set_immd_u32_l(struct nv_pc *pc, uint32_t u32)
 146 {
 147    pc->emit[0] |= (u32 & 0x3f) << 26;
 148    pc->emit[1] |= u32 >> 6;
 149 }
 150
 151 static INLINE void
 152 set_immd_u32(struct nv_pc *pc, uint32_t u32)
 153 {
 154    if ((pc->emit[0] & 0xf) == 0x2) {
 155       set_immd_u32_l(pc, u32);
 156    } else
 157    if ((pc->emit[0] & 0xf) == 0x3) {
 158       assert(!(pc->emit[1] & 0xc000));
 159       pc->emit[1] |= 0xc000;
 160       assert(!(u32 & 0xfff00000));
 161       set_immd_u32_l(pc, u32);
 162    } else {
 163       assert(!(pc->emit[1] & 0xc000));
 164       pc->emit[1] |= 0xc000;
 165       assert(!(u32 & 0xfff));
 166       set_immd_u32_l(pc, u32 >> 12);
 167    }
 168 }
 169
 170 static INLINE void
 171 set_immd(struct nv_pc *pc, struct nv_instruction *i, int s)
 172 {
 173    set_immd_u32(pc, get_immd_u32(i->src[s]));
 174 }
 175
 176 static INLINE void
 177 DVS(struct nv_pc *pc, struct nv_instruction *i)
 178 {
 179    uint s = i->def[0]->reg.size;
 180    int n;
 181    for (n = 1; n < 4 && i->def[n]; ++n)
 182       s += i->def[n]->reg.size;
 183    pc->emit[0] |= ((s / 4) - 1) << 5;
 184 }
 185
 186 static INLINE void
 187 SVS(struct nv_pc *pc, struct nv_ref *src)
 188 {
 189    pc->emit[0] |= (SREG(src)->size / 4 - 1) << 5;
 190 }
 191
 192 static void
 193 set_pred(struct nv_pc *pc, struct nv_instruction *i)
 194 {
 195    if (i->predicate >= 0) {
 196       SID(pc, i->src[i->predicate], 6);
 197       if (i->cc)
 198          pc->emit[0] |= 0x2000; /* negate */
 199    } else {
 200       pc->emit[0] |= 0x1c00;
 201    }
 202 }
 203
 204 static INLINE void
 205 set_address_16(struct nv_pc *pc, struct nv_ref *src)
 206 {
 207    pc->emit[0] |= (src->value->reg.address & 0x003f) << 26;
 208    pc->emit[1] |= (src->value->reg.address & 0xffc0) >> 6;
 209 }
 210
 211 static INLINE unsigned
 212 const_space_index(struct nv_instruction *i, int s)
 213 {
 214    return SFILE(i, s) - NV_FILE_MEM_C(0);
 215 }
 216
 217 static void
 218 emit_flow(struct nv_pc *pc, struct nv_instruction *i, uint8_t op)
 219 {
 220    pc->emit[0] = 0x00000007;
 221    pc->emit[1] = op << 24;
 222
 223    if (op == 0x40 || (op >= 0x80 && op <= 0x98)) {
 224       /* bra, exit, ret or kil */
 225       pc->emit[0] |= 0x1e0;
 226       set_pred(pc, i);
 227    }
 228
 229    if (i->target) {
 230       int32_t pcrel = i->target->emit_pos - (pc->emit_pos + 8);
 231
 232       /* we will need relocations only for global functions */
 233       /*
 234       create_fixup(pc, NVC0_FIXUP_CODE_RELOC, 0, pos, 26, 0xfc000000);
 235       create_fixup(pc, NVC0_FIXUP_CODE_RELOC, 1, pos, -6, 0x0001ffff);
 236       */
 237
 238       pc->emit[0] |= (pcrel & 0x3f) << 26;
 239       pc->emit[1] |= (pcrel >> 6) & 0x1ffff;
 240    }
 241 }
 242
 243 /* doesn't work for vfetch, export, ld, st, mov ... */
 244 static void
 245 emit_form_0(struct nv_pc *pc, struct nv_instruction *i)
 246 {
 247    int s;
 248
 249    set_pred(pc, i);
 250
 251    DID(pc, i->def[0], 14);
 252
 253    for (s = 0; s < 3 && i->src[s]; ++s) {
 254       if (SFILE(i, s) >= NV_FILE_MEM_C(0) &&
 255           SFILE(i, s) <= NV_FILE_MEM_C(15)) {
 256          assert(!(pc->emit[1] & 0xc000));
 257          assert(s <= 1);
 258          pc->emit[1] |= 0x4000 | (const_space_index(i, s) << 10);
 259          set_address_16(pc, i->src[s]);
 260       } else
 261       if (SFILE(i, s) == NV_FILE_GPR) {
 262          SID(pc, i->src[s], s ? ((s == 2) ? 49 : 26) : 20);
 263       } else
 264       if (SFILE(i, s) == NV_FILE_IMM) {
 265          assert(!(pc->emit[1] & 0xc000));
 266          assert(s == 1 || i->opcode == NV_OP_MOV);
 267          set_immd(pc, i, s);
 268       }
 269    }
 270 }
 271
 272 static void
 273 emit_form_1(struct nv_pc *pc, struct nv_instruction *i)
 274 {
 275    int s;
 276
 277    set_pred(pc, i);
 278
 279    DID(pc, i->def[0], 14);
 280
 281    for (s = 0; s < 1 && i->src[s]; ++s) {
 282       if (SFILE(i, s) >= NV_FILE_MEM_C(0) &&
 283           SFILE(i, s) <= NV_FILE_MEM_C(15)) {
 284          assert(!(pc->emit[1] & 0xc000));
 285          assert(s <= 1);
 286          pc->emit[1] |= 0x4000 | (const_space_index(i, s) << 10);
 287          set_address_16(pc, i->src[s]);
 288       } else
 289       if (SFILE(i, s) == NV_FILE_GPR) {
 290          SID(pc, i->src[s], 26);
 291       } else
 292       if (SFILE(i, s) == NV_FILE_IMM) {
 293          assert(!(pc->emit[1] & 0xc000));
 294          assert(s == 1 || i->opcode == NV_OP_MOV);
 295          set_immd(pc, i, s);
 296       }
 297    }
 298 }
 299
 300 static void
 301 emit_neg_abs_1_2(struct nv_pc *pc, struct nv_instruction *i)
 302 {
 303    if (i->src[0]->mod & NV_MOD_ABS)
 304       pc->emit[0] |= 1 << 7;
 305    if (i->src[0]->mod & NV_MOD_NEG)
 306       pc->emit[0] |= 1 << 9;
 307    if (i->src[1]->mod & NV_MOD_ABS)
 308       pc->emit[0] |= 1 << 6;
 309    if (i->src[1]->mod & NV_MOD_NEG)
 310       pc->emit[0] |= 1 << 8;
 311 }
 312
 313 static void
 314 emit_add_f32(struct nv_pc *pc, struct nv_instruction *i)
 315 {
 316    pc->emit[0] = 0x00000000;
 317    pc->emit[1] = 0x50000000;
 318
 319    emit_form_0(pc, i);
 320
 321    emit_neg_abs_1_2(pc, i);
 322
 323    if (i->saturate)
 324       pc->emit[1] |= 1 << 17;
 325 }
 326
 327 static void
 328 emit_mul_f32(struct nv_pc *pc, struct nv_instruction *i)
 329 {
 330    pc->emit[0] = 0x00000000;
 331    pc->emit[1] = 0x58000000;
 332
 333    emit_form_0(pc, i);
 334
 335    if ((i->src[0]->mod ^ i->src[1]->mod) & NV_MOD_NEG)
 336       pc->emit[1] |= 1 << 25;
 337
 338    if (i->saturate)
 339       pc->emit[0] |= 1 << 5;
 340 }
 341
 342 static void
 343 emit_mad_f32(struct nv_pc *pc, struct nv_instruction *i)
 344 {
 345    pc->emit[0] = 0x00000000;
 346    pc->emit[1] = 0x30000000;
 347
 348    emit_form_0(pc, i);
 349
 350    if ((i->src[0]->mod ^ i->src[1]->mod) & NV_MOD_NEG)
 351       pc->emit[0] |= 1 << 9;
 352
 353    if (i->src[2]->mod & NV_MOD_NEG)
 354       pc->emit[0] |= 1 << 8;
 355
 356    if (i->saturate)
 357       pc->emit[0] |= 1 << 5;
 358 }
 359
 360 static void
 361 emit_minmax(struct nv_pc *pc, struct nv_instruction *i)
 362 {
 363    pc->emit[0] = 0x00000000;
 364    pc->emit[1] = 0x08000000;
 365
 366    if (NV_BASEOP(i->opcode) == NV_OP_MAX)
 367       pc->emit[1] |= 0x001e0000;
 368    else
 369       pc->emit[1] |= 0x000e0000; /* predicate ? */
 370
 371    emit_form_0(pc, i);
 372
 373    emit_neg_abs_1_2(pc, i);
 374
 375    switch (i->opcode) {
 376    case NV_OP_MIN_U32:
 377    case NV_OP_MAX_U32:
 378       pc->emit[0] |= 3;
 379       break;
 380    case NV_OP_MIN_S32:
 381    case NV_OP_MAX_S32:
 382       pc->emit[0] |= 3 | (1 << 5);
 383       break;
 384    case NV_OP_MIN_F32:
 385    case NV_OP_MAX_F32:
 386    default:
 387       break;
 388    }
 389 }
 390
 391 static void
 392 emit_tex(struct nv_pc *pc, struct nv_instruction *i)
 393 {
 394    int src1 = i->tex_array + i->tex_dim + i->tex_cube;
 395
 396    pc->emit[0] = 0x00000086;
 397    pc->emit[1] = 0x80000000;
 398
 399    switch (i->opcode) {
 400    case NV_OP_TEX: pc->emit[1] = 0x80000000; break;
 401    case NV_OP_TXB: pc->emit[1] = 0x84000000; break;
 402    case NV_OP_TXL: pc->emit[1] = 0x86000000; break;
 403    case NV_OP_TXF: pc->emit[1] = 0x90000000; break;
 404    case NV_OP_TXG: pc->emit[1] = 0xe0000000; break;
 405    default:
 406       assert(0);
 407       break;
 408    }
 409
 410    if (i->tex_array)
 411       pc->emit[1] |= 0x00080000; /* layer index is u16, first value of SRC0 */
 412    if (i->tex_shadow)
 413       pc->emit[1] |= 0x01000000; /* shadow is part of SRC1, after bias/lod */
 414
 415    set_pred(pc, i);
 416
 417    DID(pc, i->def[0], 14);
 418    SID(pc, i->src[0], 20);
 419    SID(pc, i->src[src1], 26); /* may be NULL -> $r63 */
 420
 421    pc->emit[1] |= i->tex_mask << 14;
 422    pc->emit[1] |= (i->tex_dim - 1) << 20;
 423    if (i->tex_cube)
 424       pc->emit[1] |= 3 << 20;
 425
 426    assert(i->ext.tex.s < 16);
 427
 428    pc->emit[1] |= i->ext.tex.t;
 429    pc->emit[1] |= i->ext.tex.s << 8;
 430
 431    if (i->tex_live)
 432       pc->emit[0] |= 1 << 9;
 433 }
 434
 435 /* 0: cos, 1: sin, 2: ex2, 3: lg2, 4: rcp, 5: rsqrt */
 436 static void
 437 emit_flop(struct nv_pc *pc, struct nv_instruction *i, ubyte op)
 438 {
 439    pc->emit[0] = 0x00000000;
 440    pc->emit[1] = 0xc8000000;
 441
 442    set_pred(pc, i);
 443
 444    DID(pc, i->def[0], 14);
 445    SID(pc, i->src[0], 20);
 446
 447    pc->emit[0] |= op << 26;
 448
 449    if (op >= 4) {
 450       if (i->src[0]->mod & NV_MOD_NEG) pc->emit[0] |= 1 << 9;
 451       if (i->src[0]->mod & NV_MOD_ABS) pc->emit[0] |= 1 << 7;
 452    } else {
 453       assert(!i->src[0]->mod);
 454    }
 455 }
 456
 457 static void
 458 emit_quadop(struct nv_pc *pc, struct nv_instruction *i)
 459 {
 460    pc->emit[0] = 0x00000000;
 461    pc->emit[1] = 0x48000000;
 462
 463    set_pred(pc, i);
 464
 465    assert(SFILE(i, 0) == NV_FILE_GPR && SFILE(i, 1) == NV_FILE_GPR);
 466
 467    DID(pc, i->def[0], 14);
 468    SID(pc, i->src[0], 20);
 469    SID(pc, i->src[0], 26);
 470
 471    pc->emit[0] |= i->lanes << 6; /* l0, l1, l2, l3, dx, dy */
 472    pc->emit[1] |= i->quadop;
 473 }
 474
 475 static void
 476 emit_ddx(struct nv_pc *pc, struct nv_instruction *i)
 477 {
 478    i->quadop = 0x99;
 479    i->lanes = 4;
 480    emit_quadop(pc, i);
 481 }
 482
 483 static void
 484 emit_ddy(struct nv_pc *pc, struct nv_instruction *i)
 485 {
 486    i->quadop = 0xa5;
 487    i->lanes = 5;
 488    emit_quadop(pc, i);
 489 }
 490
 491 /* preparation op (preex2, presin / convert to fixed point) */
 492 static void
 493 emit_preop(struct nv_pc *pc, struct nv_instruction *i)
 494 {
 495    pc->emit[0] = 0x00000000;
 496    pc->emit[1] = 0x60000000;
 497
 498    if (i->opcode == NV_OP_PREEX2)
 499       pc->emit[0] |= 0x20;
 500
 501    emit_form_1(pc, i);
 502
 503    if (i->src[0]->mod & NV_MOD_NEG) pc->emit[0] |= 1 << 8;
 504    if (i->src[0]->mod & NV_MOD_ABS) pc->emit[0] |= 1 << 6;
 505 }
 506
 507 static void
 508 emit_shift(struct nv_pc *pc, struct nv_instruction *i)
 509 {
 510    pc->emit[0] = 0x00000003;
 511
 512    switch (i->opcode) {
 513    case NV_OP_SAR:
 514       pc->emit[0] |= 0x20; /* fall through */
 515    case NV_OP_SHR:
 516       pc->emit[1] = 0x58000000;
 517       break;
 518    case NV_OP_SHL:
 519    default:
 520       pc->emit[1] = 0x60000000;
 521       break;
 522    }
 523
 524    emit_form_0(pc, i);
 525 }
 526
 527 static void
 528 emit_bitop(struct nv_pc *pc, struct nv_instruction *i)
 529 {
 530    if (SFILE(i, 1) == NV_FILE_IMM) {
 531       pc->emit[0] = 0x00000002;
 532       pc->emit[1] = 0x38000000;
 533    } else {
 534       pc->emit[0] = 0x00000003;
 535       pc->emit[1] = 0x68000000;
 536    }
 537
 538    switch (i->opcode) {
 539    case NV_OP_OR:
 540       pc->emit[0] |= 0x40;
 541       break;
 542    case NV_OP_XOR:
 543       pc->emit[0] |= 0x80;
 544       break;
 545    case NV_OP_AND:
 546    default:
 547       break;
 548    }
 549
 550    emit_form_0(pc, i);
 551 }
 552
 553 static void
 554 emit_set(struct nv_pc *pc, struct nv_instruction *i)
 555 {
 556    pc->emit[0] = 0x00000000;
 557
 558    switch (i->opcode) {
 559    case NV_OP_SET_S32:
 560       pc->emit[0] |= 0x20; /* fall through */
 561    case NV_OP_SET_U32:
 562       pc->emit[0] |= 0x3;
 563       pc->emit[1] = 0x100e0000;
 564       break;
 565    case NV_OP_SET_F32_AND:
 566       pc->emit[1] = 0x18000000;
 567       break;
 568    case NV_OP_SET_F32_OR:
 569       pc->emit[1] = 0x18200000;
 570       break;
 571    case NV_OP_SET_F32_XOR:
 572       pc->emit[1] = 0x18400000;
 573       break;
 574    case NV_OP_FSET_F32:
 575       pc->emit[0] |= 0x20; /* fall through */
 576    case NV_OP_SET_F32:
 577    default:
 578       pc->emit[1] = 0x180e0000;
 579       break;
 580    }
 581
 582    if (DFILE(i, 0) == NV_FILE_PRED) {
 583       pc->emit[0] |= 0x1c000;
 584       pc->emit[1] += 0x08000000;
 585    }
 586
 587    pc->emit[1] |= i->set_cond << 23;
 588
 589    emit_form_0(pc, i);
 590
 591    emit_neg_abs_1_2(pc, i); /* maybe assert that U/S32 don't use mods */
 592 }
 593
 594 static void
 595 emit_selp(struct nv_pc *pc, struct nv_instruction *i)
 596 {
 597    pc->emit[0] = 0x00000004;
 598    pc->emit[1] = 0x20000000;
 599
 600    emit_form_0(pc, i);
 601
 602    if (i->cc || (i->src[2]->mod & NV_MOD_NOT))
 603       pc->emit[1] |= 1 << 20;
 604 }
 605
 606 static void
 607 emit_slct(struct nv_pc *pc, struct nv_instruction *i)
 608 {
 609    pc->emit[0] = 0x00000000;
 610
 611    switch (i->opcode) {
 612    case NV_OP_SLCT_S32:
 613       pc->emit[0] |= 0x20; /* fall through */
 614    case NV_OP_SLCT_U32:
 615       pc->emit[0] |= 0x3;
 616       pc->emit[1] = 0x30000000;
 617       break;
 618    case NV_OP_SLCT_F32:
 619    default:
 620       pc->emit[1] = 0x38000000;
 621       break;
 622    }
 623
 624    emit_form_0(pc, i);
 625
 626    pc->emit[1] |= i->set_cond << 23;
 627 }
 628
 629 static void
 630 emit_cvt(struct nv_pc *pc, struct nv_instruction *i)
 631 {
 632    pc->emit[0] = 0x00000004;
 633    pc->emit[1] = 0x10000000;
 634
 635    if (i->opcode != NV_OP_CVT)
 636       i->ext.cvt.d = i->ext.cvt.s = NV_OPTYPE(i->opcode);
 637
 638    switch (i->ext.cvt.d) {
 639    case NV_TYPE_F32:
 640       switch (i->ext.cvt.s) {
 641       case NV_TYPE_F32: pc->emit[1] = 0x10000000; break;
 642       case NV_TYPE_S32: pc->emit[0] |= 0x200;
 643       case NV_TYPE_U32: pc->emit[1] = 0x18000000; break;
 644       }
 645       break;
 646    case NV_TYPE_S32: pc->emit[0] |= 0x80;
 647    case NV_TYPE_U32:
 648       switch (i->ext.cvt.s) {
 649       case NV_TYPE_F32: pc->emit[1] = 0x14000000; break;
 650       case NV_TYPE_S32: pc->emit[0] |= 0x200;
 651       case NV_TYPE_U32: pc->emit[1] = 0x1c000000; break;
 652       }
 653       break;
 654    default:
 655       assert(!"cvt: unknown type");
 656       break;
 657    }
 658
 659    if (i->opcode == NV_OP_FLOOR)
 660       pc->emit[1] |= 0x00020000;
 661    else
 662    if (i->opcode == NV_OP_CEIL)
 663       pc->emit[1] |= 0x00040000;
 664    else
 665    if (i->opcode == NV_OP_TRUNC)
 666       pc->emit[1] |= 0x00060000;
 667
 668    if (i->saturate || i->opcode == NV_OP_SAT)
 669       pc->emit[0] |= 0x20;
 670
 671    if (NV_BASEOP(i->opcode) == NV_OP_ABS || i->src[0]->mod & NV_MOD_ABS)
 672       pc->emit[0] |= 1 << 6;
 673    if (NV_BASEOP(i->opcode) == NV_OP_NEG || i->src[0]->mod & NV_MOD_NEG)
 674       pc->emit[0] |= 1 << 8;
 675
 676    pc->emit[0] |= util_logbase2(DREG(i->def[0])->size) << 20;
 677    pc->emit[0] |= util_logbase2(SREG(i->src[0])->size) << 23;
 678
 679    emit_form_1(pc, i);
 680 }
 681
 682 static void
 683 emit_interp(struct nv_pc *pc, struct nv_instruction *i)
 684 {
 685    pc->emit[0] = 0x00000000;
 686    pc->emit[1] = 0xc07e0000;
 687
 688    DID(pc, i->def[0], 14);
 689
 690    set_pred(pc, i);
 691
 692    if (i->indirect)
 693       SID(pc, i->src[i->indirect], 20);
 694    else
 695       SID(pc, NULL, 20);
 696
 697    if (i->opcode == NV_OP_PINTERP) {
 698       pc->emit[0] |= 0x040;
 699       SID(pc, i->src[1], 26);
 700    } else {
 701       SID(pc, NULL, 26);
 702    }
 703
 704    pc->emit[1] |= i->src[0]->value->reg.address & 0xffff;
 705
 706    if (i->centroid)
 707       pc->emit[0] |= 0x100;
 708    else
 709    if (i->flat)
 710       pc->emit[0] |= 0x080;
 711 }
 712
 713 static void
 714 emit_vfetch(struct nv_pc *pc, struct nv_instruction *i)
 715 {
 716    pc->emit[0] = 0x03f00006;
 717    pc->emit[1] = 0x06000000 | i->src[0]->value->reg.address;
 718    if (i->patch)
 719       pc->emit[0] |= 0x100;
 720
 721    set_pred(pc, i);
 722
 723    DVS(pc, i);
 724    DID(pc, i->def[0], 14);
 725
 726    SID(pc, (i->indirect >= 0) ? i->src[i->indirect] : NULL, 26);
 727 }
 728
 729 static void
 730 emit_export(struct nv_pc *pc, struct nv_instruction *i)
 731 {
 732    pc->emit[0] = 0x00000006;
 733    pc->emit[1] = 0x0a000000;
 734    if (i->patch)
 735       pc->emit[0] |= 0x100;
 736
 737    set_pred(pc, i);
 738
 739    assert(SFILE(i, 0) == NV_FILE_MEM_V);
 740    assert(SFILE(i, 1) == NV_FILE_GPR);
 741
 742    SID(pc, i->src[1], 26); /* register source */
 743    SVS(pc, i->src[0]);
 744
 745    pc->emit[1] |= i->src[0]->value->reg.address & 0xfff;
 746
 747    SID(pc, (i->indirect >= 0) ? i->src[i->indirect] : NULL, 20);
 748 }
 749
 750 static void
 751 emit_mov(struct nv_pc *pc, struct nv_instruction *i)
 752 {
 753    if (i->opcode == NV_OP_MOV)
 754       i->lanes = 0xf;
 755
 756    if (SFILE(i, 0) == NV_FILE_IMM) {
 757       pc->emit[0] = 0x000001e2;
 758       pc->emit[1] = 0x18000000;
 759    } else
 760    if (SFILE(i, 0) == NV_FILE_PRED) {
 761       pc->emit[0] = 0x1c000004;
 762       pc->emit[1] = 0x080e0000;
 763    } else {
 764       pc->emit[0] = 0x00000004 | (i->lanes << 5);
 765       pc->emit[1] = 0x28000000;
 766    }
 767
 768    emit_form_1(pc, i);
 769 }
 770
 771 static void
 772 emit_ldst_size(struct nv_pc *pc, struct nv_instruction *i)
 773 {
 774    assert(NV_IS_MEMORY_FILE(SFILE(i, 0)));
 775
 776    switch (SSIZE(i, 0)) {
 777    case 1:
 778       if (NV_TYPE_ISSGD(i->ext.cvt.s))
 779          pc->emit[0] |= 0x20;
 780       break;
 781    case 2:
 782       pc->emit[0] |= 0x40;
 783       if (NV_TYPE_ISSGD(i->ext.cvt.s))
 784          pc->emit[0] |= 0x20;
 785       break;
 786    case 4: pc->emit[0] |= 0x80; break;
 787    case 8: pc->emit[0] |= 0xa0; break;
 788    case 16: pc->emit[0] |= 0xc0; break;
 789    default:
 790       NOUVEAU_ERR("invalid load/store size %u\n", SSIZE(i, 0));
 791       break;
 792    }
 793 }
 794
 795 static void
 796 emit_ld_const(struct nv_pc *pc, struct nv_instruction *i)
 797 {
 798    pc->emit[0] = 0x00000006;
 799    pc->emit[1] = 0x14000000 | (const_space_index(i, 0) << 10);
 800
 801    emit_ldst_size(pc, i);
 802
 803    set_pred(pc, i);
 804    set_address_16(pc, i->src[0]);
 805
 806    SID(pc, (i->indirect >= 0) ? i->src[i->indirect] : NULL, 20);
 807    DID(pc, i->def[0], 14);
 808 }
 809
 810 static void
 811 emit_ld(struct nv_pc *pc, struct nv_instruction *i)
 812 {
 813    if (SFILE(i, 0) >= NV_FILE_MEM_C(0) &&
 814        SFILE(i, 0) <= NV_FILE_MEM_C(15)) {
 815       emit_ld_const(pc, i);
 816    } else {
 817       NOUVEAU_ERR("emit_ld(%u): not handled yet\n", SFILE(i, 0));
 818       abort();
 819    }
 820 }
 821
 822 static void
 823 emit_st(struct nv_pc *pc, struct nv_instruction *i)
 824 {
 825    NOUVEAU_ERR("emit_st: not handled yet\n");
 826    abort();
 827 }
 828
 829 void
 830 nvc0_emit_instruction(struct nv_pc *pc, struct nv_instruction *i)
 831 {
 832    debug_printf("EMIT: "); nvc0_print_instruction(i);
 833
 834    switch (i->opcode) {
 835    case NV_OP_VFETCH:
 836       emit_vfetch(pc, i);
 837       break;
 838    case NV_OP_EXPORT:
 839       if (!pc->is_fragprog)
 840          emit_export(pc, i);
 841       break;
 842    case NV_OP_MOV:
 843       emit_mov(pc, i);
 844       break;
 845    case NV_OP_LD:
 846       emit_ld(pc, i);
 847       break;
 848    case NV_OP_ST:
 849       emit_st(pc, i);
 850       break;
 851    case NV_OP_LINTERP:
 852    case NV_OP_PINTERP:
 853       emit_interp(pc, i);
 854       break;
 855    case NV_OP_ADD_F32:
 856       emit_add_f32(pc, i);
 857       break;
 858    case NV_OP_AND:
 859    case NV_OP_OR:
 860    case NV_OP_XOR:
 861       emit_bitop(pc, i);
 862       break;
 863    case NV_OP_CVT:
 864    case NV_OP_ABS_F32:
 865    case NV_OP_ABS_S32:
 866    case NV_OP_NEG_F32:
 867    case NV_OP_NEG_S32:
 868    case NV_OP_SAT:
 869    case NV_OP_CEIL:
 870    case NV_OP_FLOOR:
 871    case NV_OP_TRUNC:
 872       emit_cvt(pc, i);
 873       break;
 874    case NV_OP_DFDX:
 875       emit_ddx(pc, i);
 876       break;
 877    case NV_OP_DFDY:
 878       emit_ddy(pc, i);
 879       break;
 880    case NV_OP_COS:
 881       emit_flop(pc, i, 0);
 882       break;
 883    case NV_OP_SIN:
 884       emit_flop(pc, i, 1);
 885       break;
 886    case NV_OP_EX2:
 887       emit_flop(pc, i, 2);
 888       break;
 889    case NV_OP_LG2:
 890       emit_flop(pc, i, 3);
 891       break;
 892    case NV_OP_RCP:
 893       emit_flop(pc, i, 4);
 894       break;
 895    case NV_OP_RSQ:
 896       emit_flop(pc, i, 5);
 897       break;
 898    case NV_OP_PRESIN:
 899    case NV_OP_PREEX2:
 900       emit_preop(pc, i);
 901       break;
 902    case NV_OP_MAD_F32:
 903       emit_mad_f32(pc, i);
 904       break;
 905    case NV_OP_MAX_F32:
 906    case NV_OP_MAX_S32:
 907    case NV_OP_MAX_U32:
 908    case NV_OP_MIN_F32:
 909    case NV_OP_MIN_S32:
 910    case NV_OP_MIN_U32:
 911       emit_minmax(pc, i);
 912       break;
 913    case NV_OP_MUL_F32:
 914       emit_mul_f32(pc, i);
 915       break;
 916    case NV_OP_SET_F32:
 917    case NV_OP_SET_F32_AND:
 918    case NV_OP_SET_F32_OR:
 919    case NV_OP_SET_F32_XOR:
 920    case NV_OP_SET_S32:
 921    case NV_OP_SET_U32:
 922    case NV_OP_FSET_F32:
 923       emit_set(pc, i);
 924       break;
 925    case NV_OP_SHL:
 926    case NV_OP_SHR:
 927    case NV_OP_SAR:
 928       emit_shift(pc, i);
 929       break;
 930    case NV_OP_TEX:
 931    case NV_OP_TXB:
 932    case NV_OP_TXL:
 933       emit_tex(pc, i);
 934       break;
 935    case NV_OP_BRA:
 936       emit_flow(pc, i, 0x40);
 937       break;
 938    case NV_OP_CALL:
 939       emit_flow(pc, i, 0x50);
 940       break;
 941    case NV_OP_JOINAT:
 942       emit_flow(pc, i, 0x60);
 943       break;
 944    case NV_OP_EXIT:
 945       emit_flow(pc, i, 0x80);
 946       break;
 947    case NV_OP_RET:
 948       emit_flow(pc, i, 0x90);
 949       break;
 950    case NV_OP_KIL:
 951       emit_flow(pc, i, 0x98);
 952       break;
 953    case NV_OP_JOIN:
 954    case NV_OP_NOP:
 955       pc->emit[0] = 0x00003de4;
 956       pc->emit[1] = 0x40000000;
 957       break;
 958    case NV_OP_SELP:
 959       emit_selp(pc, i);
 960       break;
 961    case NV_OP_SLCT_F32:
 962    case NV_OP_SLCT_S32:
 963    case NV_OP_SLCT_U32:
 964       emit_slct(pc, i);
 965       break;
 966    default:
 967       NOUVEAU_ERR("unhandled NV_OP: %d\n", i->opcode);
 968       abort();
 969       break;
 970    }
 971
 972    if (i->join)
 973       pc->emit[0] |= 0x10;
 974 }