projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium: add TGSI_SEMANTIC_TEXCOORD,PCOORD v3
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "nvc0_context.h"
26
27 #include "nv50/codegen/nv50_ir_driver.h"
28 #include "nve4_compute.h"
29
30 static uint32_t
31 nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
32 {
33 switch (sn) {
34 case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
35 case TGSI_SEMANTIC_PRIMID: return 0x060;
36 case TGSI_SEMANTIC_PSIZE: return 0x06c;
37 case TGSI_SEMANTIC_POSITION: return 0x070;
38 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
39 case TGSI_SEMANTIC_FOG: return 0x270;
40 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
41 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
42 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
43 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
44 case TGSI_SEMANTIC_CLIPVERTEX: return 0x260;
45 case TGSI_SEMANTIC_PCOORD: return 0x2e0;
46 case NV50_SEMANTIC_TESSCOORD: return 0x2f0;
47 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
48 case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
49 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
50 case TGSI_SEMANTIC_FACE: return 0x3fc;
51 case NV50_SEMANTIC_INVOCATIONID: return ~0;
52 default:
53 assert(!"invalid TGSI input semantic");
54 return ~0;
55 }
56 }
57
58 static uint32_t
59 nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
60 {
61 switch (sn) {
62 case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
63 case TGSI_SEMANTIC_PRIMID: return 0x060;
64 case NV50_SEMANTIC_LAYER: return 0x064;
65 case NV50_SEMANTIC_VIEWPORTINDEX: return 0x068;
66 case TGSI_SEMANTIC_PSIZE: return 0x06c;
67 case TGSI_SEMANTIC_POSITION: return 0x070;
68 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
69 case TGSI_SEMANTIC_FOG: return 0x270;
70 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
71 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
72 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
73 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
74 case TGSI_SEMANTIC_CLIPVERTEX: return 0x260;
75 case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
76 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
77 default:
78 assert(!"invalid TGSI output semantic");
79 return ~0;
80 }
81 }
82
83 static int
84 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
85 {
86 unsigned i, c, n;
87
88 for (n = 0, i = 0; i < info->numInputs; ++i) {
89 switch (info->in[i].sn) {
90 case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
91 case TGSI_SEMANTIC_VERTEXID:
92 info->in[i].mask = 0x1;
93 info->in[i].slot[0] =
94 nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
95 continue;
96 default:
97 break;
98 }
99 for (c = 0; c < 4; ++c)
100 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
101 ++n;
102 }
103
104 return 0;
105 }
106
107 static int
108 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
109 {
110 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
111 unsigned offset;
112 unsigned i, c;
113
114 for (i = 0; i < info->numInputs; ++i) {
115 offset = nvc0_shader_input_address(info->in[i].sn,
116 info->in[i].si, ubase);
117 if (info->in[i].patch && offset >= 0x20)
118 offset = 0x20 + info->in[i].si * 0x10;
119
120 if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD)
121 info->in[i].mask &= 3;
122
123 for (c = 0; c < 4; ++c)
124 info->in[i].slot[c] = (offset + c * 0x4) / 4;
125 }
126
127 return 0;
128 }
129
130 static int
131 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
132 {
133 unsigned count = info->prop.fp.numColourResults * 4;
134 unsigned i, c;
135
136 for (i = 0; i < info->numOutputs; ++i)
137 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
138 for (c = 0; c < 4; ++c)
139 info->out[i].slot[c] = info->out[i].si * 4 + c;
140
141 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
142 info->out[info->io.sampleMask].slot[0] = count++;
143 else
144 if (info->target >= 0xe0)
145 count++; /* on Kepler, depth is always last colour reg + 2 */
146
147 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
148 info->out[info->io.fragDepth].slot[2] = count;
149
150 return 0;
151 }
152
153 static int
154 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
155 {
156 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
157 unsigned offset;
158 unsigned i, c;
159
160 for (i = 0; i < info->numOutputs; ++i) {
161 offset = nvc0_shader_output_address(info->out[i].sn,
162 info->out[i].si, ubase);
163 if (info->out[i].patch && offset >= 0x20)
164 offset = 0x20 + info->out[i].si * 0x10;
165
166 for (c = 0; c < 4; ++c)
167 info->out[i].slot[c] = (offset + c * 0x4) / 4;
168 }
169
170 return 0;
171 }
172
173 static int
174 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
175 {
176 int ret;
177
178 if (info->type == PIPE_SHADER_VERTEX)
179 ret = nvc0_vp_assign_input_slots(info);
180 else
181 ret = nvc0_sp_assign_input_slots(info);
182 if (ret)
183 return ret;
184
185 if (info->type == PIPE_SHADER_FRAGMENT)
186 ret = nvc0_fp_assign_output_slots(info);
187 else
188 ret = nvc0_sp_assign_output_slots(info);
189 return ret;
190 }
191
192 static INLINE void
193 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
194 {
195 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
196 uint8_t max = (vp->hdr[4] >> 24);
197
198 min = MIN2(min, slot);
199 max = MAX2(max, slot);
200
201 vp->hdr[4] = (max << 24) | (min << 12);
202 }
203
204 /* Common part of header generation for VP, TCP, TEP and GP. */
205 static int
206 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
207 {
208 unsigned i, c, a;
209
210 for (i = 0; i < info->numInputs; ++i) {
211 if (info->in[i].patch)
212 continue;
213 for (c = 0; c < 4; ++c) {
214 a = info->in[i].slot[c];
215 if (info->in[i].mask & (1 << c)) {
216 if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD)
217 vp->hdr[5 + a / 32] |= 1 << (a % 32);
218 else
219 nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]);
220 }
221 }
222 }
223
224 for (i = 0; i < info->numOutputs; ++i) {
225 if (info->out[i].patch)
226 continue;
227 for (c = 0; c < 4; ++c) {
228 if (!(info->out[i].mask & (1 << c)))
229 continue;
230 assert(info->out[i].slot[c] >= 0x40 / 4);
231 a = info->out[i].slot[c] - 0x40 / 4;
232 vp->hdr[13 + a / 32] |= 1 << (a % 32);
233 if (info->out[i].oread)
234 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
235 }
236 }
237
238 for (i = 0; i < info->numSysVals; ++i) {
239 switch (info->sv[i].sn) {
240 case TGSI_SEMANTIC_PRIMID:
241 vp->hdr[5] |= 1 << 24;
242 break;
243 case TGSI_SEMANTIC_INSTANCEID:
244 vp->hdr[10] |= 1 << 30;
245 break;
246 case TGSI_SEMANTIC_VERTEXID:
247 vp->hdr[10] |= 1 << 31;
248 break;
249 default:
250 break;
251 }
252 }
253
254 vp->vp.clip_enable = info->io.clipDistanceMask;
255 for (i = 0; i < 8; ++i)
256 if (info->io.cullDistanceMask & (1 << i))
257 vp->vp.clip_mode |= 1 << (i * 4);
258
259 if (info->io.genUserClip < 0)
260 vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
261
262 return 0;
263 }
264
265 static int
266 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
267 {
268 vp->hdr[0] = 0x20061 | (1 << 10);
269 vp->hdr[4] = 0xff000;
270
271 vp->hdr[18] = info->io.clipDistanceMask;
272
273 return nvc0_vtgp_gen_header(vp, info);
274 }
275
276 #if defined(PIPE_SHADER_HULL) || defined(PIPE_SHADER_DOMAIN)
277 static void
278 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
279 {
280 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
281 tp->tp.tess_mode = ~0;
282 return;
283 }
284 switch (info->prop.tp.domain) {
285 case PIPE_PRIM_LINES:
286 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
287 break;
288 case PIPE_PRIM_TRIANGLES:
289 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
290 if (info->prop.tp.winding > 0)
291 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
292 break;
293 case PIPE_PRIM_QUADS:
294 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
295 break;
296 default:
297 tp->tp.tess_mode = ~0;
298 return;
299 }
300 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
301 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
302
303 switch (info->prop.tp.partitioning) {
304 case PIPE_TESS_PART_INTEGER:
305 case PIPE_TESS_PART_POW2:
306 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
307 break;
308 case PIPE_TESS_PART_FRACT_ODD:
309 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
310 break;
311 case PIPE_TESS_PART_FRACT_EVEN:
312 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
313 break;
314 default:
315 assert(!"invalid tessellator partitioning");
316 break;
317 }
318 }
319 #endif
320
321 #ifdef PIPE_SHADER_HULL
322 static int
323 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
324 {
325 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
326
327 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
328
329 if (info->numPatchConstants)
330 opcs = 8 + info->numPatchConstants * 4;
331
332 tcp->hdr[0] = 0x20061 | (2 << 10);
333
334 tcp->hdr[1] = opcs << 24;
335 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
336
337 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
338
339 nvc0_vtgp_gen_header(tcp, info);
340
341 nvc0_tp_get_tess_mode(tcp, info);
342
343 return 0;
344 }
345 #endif
346
347 #ifdef PIPE_SHADER_DOMAIN
348 static int
349 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
350 {
351 tep->tp.input_patch_size = ~0;
352
353 tep->hdr[0] = 0x20061 | (3 << 10);
354 tep->hdr[4] = 0xff000;
355
356 nvc0_vtgp_gen_header(tep, info);
357
358 nvc0_tp_get_tess_mode(tep, info);
359
360 tep->hdr[18] |= 0x3 << 12; /* ? */
361
362 return 0;
363 }
364 #endif
365
366 static int
367 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
368 {
369 gp->hdr[0] = 0x20061 | (4 << 10);
370
371 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
372
373 switch (info->prop.gp.outputPrim) {
374 case PIPE_PRIM_POINTS:
375 gp->hdr[3] = 0x01000000;
376 gp->hdr[0] |= 0xf0000000;
377 break;
378 case PIPE_PRIM_LINE_STRIP:
379 gp->hdr[3] = 0x06000000;
380 gp->hdr[0] |= 0x10000000;
381 break;
382 case PIPE_PRIM_TRIANGLE_STRIP:
383 gp->hdr[3] = 0x07000000;
384 gp->hdr[0] |= 0x10000000;
385 break;
386 default:
387 assert(0);
388 break;
389 }
390
391 gp->hdr[4] = info->prop.gp.maxVertices & 0x1ff;
392
393 return nvc0_vtgp_gen_header(gp, info);
394 }
395
396 #define NVC0_INTERP_FLAT (1 << 0)
397 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
398 #define NVC0_INTERP_LINEAR (3 << 0)
399 #define NVC0_INTERP_CENTROID (1 << 2)
400
401 static uint8_t
402 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
403 {
404 if (var->linear)
405 return NVC0_INTERP_LINEAR;
406 if (var->flat)
407 return NVC0_INTERP_FLAT;
408 return NVC0_INTERP_PERSPECTIVE;
409 }
410
411 static int
412 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
413 {
414 unsigned i, c, a, m;
415
416 /* just 00062 on Kepler */
417 fp->hdr[0] = 0x20062 | (5 << 10);
418 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
419
420 if (info->prop.fp.usesDiscard)
421 fp->hdr[0] |= 0x8000;
422 if (info->prop.fp.numColourResults > 1)
423 fp->hdr[0] |= 0x4000;
424 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
425 fp->hdr[19] |= 0x1;
426 if (info->prop.fp.writesDepth) {
427 fp->hdr[19] |= 0x2;
428 fp->flags[0] = 0x11; /* deactivate ZCULL */
429 }
430
431 for (i = 0; i < info->numInputs; ++i) {
432 m = nvc0_hdr_interp_mode(&info->in[i]);
433 for (c = 0; c < 4; ++c) {
434 if (!(info->in[i].mask & (1 << c)))
435 continue;
436 a = info->in[i].slot[c];
437 if (info->in[i].slot[0] >= (0x060 / 4) &&
438 info->in[i].slot[0] <= (0x07c / 4)) {
439 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
440 } else
441 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
442 info->in[i].slot[0] <= (0x2fc / 4)) {
443 fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x03ff0000;
444 } else {
445 if (info->in[i].slot[c] < (0x040 / 4) ||
446 info->in[i].slot[c] > (0x380 / 4))
447 continue;
448 a *= 2;
449 if (info->in[i].slot[0] >= (0x300 / 4))
450 a -= 32;
451 fp->hdr[4 + a / 32] |= m << (a % 32);
452 }
453 }
454 }
455
456 for (i = 0; i < info->numOutputs; ++i) {
457 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
458 fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
459 }
460
461 fp->fp.early_z = info->prop.fp.earlyFragTests;
462
463 return 0;
464 }
465
466 static struct nvc0_transform_feedback_state *
467 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
468 const struct pipe_stream_output_info *pso)
469 {
470 struct nvc0_transform_feedback_state *tfb;
471 unsigned b, i, c;
472
473 tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
474 if (!tfb)
475 return NULL;
476 for (b = 0; b < 4; ++b) {
477 tfb->stride[b] = pso->stride[b] * 4;
478 tfb->varying_count[b] = 0;
479 }
480 memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
481
482 for (i = 0; i < pso->num_outputs; ++i) {
483 unsigned s = pso->output[i].start_component;
484 unsigned p = pso->output[i].dst_offset;
485 b = pso->output[i].output_buffer;
486
487 for (c = 0; c < pso->output[i].num_components; ++c)
488 tfb->varying_index[b][p++] =
489 info->out[pso->output[i].register_index].slot[s + c];
490
491 tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
492 }
493 for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
494 for (c = tfb->varying_count[b]; c & 3; ++c)
495 tfb->varying_index[b][c] = 0;
496
497 return tfb;
498 }
499
500 #ifdef DEBUG
501 static void
502 nvc0_program_dump(struct nvc0_program *prog)
503 {
504 unsigned pos;
505
506 if (prog->type != PIPE_SHADER_COMPUTE) {
507 for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
508 debug_printf("HDR[%02lx] = 0x%08x\n",
509 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
510 }
511 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
512 for (pos = 0; pos < prog->code_size / 4; ++pos) {
513 if ((pos % 8) == 0)
514 debug_printf("\n");
515 debug_printf("%08x ", prog->code[pos]);
516 }
517 debug_printf("\n");
518 }
519 #endif
520
521 boolean
522 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
523 {
524 struct nv50_ir_prog_info *info;
525 int ret;
526
527 info = CALLOC_STRUCT(nv50_ir_prog_info);
528 if (!info)
529 return FALSE;
530
531 info->type = prog->type;
532 info->target = chipset;
533 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
534 info->bin.source = (void *)prog->pipe.tokens;
535
536 info->io.genUserClip = prog->vp.num_ucps;
537 info->io.ucpBase = 256;
538 info->io.ucpCBSlot = 15;
539
540 if (prog->type == PIPE_SHADER_COMPUTE) {
541 if (chipset >= NVISA_GK104_CHIPSET) {
542 info->io.resInfoCBSlot = 0;
543 info->io.texBindBase = NVE4_CP_INPUT_TEX(0);
544 info->io.suInfoBase = NVE4_CP_INPUT_SUF(0);
545 info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0);
546 }
547 info->io.msInfoCBSlot = 0;
548 info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS;
549 } else {
550 if (chipset >= NVISA_GK104_CHIPSET) {
551 info->io.resInfoCBSlot = 15;
552 info->io.texBindBase = 0x20;
553 info->io.suInfoBase = 0; /* TODO */
554 }
555 info->io.msInfoCBSlot = 15;
556 info->io.msInfoBase = 0; /* TODO */
557 }
558
559 info->assignSlots = nvc0_program_assign_varying_slots;
560
561 #ifdef DEBUG
562 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
563 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
564 #else
565 info->optLevel = 3;
566 #endif
567
568 ret = nv50_ir_generate_code(info);
569 if (ret) {
570 NOUVEAU_ERR("shader translation failed: %i\n", ret);
571 goto out;
572 }
573 if (prog->type != PIPE_SHADER_COMPUTE)
574 FREE(info->bin.syms);
575
576 prog->code = info->bin.code;
577 prog->code_size = info->bin.codeSize;
578 prog->immd_data = info->immd.buf;
579 prog->immd_size = info->immd.bufSize;
580 prog->relocs = info->bin.relocData;
581 prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
582 prog->num_barriers = info->numBarriers;
583
584 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
585
586 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
587 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
588 prog->vp.edgeflag = info->io.edgeFlagIn;
589
590 switch (prog->type) {
591 case PIPE_SHADER_VERTEX:
592 ret = nvc0_vp_gen_header(prog, info);
593 break;
594 #ifdef PIPE_SHADER_HULL
595 case PIPE_SHADER_HULL:
596 ret = nvc0_tcp_gen_header(prog, info);
597 break;
598 #endif
599 #ifdef PIPE_SHADER_DOMAIN
600 case PIPE_SHADER_DOMAIN:
601 ret = nvc0_tep_gen_header(prog, info);
602 break;
603 #endif
604 case PIPE_SHADER_GEOMETRY:
605 ret = nvc0_gp_gen_header(prog, info);
606 break;
607 case PIPE_SHADER_FRAGMENT:
608 ret = nvc0_fp_gen_header(prog, info);
609 break;
610 case PIPE_SHADER_COMPUTE:
611 prog->cp.syms = info->bin.syms;
612 prog->cp.num_syms = info->bin.numSyms;
613 break;
614 default:
615 ret = -1;
616 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
617 break;
618 }
619 if (ret)
620 goto out;
621
622 if (info->bin.tlsSpace) {
623 assert(info->bin.tlsSpace < (1 << 24));
624 prog->hdr[0] |= 1 << 26;
625 prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
626 prog->need_tls = TRUE;
627 }
628 /* TODO: factor 2 only needed where joinat/precont is used,
629 * and we only have to count non-uniform branches
630 */
631 /*
632 if ((info->maxCFDepth * 2) > 16) {
633 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
634 prog->need_tls = TRUE;
635 }
636 */
637 if (info->io.globalAccess)
638 prog->hdr[0] |= 1 << 16;
639
640 if (prog->pipe.stream_output.num_outputs)
641 prog->tfb = nvc0_program_create_tfb_state(info,
642 &prog->pipe.stream_output);
643
644 out:
645 FREE(info);
646 return !ret;
647 }
648
649 boolean
650 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
651 {
652 struct nvc0_screen *screen = nvc0->screen;
653 const boolean is_cp = prog->type == PIPE_SHADER_COMPUTE;
654 int ret;
655 uint32_t size = prog->code_size + (is_cp ? 0 : NVC0_SHADER_HEADER_SIZE);
656 uint32_t lib_pos = screen->lib_code->start;
657 uint32_t code_pos;
658
659 /* c[] bindings need to be aligned to 0x100, but we could use relocations
660 * to save space. */
661 if (prog->immd_size) {
662 prog->immd_base = size;
663 size = align(size, 0x40);
664 size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
665 }
666 /* On Fermi, SP_START_ID must be aligned to 0x40.
667 * On Kepler, the first instruction must be aligned to 0x80 because
668 * latency information is expected only at certain positions.
669 */
670 if (screen->base.class_3d >= NVE4_3D_CLASS)
671 size = size + (is_cp ? 0x40 : 0x70);
672 size = align(size, 0x40);
673
674 ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
675 if (ret) {
676 struct nouveau_heap *heap = screen->text_heap;
677 struct nouveau_heap *iter;
678 for (iter = heap; iter && iter->next != heap; iter = iter->next) {
679 struct nvc0_program *evict = iter->priv;
680 if (evict)
681 nouveau_heap_free(&evict->mem);
682 }
683 debug_printf("WARNING: out of code space, evicting all shaders.\n");
684 ret = nouveau_heap_alloc(heap, size, prog, &prog->mem);
685 if (ret) {
686 NOUVEAU_ERR("shader too large (0x%x) to fit in code space ?\n", size);
687 return FALSE;
688 }
689 IMMED_NVC0(nvc0->base.pushbuf, NVC0_3D(SERIALIZE), 0);
690 }
691 prog->code_base = prog->mem->start;
692 prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
693 assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
694 prog->mem->start + prog->mem->size));
695
696 if (!is_cp) {
697 if (screen->base.class_3d >= NVE4_3D_CLASS) {
698 switch (prog->mem->start & 0xff) {
699 case 0x40: prog->code_base += 0x70; break;
700 case 0x80: prog->code_base += 0x30; break;
701 case 0xc0: prog->code_base += 0x70; break;
702 default:
703 prog->code_base += 0x30;
704 assert((prog->mem->start & 0xff) == 0x00);
705 break;
706 }
707 }
708 code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
709 } else {
710 if (screen->base.class_3d >= NVE4_3D_CLASS) {
711 if (prog->mem->start & 0x40)
712 prog->code_base += 0x40;
713 assert((prog->code_base & 0x7f) == 0x00);
714 }
715 code_pos = prog->code_base;
716 }
717
718 if (prog->relocs)
719 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
720
721 #ifdef DEBUG
722 if (debug_get_bool_option("NV50_PROG_DEBUG", FALSE))
723 nvc0_program_dump(prog);
724 #endif
725
726 if (!is_cp)
727 nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
728 NOUVEAU_BO_VRAM, NVC0_SHADER_HEADER_SIZE, prog->hdr);
729 nvc0->base.push_data(&nvc0->base, screen->text, code_pos,
730 NOUVEAU_BO_VRAM, prog->code_size, prog->code);
731 if (prog->immd_size)
732 nvc0->base.push_data(&nvc0->base,
733 screen->text, prog->immd_base, NOUVEAU_BO_VRAM,
734 prog->immd_size, prog->immd_data);
735
736 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
737 PUSH_DATA (nvc0->base.pushbuf, 0x1011);
738
739 return TRUE;
740 }
741
742 /* Upload code for builtin functions like integer division emulation. */
743 void
744 nvc0_program_library_upload(struct nvc0_context *nvc0)
745 {
746 struct nvc0_screen *screen = nvc0->screen;
747 int ret;
748 uint32_t size;
749 const uint32_t *code;
750
751 if (screen->lib_code)
752 return;
753
754 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
755 if (!size)
756 return;
757
758 ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
759 &screen->lib_code);
760 if (ret)
761 return;
762
763 nvc0->base.push_data(&nvc0->base,
764 screen->text, screen->lib_code->start, NOUVEAU_BO_VRAM,
765 size, code);
766 /* no need for a memory barrier, will be emitted with first program */
767 }
768
769 void
770 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
771 {
772 const struct pipe_shader_state pipe = prog->pipe;
773 const ubyte type = prog->type;
774
775 if (prog->mem)
776 nouveau_heap_free(&prog->mem);
777
778 FREE(prog->code);
779 FREE(prog->immd_data);
780 FREE(prog->relocs);
781 if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
782 FREE(prog->cp.syms);
783 if (prog->tfb) {
784 if (nvc0->state.tfb == prog->tfb)
785 nvc0->state.tfb = NULL;
786 FREE(prog->tfb);
787 }
788
789 memset(prog, 0, sizeof(*prog));
790
791 prog->pipe = pipe;
792 prog->type = type;
793 }
794
795 uint32_t
796 nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
797 {
798 const struct nv50_ir_prog_symbol *syms =
799 (const struct nv50_ir_prog_symbol *)prog->cp.syms;
800 unsigned base = 0;
801 unsigned i;
802 if (prog->type != PIPE_SHADER_COMPUTE)
803 base = NVC0_SHADER_HEADER_SIZE;
804 for (i = 0; i < prog->cp.num_syms; ++i)
805 if (syms[i].label == label)
806 return prog->code_base + base + syms[i].offset;
807 return ~0;
808 }