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[mesa.git] / src / gallium / drivers / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "nvc0_context.h"
26
27 #include "nv50/codegen/nv50_ir_driver.h"
28
29 /* If only they told use the actual semantic instead of just GENERIC ... */
30 static void
31 nvc0_mesa_varying_hack(struct nv50_ir_varying *var)
32 {
33 unsigned c;
34
35 if (var->sn != TGSI_SEMANTIC_GENERIC)
36 return;
37
38 if (var->si <= 7) /* gl_TexCoord */
39 for (c = 0; c < 4; ++c)
40 var->slot[c] = (0x300 + var->si * 0x10 + c * 0x4) / 4;
41 else
42 if (var->si == 9) /* gl_PointCoord */
43 for (c = 0; c < 4; ++c)
44 var->slot[c] = (0x2e0 + c * 0x4) / 4;
45 else
46 for (c = 0; c < 4; ++c) /* move down user varyings (first has index 8) */
47 var->slot[c] -= 0x80 / 4;
48 }
49
50 static uint32_t
51 nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
52 {
53 switch (sn) {
54 case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
55 case TGSI_SEMANTIC_PRIMID: return 0x060;
56 case TGSI_SEMANTIC_PSIZE: return 0x06c;
57 case TGSI_SEMANTIC_POSITION: return 0x070;
58 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
59 case TGSI_SEMANTIC_FOG: return 0x270;
60 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
61 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
62 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
63 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
64 case TGSI_SEMANTIC_CLIPVERTEX: return 0x260;
65 case NV50_SEMANTIC_POINTCOORD: return 0x2e0;
66 case NV50_SEMANTIC_TESSCOORD: return 0x2f0;
67 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
68 case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
69 case NV50_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
70 case TGSI_SEMANTIC_FACE: return 0x3fc;
71 case NV50_SEMANTIC_INVOCATIONID: return ~0;
72 default:
73 assert(!"invalid TGSI input semantic");
74 return ~0;
75 }
76 }
77
78 static uint32_t
79 nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
80 {
81 switch (sn) {
82 case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
83 case TGSI_SEMANTIC_PRIMID: return 0x060;
84 case NV50_SEMANTIC_LAYER: return 0x064;
85 case NV50_SEMANTIC_VIEWPORTINDEX: return 0x068;
86 case TGSI_SEMANTIC_PSIZE: return 0x06c;
87 case TGSI_SEMANTIC_POSITION: return 0x070;
88 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
89 case TGSI_SEMANTIC_FOG: return 0x270;
90 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
91 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
92 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
93 case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
94 case TGSI_SEMANTIC_CLIPVERTEX: return 0x260;
95 case NV50_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
96 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
97 default:
98 assert(!"invalid TGSI output semantic");
99 return ~0;
100 }
101 }
102
103 static int
104 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
105 {
106 unsigned i, c, n;
107
108 for (n = 0, i = 0; i < info->numInputs; ++i) {
109 switch (info->in[i].sn) {
110 case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
111 case TGSI_SEMANTIC_VERTEXID:
112 info->in[i].mask = 0x1;
113 info->in[i].slot[0] =
114 nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
115 continue;
116 default:
117 break;
118 }
119 for (c = 0; c < 4; ++c)
120 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
121 ++n;
122 }
123
124 return 0;
125 }
126
127 static int
128 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
129 {
130 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
131 unsigned offset;
132 unsigned i, c;
133
134 for (i = 0; i < info->numInputs; ++i) {
135 offset = nvc0_shader_input_address(info->in[i].sn,
136 info->in[i].si, ubase);
137 if (info->in[i].patch && offset >= 0x20)
138 offset = 0x20 + info->in[i].si * 0x10;
139
140 if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD)
141 info->in[i].mask &= 3;
142
143 for (c = 0; c < 4; ++c)
144 info->in[i].slot[c] = (offset + c * 0x4) / 4;
145
146 nvc0_mesa_varying_hack(&info->in[i]);
147 }
148
149 return 0;
150 }
151
152 static int
153 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
154 {
155 unsigned last = info->prop.fp.numColourResults * 4;
156 unsigned i, c;
157
158 for (i = 0; i < info->numOutputs; ++i)
159 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
160 for (c = 0; c < 4; ++c)
161 info->out[i].slot[c] = info->out[i].si * 4 + c;
162
163 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
164 info->out[info->io.sampleMask].slot[0] = last++;
165
166 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
167 info->out[info->io.fragDepth].slot[2] = last;
168
169 return 0;
170 }
171
172 static int
173 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
174 {
175 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
176 unsigned offset;
177 unsigned i, c;
178
179 for (i = 0; i < info->numOutputs; ++i) {
180 offset = nvc0_shader_output_address(info->out[i].sn,
181 info->out[i].si, ubase);
182 if (info->out[i].patch && offset >= 0x20)
183 offset = 0x20 + info->out[i].si * 0x10;
184
185 for (c = 0; c < 4; ++c)
186 info->out[i].slot[c] = (offset + c * 0x4) / 4;
187
188 nvc0_mesa_varying_hack(&info->out[i]);
189 }
190
191 return 0;
192 }
193
194 static int
195 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
196 {
197 int ret;
198
199 if (info->type == PIPE_SHADER_VERTEX)
200 ret = nvc0_vp_assign_input_slots(info);
201 else
202 ret = nvc0_sp_assign_input_slots(info);
203 if (ret)
204 return ret;
205
206 if (info->type == PIPE_SHADER_FRAGMENT)
207 ret = nvc0_fp_assign_output_slots(info);
208 else
209 ret = nvc0_sp_assign_output_slots(info);
210 return ret;
211 }
212
213 static INLINE void
214 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
215 {
216 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
217 uint8_t max = (vp->hdr[4] >> 24);
218
219 min = MIN2(min, slot);
220 max = MAX2(max, slot);
221
222 vp->hdr[4] = (max << 24) | (min << 12);
223 }
224
225 /* Common part of header generation for VP, TCP, TEP and GP. */
226 static int
227 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
228 {
229 unsigned i, c, a;
230
231 for (i = 0; i < info->numInputs; ++i) {
232 if (info->in[i].patch)
233 continue;
234 for (c = 0; c < 4; ++c) {
235 a = info->in[i].slot[c];
236 if (info->in[i].mask & (1 << c)) {
237 if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD)
238 vp->hdr[5 + a / 32] |= 1 << (a % 32);
239 else
240 nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]);
241 }
242 }
243 }
244
245 for (i = 0; i < info->numOutputs; ++i) {
246 if (info->out[i].patch)
247 continue;
248 for (c = 0; c < 4; ++c) {
249 if (!(info->out[i].mask & (1 << c)))
250 continue;
251 assert(info->out[i].slot[c] >= 0x40 / 4);
252 a = info->out[i].slot[c] - 0x40 / 4;
253 vp->hdr[13 + a / 32] |= 1 << (a % 32);
254 if (info->out[i].oread)
255 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
256 }
257 }
258
259 for (i = 0; i < info->numSysVals; ++i) {
260 switch (info->sv[i].sn) {
261 case TGSI_SEMANTIC_PRIMID:
262 vp->hdr[5] |= 1 << 24;
263 break;
264 case TGSI_SEMANTIC_INSTANCEID:
265 vp->hdr[10] |= 1 << 30;
266 break;
267 case TGSI_SEMANTIC_VERTEXID:
268 vp->hdr[10] |= 1 << 31;
269 break;
270 default:
271 break;
272 }
273 }
274
275 vp->vp.clip_enable = info->io.clipDistanceMask;
276 for (i = 0; i < 8; ++i)
277 if (info->io.cullDistanceMask & (1 << i))
278 vp->vp.clip_mode |= 1 << (i * 4);
279
280 if (info->io.genUserClip < 0)
281 vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES; /* prevent rebuilding */
282
283 return 0;
284 }
285
286 static int
287 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
288 {
289 vp->hdr[0] = 0x20061 | (1 << 10);
290 vp->hdr[4] = 0xff000;
291
292 vp->hdr[18] = info->io.clipDistanceMask;
293
294 return nvc0_vtgp_gen_header(vp, info);
295 }
296
297 #if defined(PIPE_SHADER_HULL) || defined(PIPE_SHADER_DOMAIN)
298 static void
299 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
300 {
301 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
302 tp->tp.tess_mode = ~0;
303 return;
304 }
305 switch (info->prop.tp.domain) {
306 case PIPE_PRIM_LINES:
307 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
308 break;
309 case PIPE_PRIM_TRIANGLES:
310 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
311 if (info->prop.tp.winding > 0)
312 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
313 break;
314 case PIPE_PRIM_QUADS:
315 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
316 break;
317 default:
318 tp->tp.tess_mode = ~0;
319 return;
320 }
321 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
322 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
323
324 switch (info->prop.tp.partitioning) {
325 case PIPE_TESS_PART_INTEGER:
326 case PIPE_TESS_PART_POW2:
327 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
328 break;
329 case PIPE_TESS_PART_FRACT_ODD:
330 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
331 break;
332 case PIPE_TESS_PART_FRACT_EVEN:
333 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
334 break;
335 default:
336 assert(!"invalid tessellator partitioning");
337 break;
338 }
339 }
340 #endif
341
342 #ifdef PIPE_SHADER_HULL
343 static int
344 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
345 {
346 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
347
348 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
349
350 if (info->numPatchConstants)
351 opcs = 8 + info->numPatchConstants * 4;
352
353 tcp->hdr[0] = 0x20061 | (2 << 10);
354
355 tcp->hdr[1] = opcs << 24;
356 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
357
358 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
359
360 nvc0_vtgp_gen_header(tcp, info);
361
362 nvc0_tp_get_tess_mode(tcp, info);
363
364 return 0;
365 }
366 #endif
367
368 #ifdef PIPE_SHADER_DOMAIN
369 static int
370 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
371 {
372 tep->tp.input_patch_size = ~0;
373
374 tep->hdr[0] = 0x20061 | (3 << 10);
375 tep->hdr[4] = 0xff000;
376
377 nvc0_vtgp_gen_header(tep, info);
378
379 nvc0_tp_get_tess_mode(tep, info);
380
381 tep->hdr[18] |= 0x3 << 12; /* ? */
382
383 return 0;
384 }
385 #endif
386
387 static int
388 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
389 {
390 gp->hdr[0] = 0x20061 | (4 << 10);
391
392 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
393
394 switch (info->prop.gp.outputPrim) {
395 case PIPE_PRIM_POINTS:
396 gp->hdr[3] = 0x01000000;
397 gp->hdr[0] |= 0xf0000000;
398 break;
399 case PIPE_PRIM_LINE_STRIP:
400 gp->hdr[3] = 0x06000000;
401 gp->hdr[0] |= 0x10000000;
402 break;
403 case PIPE_PRIM_TRIANGLE_STRIP:
404 gp->hdr[3] = 0x07000000;
405 gp->hdr[0] |= 0x10000000;
406 break;
407 default:
408 assert(0);
409 break;
410 }
411
412 gp->hdr[4] = info->prop.gp.maxVertices & 0x1ff;
413
414 return nvc0_vtgp_gen_header(gp, info);
415 }
416
417 #define NVC0_INTERP_FLAT (1 << 0)
418 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
419 #define NVC0_INTERP_LINEAR (3 << 0)
420 #define NVC0_INTERP_CENTROID (1 << 2)
421
422 static uint8_t
423 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
424 {
425 if (var->linear)
426 return NVC0_INTERP_LINEAR;
427 if (var->flat)
428 return NVC0_INTERP_FLAT;
429 return NVC0_INTERP_PERSPECTIVE;
430 }
431
432 static int
433 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
434 {
435 unsigned i, c, a, m;
436
437 fp->hdr[0] = 0x20062 | (5 << 10);
438 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
439
440 if (info->prop.fp.usesDiscard)
441 fp->hdr[0] |= 0x8000;
442 if (info->prop.fp.numColourResults > 1)
443 fp->hdr[0] |= 0x4000;
444 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
445 fp->hdr[19] |= 0x1;
446 if (info->prop.fp.writesDepth) {
447 fp->hdr[19] |= 0x2;
448 fp->flags[0] = 0x11; /* deactivate ZCULL */
449 }
450
451 for (i = 0; i < info->numInputs; ++i) {
452 m = nvc0_hdr_interp_mode(&info->in[i]);
453 for (c = 0; c < 4; ++c) {
454 if (!(info->in[i].mask & (1 << c)))
455 continue;
456 a = info->in[i].slot[c];
457 if (info->in[i].slot[0] >= (0x060 / 4) &&
458 info->in[i].slot[0] <= (0x07c / 4)) {
459 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
460 } else
461 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
462 info->in[i].slot[0] <= (0x2fc / 4)) {
463 fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x03ff0000;
464 } else {
465 if (info->in[i].slot[c] < (0x040 / 4) ||
466 info->in[i].slot[c] > (0x380 / 4))
467 continue;
468 a *= 2;
469 if (info->in[i].slot[0] >= (0x300 / 4))
470 a -= 32;
471 fp->hdr[4 + a / 32] |= m << (a % 32);
472 }
473 }
474 }
475
476 for (i = 0; i < info->numOutputs; ++i) {
477 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
478 fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
479 }
480
481 fp->fp.early_z = info->prop.fp.earlyFragTests;
482 if (fp->fp.early_z == FALSE && fp->code_size >= 0x400)
483 fp->fp.early_z = !(info->prop.fp.writesDepth ||
484 info->prop.fp.usesDiscard ||
485 (info->io.globalAccess & 2));
486
487 return 0;
488 }
489
490 static struct nvc0_transform_feedback_state *
491 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
492 const struct pipe_stream_output_info *pso)
493 {
494 struct nvc0_transform_feedback_state *tfb;
495 unsigned b, i, c;
496
497 tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
498 if (!tfb)
499 return NULL;
500 for (b = 0; b < 4; ++b) {
501 tfb->stride[b] = pso->stride[b] * 4;
502 tfb->varying_count[b] = 0;
503 }
504 memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
505
506 for (i = 0; i < pso->num_outputs; ++i) {
507 unsigned s = pso->output[i].start_component;
508 unsigned p = pso->output[i].dst_offset;
509 b = pso->output[i].output_buffer;
510
511 for (c = 0; c < pso->output[i].num_components; ++c)
512 tfb->varying_index[b][p++] =
513 info->out[pso->output[i].register_index].slot[s + c];
514
515 tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
516 }
517 for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
518 for (c = tfb->varying_count[b]; c & 3; ++c)
519 tfb->varying_index[b][c] = 0;
520
521 return tfb;
522 }
523
524 #ifdef DEBUG
525 static void
526 nvc0_program_dump(struct nvc0_program *prog)
527 {
528 unsigned pos;
529
530 for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
531 debug_printf("HDR[%02lx] = 0x%08x\n",
532 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
533
534 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
535 for (pos = 0; pos < prog->code_size / 4; ++pos) {
536 if ((pos % 8) == 0)
537 debug_printf("\n");
538 debug_printf("%08x ", prog->code[pos]);
539 }
540 debug_printf("\n");
541 }
542 #endif
543
544 boolean
545 nvc0_program_translate(struct nvc0_program *prog)
546 {
547 struct nv50_ir_prog_info *info;
548 int ret;
549
550 info = CALLOC_STRUCT(nv50_ir_prog_info);
551 if (!info)
552 return FALSE;
553
554 info->type = prog->type;
555 info->target = 0xc0;
556 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
557 info->bin.source = (void *)prog->pipe.tokens;
558
559 info->io.genUserClip = prog->vp.num_ucps;
560
561 info->assignSlots = nvc0_program_assign_varying_slots;
562
563 #ifdef DEBUG
564 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
565 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
566 #else
567 info->optLevel = 3;
568 #endif
569
570 ret = nv50_ir_generate_code(info);
571 if (ret) {
572 NOUVEAU_ERR("shader translation failed: %i\n", ret);
573 goto out;
574 }
575
576 prog->code = info->bin.code;
577 prog->code_size = info->bin.codeSize;
578 prog->immd_data = info->immd.buf;
579 prog->immd_size = info->immd.bufSize;
580 prog->relocs = info->bin.relocData;
581 prog->max_gpr = MAX2(4, (info->bin.maxGPR + 1));
582
583 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
584
585 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
586 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
587 prog->vp.edgeflag = info->io.edgeFlagIn;
588
589 switch (prog->type) {
590 case PIPE_SHADER_VERTEX:
591 ret = nvc0_vp_gen_header(prog, info);
592 break;
593 #ifdef PIPE_SHADER_HULL
594 case PIPE_SHADER_HULL:
595 ret = nvc0_tcp_gen_header(prog, info);
596 break;
597 #endif
598 #ifdef PIPE_SHADER_DOMAIN
599 case PIPE_SHADER_DOMAIN:
600 ret = nvc0_tep_gen_header(prog, info);
601 break;
602 #endif
603 case PIPE_SHADER_GEOMETRY:
604 ret = nvc0_gp_gen_header(prog, info);
605 break;
606 case PIPE_SHADER_FRAGMENT:
607 ret = nvc0_fp_gen_header(prog, info);
608 break;
609 default:
610 ret = -1;
611 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
612 break;
613 }
614 if (ret)
615 goto out;
616
617 if (info->bin.tlsSpace) {
618 assert(info->bin.tlsSpace < (1 << 24));
619 prog->hdr[0] |= 1 << 26;
620 prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
621 }
622 if (info->io.globalAccess)
623 prog->hdr[0] |= 1 << 16;
624
625 if (prog->pipe.stream_output.num_outputs)
626 prog->tfb = nvc0_program_create_tfb_state(info,
627 &prog->pipe.stream_output);
628
629 out:
630 FREE(info);
631 return !ret;
632 }
633
634 boolean
635 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
636 {
637 struct nvc0_screen *screen = nvc0->screen;
638 int ret;
639 uint32_t size = prog->code_size + NVC0_SHADER_HEADER_SIZE;
640 uint32_t lib_pos = screen->lib_code->start;
641 uint32_t code_pos;
642
643 /* c[] bindings need to be aligned to 0x100, but we could use relocations
644 * to save space. */
645 if (prog->immd_size) {
646 prog->immd_base = size;
647 size = align(size, 0x40);
648 size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
649 }
650 size = align(size, 0x40); /* required by SP_START_ID */
651
652 ret = nouveau_resource_alloc(screen->text_heap, size, prog, &prog->res);
653 if (ret) {
654 NOUVEAU_ERR("out of code space\n");
655 return FALSE;
656 }
657 prog->code_base = prog->res->start;
658 prog->immd_base = align(prog->res->start + prog->immd_base, 0x100);
659 assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
660 prog->res->start + prog->res->size));
661
662 code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
663
664 if (prog->relocs)
665 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
666
667 #ifdef DEBUG
668 if (debug_get_bool_option("NV50_PROG_DEBUG", FALSE))
669 nvc0_program_dump(prog);
670 #endif
671
672 nvc0_m2mf_push_linear(&nvc0->base, screen->text, prog->code_base,
673 NOUVEAU_BO_VRAM, NVC0_SHADER_HEADER_SIZE, prog->hdr);
674 nvc0_m2mf_push_linear(&nvc0->base, screen->text,
675 prog->code_base + NVC0_SHADER_HEADER_SIZE,
676 NOUVEAU_BO_VRAM, prog->code_size, prog->code);
677 if (prog->immd_size)
678 nvc0_m2mf_push_linear(&nvc0->base,
679 screen->text, prog->immd_base, NOUVEAU_BO_VRAM,
680 prog->immd_size, prog->immd_data);
681
682 BEGIN_RING(screen->base.channel, RING_3D(MEM_BARRIER), 1);
683 OUT_RING (screen->base.channel, 0x1111);
684
685 return TRUE;
686 }
687
688 /* Upload code for builtin functions like integer division emulation. */
689 void
690 nvc0_program_library_upload(struct nvc0_context *nvc0)
691 {
692 struct nvc0_screen *screen = nvc0->screen;
693 int ret;
694 uint32_t size;
695 const uint32_t *code;
696
697 if (screen->lib_code)
698 return;
699
700 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
701 if (!size)
702 return;
703
704 ret = nouveau_resource_alloc(screen->text_heap, align(size, 0x100), NULL,
705 &screen->lib_code);
706 if (ret)
707 return;
708
709 nvc0_m2mf_push_linear(&nvc0->base,
710 screen->text, screen->lib_code->start, NOUVEAU_BO_VRAM,
711 size, code);
712 /* no need for a memory barrier, will be emitted with first program */
713 }
714
715 void
716 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
717 {
718 const struct pipe_shader_state pipe = prog->pipe;
719 const ubyte type = prog->type;
720
721 if (prog->res)
722 nouveau_resource_free(&prog->res);
723
724 if (prog->code)
725 FREE(prog->code);
726 if (prog->immd_data)
727 FREE(prog->immd_data);
728 if (prog->relocs)
729 FREE(prog->relocs);
730 if (prog->tfb) {
731 if (nvc0->state.tfb == prog->tfb)
732 nvc0->state.tfb = NULL;
733 FREE(prog->tfb);
734 }
735
736 memset(prog, 0, sizeof(*prog));
737
738 prog->pipe = pipe;
739 prog->type = type;
740 }