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i915g: Implement KILP.
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "nvc0_context.h"
26
27 #include "nv50/codegen/nv50_ir_driver.h"
28
29 /* If only they told use the actual semantic instead of just GENERIC ... */
30 static void
31 nvc0_mesa_varying_hack(struct nv50_ir_varying *var)
32 {
33 unsigned c;
34
35 if (var->sn != TGSI_SEMANTIC_GENERIC)
36 return;
37
38 if (var->si <= 7) /* gl_TexCoord */
39 for (c = 0; c < 4; ++c)
40 var->slot[c] = (0x300 + var->si * 0x10 + c * 0x4) / 4;
41 else
42 if (var->si == 9) /* gl_PointCoord */
43 for (c = 0; c < 4; ++c)
44 var->slot[c] = (0x2e0 + c * 0x4) / 4;
45 else
46 for (c = 0; c < 4; ++c) /* move down user varyings (first has index 8) */
47 var->slot[c] -= 0x80 / 4;
48 }
49
50 static uint32_t
51 nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
52 {
53 switch (sn) {
54 case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
55 case TGSI_SEMANTIC_PRIMID: return 0x060;
56 case TGSI_SEMANTIC_PSIZE: return 0x06c;
57 case TGSI_SEMANTIC_POSITION: return 0x070;
58 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
59 case TGSI_SEMANTIC_FOG: return 0x270;
60 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
61 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
62 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x10;
63 case NV50_SEMANTIC_POINTCOORD: return 0x2e0;
64 case NV50_SEMANTIC_TESSCOORD: return 0x2f0;
65 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
66 case NV50_SEMANTIC_VERTEXID: return 0x2fc;
67 case NV50_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
68 case TGSI_SEMANTIC_FACE: return 0x3fc;
69 case NV50_SEMANTIC_INVOCATIONID: return ~0;
70 default:
71 assert(!"invalid TGSI input semantic");
72 return ~0;
73 }
74 }
75
76 static uint32_t
77 nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
78 {
79 switch (sn) {
80 case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
81 case TGSI_SEMANTIC_PRIMID: return 0x060;
82 case NV50_SEMANTIC_LAYER: return 0x064;
83 case NV50_SEMANTIC_VIEWPORTINDEX: return 0x068;
84 case TGSI_SEMANTIC_PSIZE: return 0x06c;
85 case TGSI_SEMANTIC_POSITION: return 0x070;
86 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
87 case TGSI_SEMANTIC_FOG: return 0x270;
88 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
89 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
90 case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x10;
91 case NV50_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
92 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
93 default:
94 assert(!"invalid TGSI output semantic");
95 return ~0;
96 }
97 }
98
99 static int
100 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
101 {
102 unsigned i, c, n;
103
104 for (n = 0, i = 0; i < info->numInputs; ++i) {
105 switch (info->in[i].sn) {
106 case TGSI_SEMANTIC_INSTANCEID:
107 case NV50_SEMANTIC_VERTEXID:
108 info->in[i].mask = 0x1;
109 info->in[i].slot[0] =
110 nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
111 continue;
112 default:
113 break;
114 }
115 for (c = 0; c < 4; ++c)
116 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
117 ++n;
118 }
119
120 return 0;
121 }
122
123 static int
124 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
125 {
126 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
127 unsigned offset;
128 unsigned i, c;
129
130 for (i = 0; i < info->numInputs; ++i) {
131 offset = nvc0_shader_input_address(info->in[i].sn,
132 info->in[i].si, ubase);
133 if (info->in[i].patch && offset >= 0x20)
134 offset = 0x20 + info->in[i].si * 0x10;
135
136 if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD)
137 info->in[i].mask &= 3;
138
139 for (c = 0; c < 4; ++c)
140 info->in[i].slot[c] = (offset + c * 0x4) / 4;
141
142 nvc0_mesa_varying_hack(&info->in[i]);
143 }
144
145 return 0;
146 }
147
148 static int
149 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
150 {
151 unsigned last = info->prop.fp.numColourResults * 4;
152 unsigned i, c;
153
154 for (i = 0; i < info->numOutputs; ++i)
155 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
156 for (c = 0; c < 4; ++c)
157 info->out[i].slot[c] = info->out[i].si * 4 + c;
158
159 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
160 info->out[info->io.sampleMask].slot[0] = last++;
161
162 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
163 info->out[info->io.fragDepth].slot[2] = last;
164
165 return 0;
166 }
167
168 static int
169 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
170 {
171 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
172 unsigned offset;
173 unsigned i, c;
174
175 for (i = 0; i < info->numOutputs; ++i) {
176 offset = nvc0_shader_output_address(info->out[i].sn,
177 info->out[i].si, ubase);
178 if (info->out[i].patch && offset >= 0x20)
179 offset = 0x20 + info->out[i].si * 0x10;
180
181 for (c = 0; c < 4; ++c)
182 info->out[i].slot[c] = (offset + c * 0x4) / 4;
183
184 nvc0_mesa_varying_hack(&info->out[i]);
185 }
186
187 return 0;
188 }
189
190 static int
191 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
192 {
193 int ret;
194
195 if (info->type == PIPE_SHADER_VERTEX)
196 ret = nvc0_vp_assign_input_slots(info);
197 else
198 ret = nvc0_sp_assign_input_slots(info);
199 if (ret)
200 return ret;
201
202 if (info->type == PIPE_SHADER_FRAGMENT)
203 ret = nvc0_fp_assign_output_slots(info);
204 else
205 ret = nvc0_sp_assign_output_slots(info);
206 return ret;
207 }
208
209 static INLINE void
210 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
211 {
212 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
213 uint8_t max = (vp->hdr[4] >> 24);
214
215 min = MIN2(min, slot);
216 max = MAX2(max, slot);
217
218 vp->hdr[4] = (max << 24) | (min << 12);
219 }
220
221 /* Common part of header generation for VP, TCP, TEP and GP. */
222 static int
223 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
224 {
225 unsigned i, c, a;
226
227 for (i = 0; i < info->numInputs; ++i) {
228 if (info->in[i].patch)
229 continue;
230 for (c = 0; c < 4; ++c) {
231 a = info->in[i].slot[c];
232 if (info->in[i].mask & (1 << c)) {
233 if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD)
234 vp->hdr[5 + a / 32] |= 1 << (a % 32);
235 else
236 nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]);
237 }
238 }
239 }
240
241 for (i = 0; i < info->numOutputs; ++i) {
242 if (info->out[i].patch)
243 continue;
244 for (c = 0; c < 4; ++c) {
245 if (!(info->out[i].mask & (1 << c)))
246 continue;
247 assert(info->out[i].slot[c] >= 0x40 / 4);
248 a = info->out[i].slot[c] - 0x40 / 4;
249 vp->hdr[13 + a / 32] |= 1 << (a % 32);
250 if (info->out[i].oread)
251 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
252 }
253 }
254
255 for (i = 0; i < info->numSysVals; ++i) {
256 switch (info->sv[i].sn) {
257 case TGSI_SEMANTIC_PRIMID:
258 vp->hdr[5] |= 1 << 24;
259 break;
260 case TGSI_SEMANTIC_INSTANCEID:
261 vp->hdr[10] |= 1 << 30;
262 break;
263 case NV50_SEMANTIC_VERTEXID:
264 vp->hdr[10] |= 1 << 31;
265 break;
266 default:
267 break;
268 }
269 }
270
271 vp->vp.clip_enable = (1 << info->io.clipDistanceCount) - 1;
272 for (i = 0; i < 8; ++i)
273 if (info->io.cullDistanceMask & (1 << i))
274 vp->vp.clip_mode |= 1 << (i * 4);
275
276 return 0;
277 }
278
279 static int
280 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
281 {
282 vp->hdr[0] = 0x20061 | (1 << 10);
283 vp->hdr[4] = 0xff000;
284
285 vp->hdr[18] = (1 << info->io.clipDistanceCount) - 1;
286
287 return nvc0_vtgp_gen_header(vp, info);
288 }
289
290 #if defined(PIPE_SHADER_HULL) || defined(PIPE_SHADER_DOMAIN)
291 static void
292 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
293 {
294 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
295 tp->tp.tess_mode = ~0;
296 return;
297 }
298 switch (info->prop.tp.domain) {
299 case PIPE_PRIM_LINES:
300 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
301 break;
302 case PIPE_PRIM_TRIANGLES:
303 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
304 if (info->prop.tp.winding > 0)
305 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
306 break;
307 case PIPE_PRIM_QUADS:
308 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
309 break;
310 default:
311 tp->tp.tess_mode = ~0;
312 return;
313 }
314 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
315 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
316
317 switch (info->prop.tp.partitioning) {
318 case PIPE_TESS_PART_INTEGER:
319 case PIPE_TESS_PART_POW2:
320 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
321 break;
322 case PIPE_TESS_PART_FRACT_ODD:
323 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
324 break;
325 case PIPE_TESS_PART_FRACT_EVEN:
326 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
327 break;
328 default:
329 assert(!"invalid tessellator partitioning");
330 break;
331 }
332 }
333 #endif
334
335 #ifdef PIPE_SHADER_HULL
336 static int
337 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
338 {
339 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
340
341 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
342
343 if (info->numPatchConstants)
344 opcs = 8 + info->numPatchConstants * 4;
345
346 tcp->hdr[0] = 0x20061 | (2 << 10);
347
348 tcp->hdr[1] = opcs << 24;
349 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
350
351 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
352
353 nvc0_vtgp_gen_header(tcp, info);
354
355 nvc0_tp_get_tess_mode(tcp, info);
356
357 return 0;
358 }
359 #endif
360
361 #ifdef PIPE_SHADER_DOMAIN
362 static int
363 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
364 {
365 tep->tp.input_patch_size = ~0;
366
367 tep->hdr[0] = 0x20061 | (3 << 10);
368 tep->hdr[4] = 0xff000;
369
370 nvc0_vtgp_gen_header(tep, info);
371
372 nvc0_tp_get_tess_mode(tep, info);
373
374 tep->hdr[18] |= 0x3 << 12; /* ? */
375
376 return 0;
377 }
378 #endif
379
380 static int
381 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
382 {
383 gp->hdr[0] = 0x20061 | (4 << 10);
384
385 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
386
387 switch (info->prop.gp.outputPrim) {
388 case PIPE_PRIM_POINTS:
389 gp->hdr[3] = 0x01000000;
390 gp->hdr[0] |= 0xf0000000;
391 break;
392 case PIPE_PRIM_LINE_STRIP:
393 gp->hdr[3] = 0x06000000;
394 gp->hdr[0] |= 0x10000000;
395 break;
396 case PIPE_PRIM_TRIANGLE_STRIP:
397 gp->hdr[3] = 0x07000000;
398 gp->hdr[0] |= 0x10000000;
399 break;
400 default:
401 assert(0);
402 break;
403 }
404
405 gp->hdr[4] = info->prop.gp.maxVertices & 0x1ff;
406
407 return nvc0_vtgp_gen_header(gp, info);
408 }
409
410 #define NVC0_INTERP_FLAT (1 << 0)
411 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
412 #define NVC0_INTERP_LINEAR (3 << 0)
413 #define NVC0_INTERP_CENTROID (1 << 2)
414
415 static uint8_t
416 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
417 {
418 if (var->linear)
419 return NVC0_INTERP_LINEAR;
420 if (var->flat)
421 return NVC0_INTERP_FLAT;
422 return NVC0_INTERP_PERSPECTIVE;
423 }
424
425 static int
426 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
427 {
428 unsigned i, c, a, m;
429
430 fp->hdr[0] = 0x20062 | (5 << 10);
431 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
432
433 if (info->prop.fp.usesDiscard)
434 fp->hdr[0] |= 0x8000;
435 if (info->prop.fp.numColourResults > 1)
436 fp->hdr[0] |= 0x4000;
437 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
438 fp->hdr[19] |= 0x1;
439 if (info->prop.fp.writesDepth) {
440 fp->hdr[19] |= 0x2;
441 fp->flags[0] = 0x11; /* deactivate ZCULL */
442 }
443
444 for (i = 0; i < info->numInputs; ++i) {
445 m = nvc0_hdr_interp_mode(&info->in[i]);
446 for (c = 0; c < 4; ++c) {
447 if (!(info->in[i].mask & (1 << c)))
448 continue;
449 a = info->in[i].slot[c];
450 if (info->in[i].slot[0] >= (0x060 / 4) &&
451 info->in[i].slot[0] <= (0x07c / 4)) {
452 fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
453 } else
454 if (info->in[i].slot[0] == (0x2e0 / 4)) {
455 if (c <= 1)
456 fp->hdr[14] |= 1 << (24 + c);
457 } else {
458 if (info->in[i].slot[c] < (0x040 / 4) ||
459 info->in[i].slot[c] > (0x380 / 4))
460 continue;
461 a *= 2;
462 if (info->in[i].slot[0] >= (0x2c0 / 4))
463 a -= 32;
464 fp->hdr[4 + a / 32] |= m << (a % 32);
465 }
466 }
467 }
468
469 for (i = 0; i < info->numOutputs; ++i) {
470 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
471 fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
472 }
473
474 fp->fp.early_z = info->prop.fp.earlyFragTests;
475 if (fp->fp.early_z == FALSE && fp->code_size >= 0x400)
476 fp->fp.early_z = !(info->prop.fp.writesDepth ||
477 info->prop.fp.usesDiscard ||
478 (info->io.globalAccess & 2));
479
480 return 0;
481 }
482
483 static struct nvc0_transform_feedback_state *
484 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
485 const struct pipe_stream_output_info *pso)
486 {
487 struct nvc0_transform_feedback_state *tfb;
488 int n = 0;
489 int i, c, b;
490
491 tfb = MALLOC(sizeof(*tfb) + pso->num_outputs * 4 * sizeof(uint8_t));
492 if (!tfb)
493 return NULL;
494
495 for (b = 0; b < 4; ++b) {
496 tfb->varying_count[b] = 0;
497
498 for (i = 0; i < pso->num_outputs; ++i) {
499 if (pso->output[i].output_buffer != b)
500 continue;
501 for (c = 0; c < 4; ++c) {
502 if (!(pso->output[i].register_mask & (1 << c)))
503 continue;
504 tfb->varying_count[b]++;
505 tfb->varying_index[n++] =
506 info->out[pso->output[i].register_index].slot[c];
507 }
508 }
509 tfb->stride[b] = tfb->varying_count[b] * 4;
510 }
511 if (pso->stride)
512 tfb->stride[0] = pso->stride;
513
514 return tfb;
515 }
516
517 #ifdef DEBUG
518 static void
519 nvc0_program_dump(struct nvc0_program *prog)
520 {
521 unsigned pos;
522
523 for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
524 debug_printf("HDR[%02lx] = 0x%08x\n",
525 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
526
527 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
528 for (pos = 0; pos < prog->code_size / 4; ++pos) {
529 if ((pos % 8) == 0)
530 debug_printf("\n");
531 debug_printf("%08x ", prog->code[pos]);
532 }
533 debug_printf("\n");
534 }
535 #endif
536
537 boolean
538 nvc0_program_translate(struct nvc0_program *prog)
539 {
540 struct nv50_ir_prog_info *info;
541 int ret;
542
543 info = CALLOC_STRUCT(nv50_ir_prog_info);
544 if (!info)
545 return FALSE;
546
547 info->type = prog->type;
548 info->target = 0xc0;
549 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
550 info->bin.source = (void *)prog->pipe.tokens;
551
552 info->io.clipDistanceCount = prog->vp.num_ucps;
553
554 info->assignSlots = nvc0_program_assign_varying_slots;
555
556 #ifdef DEBUG
557 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
558 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
559 #else
560 info->optLevel = 3;
561 #endif
562
563 ret = nv50_ir_generate_code(info);
564 if (ret) {
565 NOUVEAU_ERR("shader translation failed: %i\n", ret);
566 goto out;
567 }
568
569 prog->code = info->bin.code;
570 prog->code_size = info->bin.codeSize;
571 prog->immd_data = info->immd.buf;
572 prog->immd_size = info->immd.bufSize;
573 prog->relocs = info->bin.relocData;
574 prog->max_gpr = MAX2(4, (info->bin.maxGPR + 1));
575
576 prog->vp.edgeflag = PIPE_MAX_ATTRIBS;
577
578 switch (prog->type) {
579 case PIPE_SHADER_VERTEX:
580 ret = nvc0_vp_gen_header(prog, info);
581 break;
582 #ifdef PIPE_SHADER_HULL
583 case PIPE_SHADER_HULL:
584 ret = nvc0_tcp_gen_header(prog, info);
585 break;
586 #endif
587 #ifdef PIPE_SHADER_DOMAIN
588 case PIPE_SHADER_DOMAIN:
589 ret = nvc0_tep_gen_header(prog, info);
590 break;
591 #endif
592 case PIPE_SHADER_GEOMETRY:
593 ret = nvc0_gp_gen_header(prog, info);
594 break;
595 case PIPE_SHADER_FRAGMENT:
596 ret = nvc0_fp_gen_header(prog, info);
597 break;
598 default:
599 ret = -1;
600 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
601 break;
602 }
603 if (ret)
604 goto out;
605
606 if (info->bin.tlsSpace) {
607 assert(info->bin.tlsSpace < (1 << 24));
608 prog->hdr[0] |= 1 << 26;
609 prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
610 }
611 if (info->io.globalAccess)
612 prog->hdr[0] |= 1 << 16;
613
614 if (prog->pipe.stream_output.num_outputs)
615 prog->tfb = nvc0_program_create_tfb_state(info,
616 &prog->pipe.stream_output);
617
618 out:
619 FREE(info);
620 return !ret;
621 }
622
623 boolean
624 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
625 {
626 struct nvc0_screen *screen = nvc0->screen;
627 int ret;
628 uint32_t size = prog->code_size + NVC0_SHADER_HEADER_SIZE;
629 uint32_t lib_pos = screen->lib_code->start;
630 uint32_t code_pos;
631
632 /* c[] bindings need to be aligned to 0x100, but we could use relocations
633 * to save space. */
634 if (prog->immd_size) {
635 prog->immd_base = size;
636 size = align(size, 0x40);
637 size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
638 }
639 size = align(size, 0x40); /* required by SP_START_ID */
640
641 ret = nouveau_resource_alloc(screen->text_heap, size, prog, &prog->res);
642 if (ret) {
643 NOUVEAU_ERR("out of code space\n");
644 return FALSE;
645 }
646 prog->code_base = prog->res->start;
647 prog->immd_base = align(prog->res->start + prog->immd_base, 0x100);
648 assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
649 prog->res->start + prog->res->size));
650
651 code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
652
653 if (prog->relocs)
654 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
655
656 #ifdef DEBUG
657 if (debug_get_bool_option("NV50_PROG_DEBUG", FALSE))
658 nvc0_program_dump(prog);
659 #endif
660
661 nvc0_m2mf_push_linear(&nvc0->base, screen->text, prog->code_base,
662 NOUVEAU_BO_VRAM, NVC0_SHADER_HEADER_SIZE, prog->hdr);
663 nvc0_m2mf_push_linear(&nvc0->base, screen->text,
664 prog->code_base + NVC0_SHADER_HEADER_SIZE,
665 NOUVEAU_BO_VRAM, prog->code_size, prog->code);
666 if (prog->immd_size)
667 nvc0_m2mf_push_linear(&nvc0->base,
668 screen->text, prog->immd_base, NOUVEAU_BO_VRAM,
669 prog->immd_size, prog->immd_data);
670
671 BEGIN_RING(screen->base.channel, RING_3D(MEM_BARRIER), 1);
672 OUT_RING (screen->base.channel, 0x1111);
673
674 return TRUE;
675 }
676
677 /* Upload code for builtin functions like integer division emulation. */
678 void
679 nvc0_program_library_upload(struct nvc0_context *nvc0)
680 {
681 struct nvc0_screen *screen = nvc0->screen;
682 int ret;
683 uint32_t size;
684 const uint32_t *code;
685
686 if (screen->lib_code)
687 return;
688
689 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
690 if (!size)
691 return;
692
693 ret = nouveau_resource_alloc(screen->text_heap, align(size, 0x100), NULL,
694 &screen->lib_code);
695 if (ret)
696 return;
697
698 nvc0_m2mf_push_linear(&nvc0->base,
699 screen->text, screen->lib_code->start, NOUVEAU_BO_VRAM,
700 size, code);
701 /* no need for a memory barrier, will be emitted with first program */
702 }
703
704 void
705 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
706 {
707 if (prog->res)
708 nouveau_resource_free(&prog->res);
709
710 if (prog->code)
711 FREE(prog->code);
712 if (prog->immd_data)
713 FREE(prog->immd_data);
714 if (prog->relocs)
715 FREE(prog->relocs);
716 if (prog->tfb) {
717 if (nvc0->state.tfb == prog->tfb)
718 nvc0->state.tfb = NULL;
719 FREE(prog->tfb);
720 }
721
722 memset(prog->hdr, 0, sizeof(prog->hdr));
723
724 prog->translated = FALSE;
725 }