src/gallium/drivers/nvc0/nvc0_program.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "pipe/p_defines.h"
  24
  25 #include "nvc0_context.h"
  26
  27 #include "nv50/codegen/nv50_ir_driver.h"
  28
  29 /* If only they told use the actual semantic instead of just GENERIC ... */
  30 static void
  31 nvc0_mesa_varying_hack(struct nv50_ir_varying *var)
  32 {
  33    unsigned c;
  34
  35    if (var->sn != TGSI_SEMANTIC_GENERIC)
  36       return;
  37
  38    if (var->si <= 7) /* gl_TexCoord */
  39       for (c = 0; c < 4; ++c)
  40          var->slot[c] = (0x300 + var->si * 0x10 + c * 0x4) / 4;
  41    else
  42    if (var->si == 9) /* gl_PointCoord */
  43       for (c = 0; c < 4; ++c)
  44          var->slot[c] = (0x2e0 + c * 0x4) / 4;
  45    else
  46       for (c = 0; c < 4; ++c) /* move down user varyings (first has index 8) */
  47          var->slot[c] -= 0x80 / 4;
  48 }
  49
  50 static uint32_t
  51 nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
  52 {
  53    switch (sn) {
  54    case NV50_SEMANTIC_TESSFACTOR:   return 0x000 + si * 0x4;
  55    case TGSI_SEMANTIC_PRIMID:       return 0x060;
  56    case TGSI_SEMANTIC_PSIZE:        return 0x06c;
  57    case TGSI_SEMANTIC_POSITION:     return 0x070;
  58    case TGSI_SEMANTIC_GENERIC:      return ubase + si * 0x10;
  59    case TGSI_SEMANTIC_FOG:          return 0x270;
  60    case TGSI_SEMANTIC_COLOR:        return 0x280 + si * 0x10;
  61    case TGSI_SEMANTIC_BCOLOR:       return 0x2a0 + si * 0x10;
  62    case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
  63    case TGSI_SEMANTIC_CLIPDIST:     return 0x2c0 + si * 0x10;
  64    case TGSI_SEMANTIC_CLIPVERTEX:   return 0x260;
  65    case NV50_SEMANTIC_POINTCOORD:   return 0x2e0;
  66    case NV50_SEMANTIC_TESSCOORD:    return 0x2f0;
  67    case TGSI_SEMANTIC_INSTANCEID:   return 0x2f8;
  68    case TGSI_SEMANTIC_VERTEXID:     return 0x2fc;
  69    case NV50_SEMANTIC_TEXCOORD:     return 0x300 + si * 0x10;
  70    case TGSI_SEMANTIC_FACE:         return 0x3fc;
  71    case NV50_SEMANTIC_INVOCATIONID: return ~0;
  72    default:
  73       assert(!"invalid TGSI input semantic");
  74       return ~0;
  75    }
  76 }
  77
  78 static uint32_t
  79 nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
  80 {
  81    switch (sn) {
  82    case NV50_SEMANTIC_TESSFACTOR:    return 0x000 + si * 0x4;
  83    case TGSI_SEMANTIC_PRIMID:        return 0x060;
  84    case NV50_SEMANTIC_LAYER:         return 0x064;
  85    case NV50_SEMANTIC_VIEWPORTINDEX: return 0x068;
  86    case TGSI_SEMANTIC_PSIZE:         return 0x06c;
  87    case TGSI_SEMANTIC_POSITION:      return 0x070;
  88    case TGSI_SEMANTIC_GENERIC:       return ubase + si * 0x10;
  89    case TGSI_SEMANTIC_FOG:           return 0x270;
  90    case TGSI_SEMANTIC_COLOR:         return 0x280 + si * 0x10;
  91    case TGSI_SEMANTIC_BCOLOR:        return 0x2a0 + si * 0x10;
  92    case NV50_SEMANTIC_CLIPDISTANCE:  return 0x2c0 + si * 0x4;
  93    case TGSI_SEMANTIC_CLIPDIST:      return 0x2c0 + si * 0x10;
  94    case TGSI_SEMANTIC_CLIPVERTEX:    return 0x260;
  95    case NV50_SEMANTIC_TEXCOORD:      return 0x300 + si * 0x10;
  96    case TGSI_SEMANTIC_EDGEFLAG:      return ~0;
  97    default:
  98       assert(!"invalid TGSI output semantic");
  99       return ~0;
 100    }
 101 }
 102
 103 static int
 104 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
 105 {
 106    unsigned i, c, n;
 107
 108    for (n = 0, i = 0; i < info->numInputs; ++i) {
 109       switch (info->in[i].sn) {
 110       case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
 111       case TGSI_SEMANTIC_VERTEXID:
 112          info->in[i].mask = 0x1;
 113          info->in[i].slot[0] =
 114             nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
 115          continue;
 116       default:
 117          break;
 118       }
 119       for (c = 0; c < 4; ++c)
 120          info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
 121       ++n;
 122    }
 123
 124    return 0;
 125 }
 126
 127 static int
 128 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
 129 {
 130    unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
 131    unsigned offset;
 132    unsigned i, c;
 133
 134    for (i = 0; i < info->numInputs; ++i) {
 135       offset = nvc0_shader_input_address(info->in[i].sn,
 136                                          info->in[i].si, ubase);
 137       if (info->in[i].patch && offset >= 0x20)
 138          offset = 0x20 + info->in[i].si * 0x10;
 139
 140       if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD)
 141          info->in[i].mask &= 3;
 142
 143       for (c = 0; c < 4; ++c)
 144          info->in[i].slot[c] = (offset + c * 0x4) / 4;
 145
 146       nvc0_mesa_varying_hack(&info->in[i]);
 147    }
 148
 149    return 0;
 150 }
 151
 152 static int
 153 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
 154 {
 155    unsigned count = info->prop.fp.numColourResults * 4;
 156    unsigned i, c;
 157
 158    for (i = 0; i < info->numOutputs; ++i)
 159       if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
 160          for (c = 0; c < 4; ++c)
 161             info->out[i].slot[c] = info->out[i].si * 4 + c;
 162
 163    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
 164       info->out[info->io.sampleMask].slot[0] = count++;
 165    else
 166    if (info->target >= 0xe0)
 167       count++; /* on Kepler, depth is always last colour reg + 2 */
 168
 169    if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
 170       info->out[info->io.fragDepth].slot[2] = count;
 171
 172    return 0;
 173 }
 174
 175 static int
 176 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
 177 {
 178    unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
 179    unsigned offset;
 180    unsigned i, c;
 181
 182    for (i = 0; i < info->numOutputs; ++i) {
 183       offset = nvc0_shader_output_address(info->out[i].sn,
 184                                           info->out[i].si, ubase);
 185       if (info->out[i].patch && offset >= 0x20)
 186          offset = 0x20 + info->out[i].si * 0x10;
 187
 188       for (c = 0; c < 4; ++c)
 189          info->out[i].slot[c] = (offset + c * 0x4) / 4;
 190
 191       nvc0_mesa_varying_hack(&info->out[i]);
 192    }
 193
 194    return 0;
 195 }
 196
 197 static int
 198 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
 199 {
 200    int ret;
 201
 202    if (info->type == PIPE_SHADER_VERTEX)
 203       ret = nvc0_vp_assign_input_slots(info);
 204    else
 205       ret = nvc0_sp_assign_input_slots(info);
 206    if (ret)
 207       return ret;
 208
 209    if (info->type == PIPE_SHADER_FRAGMENT)
 210       ret = nvc0_fp_assign_output_slots(info);
 211    else
 212       ret = nvc0_sp_assign_output_slots(info);
 213    return ret;
 214 }
 215
 216 static INLINE void
 217 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
 218 {
 219    uint8_t min = (vp->hdr[4] >> 12) & 0xff;
 220    uint8_t max = (vp->hdr[4] >> 24);
 221
 222    min = MIN2(min, slot);
 223    max = MAX2(max, slot);
 224
 225    vp->hdr[4] = (max << 24) | (min << 12);
 226 }
 227
 228 /* Common part of header generation for VP, TCP, TEP and GP. */
 229 static int
 230 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
 231 {
 232    unsigned i, c, a;
 233
 234    for (i = 0; i < info->numInputs; ++i) {
 235       if (info->in[i].patch)
 236          continue;
 237       for (c = 0; c < 4; ++c) {
 238          a = info->in[i].slot[c];
 239          if (info->in[i].mask & (1 << c)) {
 240             if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD)
 241                vp->hdr[5 + a / 32] |= 1 << (a % 32);
 242             else
 243                nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]);
 244          }
 245       }
 246    }
 247
 248    for (i = 0; i < info->numOutputs; ++i) {
 249       if (info->out[i].patch)
 250          continue;
 251       for (c = 0; c < 4; ++c) {
 252          if (!(info->out[i].mask & (1 << c)))
 253             continue;
 254          assert(info->out[i].slot[c] >= 0x40 / 4);
 255          a = info->out[i].slot[c] - 0x40 / 4;
 256          vp->hdr[13 + a / 32] |= 1 << (a % 32);
 257          if (info->out[i].oread)
 258             nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
 259       }
 260    }
 261
 262    for (i = 0; i < info->numSysVals; ++i) {
 263       switch (info->sv[i].sn) {
 264       case TGSI_SEMANTIC_PRIMID:
 265          vp->hdr[5] |= 1 << 24;
 266          break;
 267       case TGSI_SEMANTIC_INSTANCEID:
 268          vp->hdr[10] |= 1 << 30;
 269          break;
 270       case TGSI_SEMANTIC_VERTEXID:
 271          vp->hdr[10] |= 1 << 31;
 272          break;
 273       default:
 274          break;
 275       }
 276    }
 277
 278    vp->vp.clip_enable = info->io.clipDistanceMask;
 279    for (i = 0; i < 8; ++i)
 280       if (info->io.cullDistanceMask & (1 << i))
 281          vp->vp.clip_mode |= 1 << (i * 4);
 282
 283    if (info->io.genUserClip < 0)
 284       vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
 285
 286    return 0;
 287 }
 288
 289 static int
 290 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
 291 {
 292    vp->hdr[0] = 0x20061 | (1 << 10);
 293    vp->hdr[4] = 0xff000;
 294
 295    vp->hdr[18] = info->io.clipDistanceMask;
 296
 297    return nvc0_vtgp_gen_header(vp, info);
 298 }
 299
 300 #if defined(PIPE_SHADER_HULL) || defined(PIPE_SHADER_DOMAIN)
 301 static void
 302 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
 303 {
 304    if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
 305       tp->tp.tess_mode = ~0;
 306       return;
 307    }
 308    switch (info->prop.tp.domain) {
 309    case PIPE_PRIM_LINES:
 310       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
 311       break;
 312    case PIPE_PRIM_TRIANGLES:
 313       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
 314       if (info->prop.tp.winding > 0)
 315          tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
 316       break;
 317    case PIPE_PRIM_QUADS:
 318       tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
 319       break;
 320    default:
 321       tp->tp.tess_mode = ~0;
 322       return;
 323    }
 324    if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
 325       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
 326
 327    switch (info->prop.tp.partitioning) {
 328    case PIPE_TESS_PART_INTEGER:
 329    case PIPE_TESS_PART_POW2:
 330       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
 331       break;
 332    case PIPE_TESS_PART_FRACT_ODD:
 333       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
 334       break;
 335    case PIPE_TESS_PART_FRACT_EVEN:
 336       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
 337       break;
 338    default:
 339       assert(!"invalid tessellator partitioning");
 340       break;
 341    }
 342 }
 343 #endif
 344
 345 #ifdef PIPE_SHADER_HULL
 346 static int
 347 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
 348 {
 349    unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
 350
 351    tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
 352
 353    if (info->numPatchConstants)
 354       opcs = 8 + info->numPatchConstants * 4;
 355
 356    tcp->hdr[0] = 0x20061 | (2 << 10);
 357
 358    tcp->hdr[1] = opcs << 24;
 359    tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
 360
 361    tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
 362
 363    nvc0_vtgp_gen_header(tcp, info);
 364
 365    nvc0_tp_get_tess_mode(tcp, info);
 366
 367    return 0;
 368 }
 369 #endif
 370
 371 #ifdef PIPE_SHADER_DOMAIN
 372 static int
 373 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
 374 {
 375    tep->tp.input_patch_size = ~0;
 376
 377    tep->hdr[0] = 0x20061 | (3 << 10);
 378    tep->hdr[4] = 0xff000;
 379
 380    nvc0_vtgp_gen_header(tep, info);
 381
 382    nvc0_tp_get_tess_mode(tep, info);
 383
 384    tep->hdr[18] |= 0x3 << 12; /* ? */
 385
 386    return 0;
 387 }
 388 #endif
 389
 390 static int
 391 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
 392 {
 393    gp->hdr[0] = 0x20061 | (4 << 10);
 394
 395    gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
 396
 397    switch (info->prop.gp.outputPrim) {
 398    case PIPE_PRIM_POINTS:
 399       gp->hdr[3] = 0x01000000;
 400       gp->hdr[0] |= 0xf0000000;
 401       break;
 402    case PIPE_PRIM_LINE_STRIP:
 403       gp->hdr[3] = 0x06000000;
 404       gp->hdr[0] |= 0x10000000;
 405       break;
 406    case PIPE_PRIM_TRIANGLE_STRIP:
 407       gp->hdr[3] = 0x07000000;
 408       gp->hdr[0] |= 0x10000000;
 409       break;
 410    default:
 411       assert(0);
 412       break;
 413    }
 414
 415    gp->hdr[4] = info->prop.gp.maxVertices & 0x1ff;
 416
 417    return nvc0_vtgp_gen_header(gp, info);
 418 }
 419
 420 #define NVC0_INTERP_FLAT          (1 << 0)
 421 #define NVC0_INTERP_PERSPECTIVE   (2 << 0)
 422 #define NVC0_INTERP_LINEAR        (3 << 0)
 423 #define NVC0_INTERP_CENTROID      (1 << 2)
 424
 425 static uint8_t
 426 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
 427 {
 428    if (var->linear)
 429       return NVC0_INTERP_LINEAR;
 430    if (var->flat)
 431       return NVC0_INTERP_FLAT;
 432    return NVC0_INTERP_PERSPECTIVE;
 433 }
 434
 435 static int
 436 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
 437 {
 438    unsigned i, c, a, m;
 439
 440    /* just 00062 on Kepler */
 441    fp->hdr[0] = 0x20062 | (5 << 10);
 442    fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
 443
 444    if (info->prop.fp.usesDiscard)
 445       fp->hdr[0] |= 0x8000;
 446    if (info->prop.fp.numColourResults > 1)
 447       fp->hdr[0] |= 0x4000;
 448    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
 449       fp->hdr[19] |= 0x1;
 450    if (info->prop.fp.writesDepth) {
 451       fp->hdr[19] |= 0x2;
 452       fp->flags[0] = 0x11; /* deactivate ZCULL */
 453    }
 454
 455    for (i = 0; i < info->numInputs; ++i) {
 456       m = nvc0_hdr_interp_mode(&info->in[i]);
 457       for (c = 0; c < 4; ++c) {
 458          if (!(info->in[i].mask & (1 << c)))
 459             continue;
 460          a = info->in[i].slot[c];
 461          if (info->in[i].slot[0] >= (0x060 / 4) &&
 462              info->in[i].slot[0] <= (0x07c / 4)) {
 463             fp->hdr[5] |= 1 << (24 + (a - 0x060 / 4));
 464          } else
 465          if (info->in[i].slot[0] >= (0x2c0 / 4) &&
 466              info->in[i].slot[0] <= (0x2fc / 4)) {
 467             fp->hdr[14] |= (1 << (a - 0x280 / 4)) & 0x03ff0000;
 468          } else {
 469             if (info->in[i].slot[c] < (0x040 / 4) ||
 470                 info->in[i].slot[c] > (0x380 / 4))
 471                continue;
 472             a *= 2;
 473             if (info->in[i].slot[0] >= (0x300 / 4))
 474                a -= 32;
 475             fp->hdr[4 + a / 32] |= m << (a % 32);
 476          }
 477       }
 478    }
 479
 480    for (i = 0; i < info->numOutputs; ++i) {
 481       if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
 482          fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
 483    }
 484
 485    fp->fp.early_z = info->prop.fp.earlyFragTests;
 486
 487    return 0;
 488 }
 489
 490 static struct nvc0_transform_feedback_state *
 491 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
 492                               const struct pipe_stream_output_info *pso)
 493 {
 494    struct nvc0_transform_feedback_state *tfb;
 495    unsigned b, i, c;
 496
 497    tfb = MALLOC_STRUCT(nvc0_transform_feedback_state);
 498    if (!tfb)
 499       return NULL;
 500    for (b = 0; b < 4; ++b) {
 501       tfb->stride[b] = pso->stride[b] * 4;
 502       tfb->varying_count[b] = 0;
 503    }
 504    memset(tfb->varying_index, 0xff, sizeof(tfb->varying_index)); /* = skip */
 505
 506    for (i = 0; i < pso->num_outputs; ++i) {
 507       unsigned s = pso->output[i].start_component;
 508       unsigned p = pso->output[i].dst_offset;
 509       b = pso->output[i].output_buffer;
 510
 511       for (c = 0; c < pso->output[i].num_components; ++c)
 512          tfb->varying_index[b][p++] =
 513             info->out[pso->output[i].register_index].slot[s + c];
 514
 515       tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
 516    }
 517    for (b = 0; b < 4; ++b) // zero unused indices (looks nicer)
 518       for (c = tfb->varying_count[b]; c & 3; ++c)
 519          tfb->varying_index[b][c] = 0;
 520
 521    return tfb;
 522 }
 523
 524 #ifdef DEBUG
 525 static void
 526 nvc0_program_dump(struct nvc0_program *prog)
 527 {
 528    unsigned pos;
 529
 530    for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
 531       debug_printf("HDR[%02lx] = 0x%08x\n",
 532                    pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
 533
 534    debug_printf("shader binary code (0x%x bytes):", prog->code_size);
 535    for (pos = 0; pos < prog->code_size / 4; ++pos) {
 536       if ((pos % 8) == 0)
 537          debug_printf("\n");
 538       debug_printf("%08x ", prog->code[pos]);
 539    }
 540    debug_printf("\n");
 541 }
 542 #endif
 543
 544 boolean
 545 nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
 546 {
 547    struct nv50_ir_prog_info *info;
 548    int ret;
 549
 550    info = CALLOC_STRUCT(nv50_ir_prog_info);
 551    if (!info)
 552       return FALSE;
 553
 554    info->type = prog->type;
 555    info->target = chipset;
 556    info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
 557    info->bin.source = (void *)prog->pipe.tokens;
 558
 559    info->io.genUserClip = prog->vp.num_ucps;
 560    info->io.ucpBase = 256;
 561    info->io.ucpBinding = 15;
 562
 563    info->assignSlots = nvc0_program_assign_varying_slots;
 564
 565 #ifdef DEBUG
 566    info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
 567    info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
 568 #else
 569    info->optLevel = 3;
 570 #endif
 571
 572    ret = nv50_ir_generate_code(info);
 573    if (ret) {
 574       NOUVEAU_ERR("shader translation failed: %i\n", ret);
 575       goto out;
 576    }
 577    FREE(info->bin.syms);
 578
 579    prog->code = info->bin.code;
 580    prog->code_size = info->bin.codeSize;
 581    prog->immd_data = info->immd.buf;
 582    prog->immd_size = info->immd.bufSize;
 583    prog->relocs = info->bin.relocData;
 584    prog->max_gpr = MAX2(4, (info->bin.maxGPR + 1));
 585
 586    prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
 587
 588    if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
 589       info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
 590    prog->vp.edgeflag = info->io.edgeFlagIn;
 591
 592    switch (prog->type) {
 593    case PIPE_SHADER_VERTEX:
 594       ret = nvc0_vp_gen_header(prog, info);
 595       break;
 596 #ifdef PIPE_SHADER_HULL
 597    case PIPE_SHADER_HULL:
 598       ret = nvc0_tcp_gen_header(prog, info);
 599       break;
 600 #endif
 601 #ifdef PIPE_SHADER_DOMAIN
 602    case PIPE_SHADER_DOMAIN:
 603       ret = nvc0_tep_gen_header(prog, info);
 604       break;
 605 #endif
 606    case PIPE_SHADER_GEOMETRY:
 607       ret = nvc0_gp_gen_header(prog, info);
 608       break;
 609    case PIPE_SHADER_FRAGMENT:
 610       ret = nvc0_fp_gen_header(prog, info);
 611       break;
 612    default:
 613       ret = -1;
 614       NOUVEAU_ERR("unknown program type: %u\n", prog->type);
 615       break;
 616    }
 617    if (ret)
 618       goto out;
 619
 620    if (info->bin.tlsSpace) {
 621       assert(info->bin.tlsSpace < (1 << 24));
 622       prog->hdr[0] |= 1 << 26;
 623       prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
 624       prog->need_tls = TRUE;
 625    }
 626    /* TODO: factor 2 only needed where joinat/precont is used,
 627     *       and we only have to count non-uniform branches
 628     */
 629    /*
 630    if ((info->maxCFDepth * 2) > 16) {
 631       prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
 632       prog->need_tls = TRUE;
 633    }
 634    */
 635    if (info->io.globalAccess)
 636       prog->hdr[0] |= 1 << 16;
 637
 638    if (prog->pipe.stream_output.num_outputs)
 639       prog->tfb = nvc0_program_create_tfb_state(info,
 640                                                 &prog->pipe.stream_output);
 641
 642 out:
 643    FREE(info);
 644    return !ret;
 645 }
 646
 647 boolean
 648 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
 649 {
 650    struct nvc0_screen *screen = nvc0->screen;
 651    int ret;
 652    uint32_t size = prog->code_size + NVC0_SHADER_HEADER_SIZE;
 653    uint32_t lib_pos = screen->lib_code->start;
 654    uint32_t code_pos;
 655
 656    /* c[] bindings need to be aligned to 0x100, but we could use relocations
 657     * to save space. */
 658    if (prog->immd_size) {
 659       prog->immd_base = size;
 660       size = align(size, 0x40);
 661       size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
 662    }
 663    /* On Fermi, SP_START_ID must be aligned to 0x40.
 664     * On Kepler, the first instruction must be aligned to 0x80 because
 665     * latency information is expected only at certain positions.
 666     */
 667    if (screen->base.class_3d >= NVE4_3D_CLASS)
 668       size = size + 0x70;
 669    size = align(size, 0x40);
 670
 671    ret = nouveau_heap_alloc(screen->text_heap, size, prog, &prog->mem);
 672    if (ret) {
 673       NOUVEAU_ERR("out of code space\n");
 674       return FALSE;
 675    }
 676    prog->code_base = prog->mem->start;
 677    prog->immd_base = align(prog->mem->start + prog->immd_base, 0x100);
 678    assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <=
 679                                      prog->mem->start + prog->mem->size));
 680
 681    if (screen->base.class_3d >= NVE4_3D_CLASS) {
 682       switch (prog->mem->start & 0xff) {
 683       case 0x40: prog->code_base += 0x70; break;
 684       case 0x80: prog->code_base += 0x30; break;
 685       case 0xc0: prog->code_base += 0x70; break;
 686       default:
 687          prog->code_base += 0x30;
 688          assert((prog->mem->start & 0xff) == 0x00);
 689          break;
 690       }
 691    }
 692    code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
 693
 694    if (prog->relocs)
 695       nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
 696
 697 #ifdef DEBUG
 698    if (debug_get_bool_option("NV50_PROG_DEBUG", FALSE))
 699       nvc0_program_dump(prog);
 700 #endif
 701
 702    nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base,
 703                         NOUVEAU_BO_VRAM, NVC0_SHADER_HEADER_SIZE, prog->hdr);
 704    nvc0->base.push_data(&nvc0->base, screen->text,
 705                         prog->code_base + NVC0_SHADER_HEADER_SIZE,
 706                         NOUVEAU_BO_VRAM, prog->code_size, prog->code);
 707    if (prog->immd_size)
 708       nvc0->base.push_data(&nvc0->base,
 709                            screen->text, prog->immd_base, NOUVEAU_BO_VRAM,
 710                            prog->immd_size, prog->immd_data);
 711
 712    BEGIN_NVC0(nvc0->base.pushbuf, NVC0_3D(MEM_BARRIER), 1);
 713    PUSH_DATA (nvc0->base.pushbuf, 0x1011);
 714
 715    return TRUE;
 716 }
 717
 718 /* Upload code for builtin functions like integer division emulation. */
 719 void
 720 nvc0_program_library_upload(struct nvc0_context *nvc0)
 721 {
 722    struct nvc0_screen *screen = nvc0->screen;
 723    int ret;
 724    uint32_t size;
 725    const uint32_t *code;
 726
 727    if (screen->lib_code)
 728       return;
 729
 730    nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
 731    if (!size)
 732       return;
 733
 734    ret = nouveau_heap_alloc(screen->text_heap, align(size, 0x100), NULL,
 735                             &screen->lib_code);
 736    if (ret)
 737       return;
 738
 739    nvc0->base.push_data(&nvc0->base,
 740                         screen->text, screen->lib_code->start, NOUVEAU_BO_VRAM,
 741                         size, code);
 742    /* no need for a memory barrier, will be emitted with first program */
 743 }
 744
 745 void
 746 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
 747 {
 748    const struct pipe_shader_state pipe = prog->pipe;
 749    const ubyte type = prog->type;
 750
 751    if (prog->mem)
 752       nouveau_heap_free(&prog->mem);
 753
 754    FREE(prog->code);
 755    FREE(prog->immd_data);
 756    FREE(prog->relocs);
 757    if (prog->tfb) {
 758       if (nvc0->state.tfb == prog->tfb)
 759          nvc0->state.tfb = NULL;
 760       FREE(prog->tfb);
 761    }
 762
 763    memset(prog, 0, sizeof(*prog));
 764
 765    prog->pipe = pipe;
 766    prog->type = type;
 767 }