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eaad08059097f762125f8b23166352ba180bd1c5
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_program.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24
25 #include "nvc0_context.h"
26
27 #include "nv50/codegen/nv50_ir_driver.h"
28
29 /* If only they told use the actual semantic instead of just GENERIC ... */
30 static void
31 nvc0_mesa_varying_hack(struct nv50_ir_varying *var)
32 {
33 unsigned c;
34
35 if (var->sn != TGSI_SEMANTIC_GENERIC)
36 return;
37
38 if (var->si <= 7) /* gl_TexCoord */
39 for (c = 0; c < 4; ++c)
40 var->slot[c] = (0x300 + var->si * 0x10 + c * 0x4) / 4;
41 else
42 if (var->si == 9) /* gl_PointCoord */
43 for (c = 0; c < 4; ++c)
44 var->slot[c] = (0x2e0 + c * 0x4) / 4;
45 else
46 for (c = 0; c < 4; ++c) /* move down user varyings (first has index 8) */
47 var->slot[c] -= 0x80 / 4;
48 }
49
50 static uint32_t
51 nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
52 {
53 switch (sn) {
54 /* case TGSI_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4; */
55 case TGSI_SEMANTIC_PRIMID: return 0x060;
56 case TGSI_SEMANTIC_PSIZE: return 0x06c;
57 case TGSI_SEMANTIC_POSITION: return 0x070;
58 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
59 case TGSI_SEMANTIC_FOG: return 0x270;
60 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
61 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
62 /* case TGSI_SEMANTIC_CLIP: return 0x2c0 + si * 0x10; */
63 /* case TGSI_SEMANTIC_POINTCOORD: return 0x2e0; */
64 /* case TGSI_SEMANTIC_TESSCOORD: return ~0; */ /* 0x2f0, but special load */
65 case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
66 /* case TGSI_SEMANTIC_VERTEXID: return 0x2fc; */
67 /* case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10; */
68 case TGSI_SEMANTIC_FACE: return 0x3fc;
69 /* case TGSI_SEMANTIC_INVOCATIONID: return ~0; */
70 default:
71 assert(!"invalid TGSI input semantic");
72 return ~0;
73 }
74 }
75
76 static uint32_t
77 nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
78 {
79 switch (sn) {
80 /* case TGSI_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4; */
81 case TGSI_SEMANTIC_PRIMID: return 0x040;
82 /* case TGSI_SEMANTIC_LAYER: return 0x064; */
83 /* case TGSI_SEMANTIC_VIEWPORTINDEX: return 0x068; */
84 case TGSI_SEMANTIC_PSIZE: return 0x06c;
85 case TGSI_SEMANTIC_POSITION: return 0x070;
86 case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
87 case TGSI_SEMANTIC_FOG: return 0x270;
88 case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
89 case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
90 /* case TGSI_SEMANTIC_CLIP: return 0x2c0 + si * 0x10; */
91 /* case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10; */
92 case TGSI_SEMANTIC_EDGEFLAG: return ~0;
93 default:
94 assert(!"invalid TGSI output semantic");
95 return ~0;
96 }
97 }
98
99 static int
100 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
101 {
102 unsigned i, c;
103
104 for (i = 0; i < info->numInputs; ++i)
105 for (c = 0; c < 4; ++c)
106 info->in[i].slot[c] = (0x80 + i * 0x10 + c * 0x4) / 4;
107
108 return 0;
109 }
110
111 static int
112 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
113 {
114 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
115 unsigned offset;
116 unsigned i, c;
117
118 for (i = 0; i < info->numInputs; ++i) {
119 offset = nvc0_shader_input_address(info->in[i].sn,
120 info->in[i].si, ubase);
121 if (info->in[i].patch && offset >= 0x20)
122 offset = 0x20 + info->in[i].si * 0x10;
123
124 for (c = 0; c < 4; ++c)
125 info->in[i].slot[c] = (offset + c * 0x4) / 4;
126
127 nvc0_mesa_varying_hack(&info->in[i]);
128 }
129
130 return 0;
131 }
132
133 static int
134 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
135 {
136 unsigned last = info->prop.fp.numColourResults * 4;
137 unsigned i, c;
138
139 for (i = 0; i < info->numOutputs; ++i)
140 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
141 for (c = 0; c < 4; ++c)
142 info->out[i].slot[c] = info->out[i].si * 4 + c;
143
144 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
145 info->out[info->io.sampleMask].slot[0] = last++;
146
147 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
148 info->out[info->io.fragDepth].slot[2] = last;
149
150 return 0;
151 }
152
153 static int
154 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
155 {
156 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
157 unsigned offset;
158 unsigned i, c;
159
160 for (i = 0; i < info->numOutputs; ++i) {
161 offset = nvc0_shader_output_address(info->out[i].sn,
162 info->out[i].si, ubase);
163 if (info->out[i].patch && offset >= 0x20)
164 offset = 0x20 + info->out[i].si * 0x10;
165
166 for (c = 0; c < 4; ++c)
167 info->out[i].slot[c] = (offset + c * 0x4) / 4;
168
169 nvc0_mesa_varying_hack(&info->out[i]);
170 }
171
172 return 0;
173 }
174
175 static int
176 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
177 {
178 int ret;
179
180 if (info->type == PIPE_SHADER_VERTEX)
181 ret = nvc0_vp_assign_input_slots(info);
182 else
183 ret = nvc0_sp_assign_input_slots(info);
184 if (ret)
185 return ret;
186
187 if (info->type == PIPE_SHADER_FRAGMENT)
188 ret = nvc0_fp_assign_output_slots(info);
189 else
190 ret = nvc0_sp_assign_output_slots(info);
191 return ret;
192 }
193
194 static INLINE void
195 nvc0_vtgp_hdr_update_oread(struct nvc0_program *vp, uint8_t slot)
196 {
197 uint8_t min = (vp->hdr[4] >> 12) & 0xff;
198 uint8_t max = (vp->hdr[4] >> 24);
199
200 min = MIN2(min, slot);
201 max = MAX2(max, slot);
202
203 vp->hdr[4] = (max << 24) | (min << 12);
204 }
205
206 /* Common part of header generation for VP, TCP, TEP and GP. */
207 static int
208 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
209 {
210 unsigned i, c, a;
211
212 for (i = 0; i < info->numInputs; ++i) {
213 if (info->in[i].patch)
214 continue;
215 for (c = 0; c < 4; ++c) {
216 a = info->in[i].slot[c];
217 if (info->in[i].mask & (1 << c))
218 vp->hdr[5 + a / 32] |= 1 << (a % 32);
219 }
220 }
221
222 for (i = 0; i < info->numOutputs; ++i) {
223 if (info->out[i].patch)
224 continue;
225 for (c = 0; c < 4; ++c) {
226 if (!(info->out[i].mask & (1 << c)))
227 continue;
228 assert(info->out[i].slot[c] >= 0x40 / 4);
229 a = info->out[i].slot[c] - 0x40 / 4;
230 vp->hdr[13 + a / 32] |= 1 << (a % 32);
231 if (info->out[i].oread)
232 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
233 }
234 }
235
236 for (i = 0; i < info->numSysVals; ++i) {
237 switch (info->sv[i].sn) {
238 case TGSI_SEMANTIC_PRIMID:
239 vp->hdr[5] |= 1 << 24;
240 break;
241 case TGSI_SEMANTIC_INSTANCEID:
242 vp->hdr[10] |= 1 << 30;
243 break;
244 /*
245 case TGSI_SEMANTIC_VERTEXID:
246 vp->hdr[10] |= 1 << 31;
247 break;
248 */
249 default:
250 break;
251 }
252 }
253
254 return 0;
255 }
256
257 static int
258 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
259 {
260 vp->hdr[0] = 0x20061 | (1 << 10);
261 vp->hdr[4] = 0xff000;
262
263 vp->hdr[18] = (1 << info->io.clipDistanceCount) - 1;
264
265 return nvc0_vtgp_gen_header(vp, info);
266 }
267
268 #if defined(PIPE_SHADER_HULL) || defined(PIPE_SHADER_DOMAIN)
269 static void
270 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
271 {
272 switch (info->prop.tp.domain) {
273 case PIPE_PRIM_LINES:
274 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_ISOLINES;
275 break;
276 case PIPE_PRIM_TRIANGLES:
277 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
278 if (info->prop.tp.winding > 0)
279 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
280 break;
281 case PIPE_PRIM_QUADS:
282 tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
283 break;
284 default:
285 tp->tp.tess_mode = ~0;
286 return;
287 }
288 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
289 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
290
291 switch (info->prop.tp.partitioning) {
292 case PIPE_TESS_PART_INTEGER:
293 case PIPE_TESS_PART_POW2:
294 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
295 break;
296 case PIPE_TESS_PART_FRACT_ODD:
297 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
298 break;
299 case PIPE_TESS_PART_FRACT_EVEN:
300 tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
301 break;
302 default:
303 assert(!"invalid tessellator partitioning");
304 break;
305 }
306 }
307 #endif
308
309 #ifdef PIPE_SHADER_HULL
310 static int
311 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
312 {
313 unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
314
315 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
316
317 if (info->numPatchConstants)
318 opcs = 8 + info->numPatchConstants * 4;
319
320 tcp->hdr[0] = 0x20061 | (2 << 10);
321
322 tcp->hdr[1] = opcs << 24;
323 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
324
325 tcp->hdr[4] = 0xff000; /* initial min/max parallel output read address */
326
327 nvc0_vtgp_gen_header(tcp, info);
328
329 nvc0_tp_get_tess_mode(tcp, info);
330
331 return 0;
332 }
333 #endif
334
335 #ifdef PIPE_SHADER_DOMAIN
336 static int
337 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
338 {
339 tep->hdr[0] = 0x20061 | (3 << 10);
340 tep->hdr[4] = 0xff000;
341
342 nvc0_vtgp_gen_header(tep, info);
343
344 nvc0_tp_get_tess_mode(tep, info);
345
346 tep->hdr[18] |= 0x3 << 12; /* ? */
347
348 return 0;
349 }
350 #endif
351
352 static int
353 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
354 {
355 gp->hdr[0] = 0x20061 | (4 << 10);
356
357 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
358
359 switch (info->prop.gp.outputPrim) {
360 case PIPE_PRIM_POINTS:
361 gp->hdr[3] = 0x01000000;
362 gp->hdr[0] |= 0xf0000000;
363 break;
364 case PIPE_PRIM_LINE_STRIP:
365 gp->hdr[3] = 0x06000000;
366 gp->hdr[0] |= 0x10000000;
367 break;
368 case PIPE_PRIM_TRIANGLE_STRIP:
369 gp->hdr[3] = 0x07000000;
370 gp->hdr[0] |= 0x10000000;
371 break;
372 default:
373 assert(0);
374 break;
375 }
376
377 gp->hdr[4] = info->prop.gp.maxVertices & 0x1ff;
378
379 return nvc0_vtgp_gen_header(gp, info);
380 }
381
382 #define NVC0_INTERP_FLAT (1 << 0)
383 #define NVC0_INTERP_PERSPECTIVE (2 << 0)
384 #define NVC0_INTERP_LINEAR (3 << 0)
385 #define NVC0_INTERP_CENTROID (1 << 2)
386
387 static uint8_t
388 nvc0_hdr_interp_mode(const struct nv50_ir_varying *var)
389 {
390 if (var->linear)
391 return NVC0_INTERP_LINEAR;
392 if (var->flat)
393 return NVC0_INTERP_FLAT;
394 return NVC0_INTERP_PERSPECTIVE;
395 }
396
397 static int
398 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
399 {
400 unsigned i, c, a, m;
401
402 fp->hdr[0] = 0x20062 | (5 << 10);
403 fp->hdr[5] = 0x80000000; /* getting a trap if FRAG_COORD_UMASK.w = 0 */
404
405 if (info->prop.fp.usesDiscard)
406 fp->hdr[0] |= 0x8000;
407 if (info->prop.fp.numColourResults > 1)
408 fp->hdr[0] |= 0x4000;
409 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
410 fp->hdr[19] |= 0x1;
411 if (info->prop.fp.writesDepth) {
412 fp->hdr[19] |= 0x2;
413 fp->flags[0] = 0x11; /* deactivate ZCULL */
414 }
415
416 for (i = 0; i < info->numInputs; ++i) {
417 m = nvc0_hdr_interp_mode(&info->in[i]);
418 for (c = 0; c < 4; ++c) {
419 if (!(info->in[i].mask & (1 << c)))
420 continue;
421 if (info->in[i].slot[0] == (0x070 / 4)) {
422 fp->hdr[5] |= 1 << (28 + c);
423 } else
424 if (info->in[i].slot[0] == (0x2e0 / 4)) {
425 if (c <= 1)
426 fp->hdr[14] |= 1 << (24 + c);
427 } else {
428 if (info->in[i].slot[c] < (0x040 / 4) ||
429 info->in[i].slot[c] > (0x380 / 4))
430 continue;
431 a = info->in[i].slot[c] * 2;
432 if (info->in[i].slot[0] >= (0x2c0 / 4))
433 a -= 32;
434 fp->hdr[4 + a / 32] |= m << (a % 32);
435 }
436 }
437 }
438
439 for (i = 0; i < info->numOutputs; ++i) {
440 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
441 fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
442 }
443
444 fp->fp.early_z = info->prop.fp.earlyFragTests;
445 if (fp->fp.early_z == FALSE && fp->code_size >= 0x400)
446 fp->fp.early_z = !(info->prop.fp.writesDepth ||
447 info->prop.fp.usesDiscard ||
448 (info->io.globalAccess & 2));
449
450 return 0;
451 }
452
453 #ifdef DEBUG
454 static void
455 nvc0_program_dump(struct nvc0_program *prog)
456 {
457 unsigned pos;
458
459 for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
460 debug_printf("HDR[%02lx] = 0x%08x\n",
461 pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
462
463 debug_printf("shader binary code (0x%x bytes):", prog->code_size);
464 for (pos = 0; pos < prog->code_size / 4; ++pos) {
465 if ((pos % 8) == 0)
466 debug_printf("\n");
467 debug_printf("%08x ", prog->code[pos]);
468 }
469 debug_printf("\n");
470 }
471 #endif
472
473 boolean
474 nvc0_program_translate(struct nvc0_program *prog)
475 {
476 struct nv50_ir_prog_info *info;
477 int ret;
478
479 info = CALLOC_STRUCT(nv50_ir_prog_info);
480 if (!info)
481 return FALSE;
482
483 info->type = prog->type;
484 info->target = 0xc0;
485 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
486 info->bin.source = (void *)prog->pipe.tokens;
487
488 info->io.clipDistanceCount = prog->vp.num_ucps;
489
490 info->assignSlots = nvc0_program_assign_varying_slots;
491
492 #ifdef DEBUG
493 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
494 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
495 #else
496 info->optLevel = 3;
497 #endif
498
499 ret = nv50_ir_generate_code(info);
500 if (ret) {
501 NOUVEAU_ERR("shader translation failed: %i\n", ret);
502 goto out;
503 }
504
505 prog->code = info->bin.code;
506 prog->code_size = info->bin.codeSize;
507 prog->immd_data = info->immd.buf;
508 prog->immd_size = info->immd.bufSize;
509 prog->relocs = info->bin.relocData;
510 prog->max_gpr = MAX2(4, (info->bin.maxGPR + 1));
511
512 prog->vp.edgeflag = PIPE_MAX_ATTRIBS;
513
514 switch (prog->type) {
515 case PIPE_SHADER_VERTEX:
516 ret = nvc0_vp_gen_header(prog, info);
517 break;
518 #ifdef PIPE_SHADER_HULL
519 case PIPE_SHADER_HULL:
520 ret = nvc0_tcp_gen_header(prog, info);
521 break;
522 #endif
523 #ifdef PIPE_SHADER_DOMAIN
524 case PIPE_SHADER_DOMAIN:
525 ret = nvc0_tep_gen_header(prog, info);
526 break;
527 #endif
528 case PIPE_SHADER_GEOMETRY:
529 ret = nvc0_gp_gen_header(prog, info);
530 break;
531 case PIPE_SHADER_FRAGMENT:
532 ret = nvc0_fp_gen_header(prog, info);
533 break;
534 default:
535 ret = -1;
536 NOUVEAU_ERR("unknown program type: %u\n", prog->type);
537 break;
538 }
539 if (ret)
540 goto out;
541
542 if (info->bin.tlsSpace) {
543 assert(info->bin.tlsSpace < (1 << 24));
544 prog->hdr[0] |= 1 << 26;
545 prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */
546 }
547 if (info->io.globalAccess)
548 prog->hdr[0] |= 1 << 16;
549
550 out:
551 FREE(info);
552 return !ret;
553 }
554
555 boolean
556 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
557 {
558 struct nvc0_screen *screen = nvc0->screen;
559 int ret;
560 uint32_t size = prog->code_size + NVC0_SHADER_HEADER_SIZE;
561 uint32_t lib_pos = screen->lib_code->start;
562 uint32_t code_pos;
563
564 /* c[] bindings need to be aligned to 0x100, but we could use relocations
565 * to save space. */
566 if (prog->immd_size) {
567 prog->immd_base = size;
568 size = align(size, 0x40);
569 size += prog->immd_size + 0xc0; /* add 0xc0 for align 0x40 -> 0x100 */
570 }
571 size = align(size, 0x40); /* required by SP_START_ID */
572
573 ret = nouveau_resource_alloc(screen->text_heap, size, prog, &prog->res);
574 if (ret) {
575 NOUVEAU_ERR("out of code space\n");
576 return FALSE;
577 }
578 prog->code_base = prog->res->start;
579 prog->immd_base = align(prog->res->start + prog->immd_base, 0x100);
580 assert((prog->immd_size == 0) || (prog->immd_base + prog->immd_size <
581 prog->res->start + prog->res->size));
582
583 code_pos = prog->code_base + NVC0_SHADER_HEADER_SIZE;
584
585 if (prog->relocs)
586 nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
587
588 #ifdef DEBUG
589 if (debug_get_bool_option("NV50_PROG_DEBUG", FALSE))
590 nvc0_program_dump(prog);
591 #endif
592
593 nvc0_m2mf_push_linear(&nvc0->base, screen->text, prog->code_base,
594 NOUVEAU_BO_VRAM, NVC0_SHADER_HEADER_SIZE, prog->hdr);
595 nvc0_m2mf_push_linear(&nvc0->base, screen->text,
596 prog->code_base + NVC0_SHADER_HEADER_SIZE,
597 NOUVEAU_BO_VRAM, prog->code_size, prog->code);
598 if (prog->immd_size)
599 nvc0_m2mf_push_linear(&nvc0->base,
600 screen->text, prog->immd_base, NOUVEAU_BO_VRAM,
601 prog->immd_size, prog->immd_data);
602
603 BEGIN_RING(screen->base.channel, RING_3D(MEM_BARRIER), 1);
604 OUT_RING (screen->base.channel, 0x1111);
605
606 return TRUE;
607 }
608
609 /* Upload code for builtin functions like integer division emulation. */
610 void
611 nvc0_program_library_upload(struct nvc0_context *nvc0)
612 {
613 struct nvc0_screen *screen = nvc0->screen;
614 int ret;
615 uint32_t size;
616 const uint32_t *code;
617
618 if (screen->lib_code)
619 return;
620
621 nv50_ir_get_target_library(screen->base.device->chipset, &code, &size);
622 if (!size)
623 return;
624
625 ret = nouveau_resource_alloc(screen->text_heap, align(size, 0x100), NULL,
626 &screen->lib_code);
627 if (ret)
628 return;
629
630 nvc0_m2mf_push_linear(&nvc0->base,
631 screen->text, screen->lib_code->start, NOUVEAU_BO_VRAM,
632 size, code);
633 /* no need for a memory barrier, will be emitted with first program */
634 }
635
636 void
637 nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
638 {
639 if (prog->res)
640 nouveau_resource_free(&prog->res);
641
642 if (prog->code)
643 FREE(prog->code);
644 if (prog->immd_data)
645 FREE(prog->immd_data);
646 if (prog->relocs)
647 FREE(prog->relocs);
648
649 memset(prog->hdr, 0, sizeof(prog->hdr));
650
651 prog->translated = FALSE;
652 }