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2 #ifndef __NVC0_RESOURCE_H__
3 #define __NVC0_RESOURCE_H__
5 #include "util/u_transfer.h"
6 #include "util/u_double_list.h"
8 #include "nouveau/nouveau_winsys.h"
11 #include "nvc0_fence.h"
16 /* Resources, if mapped into the GPU's address space, are guaranteed to
17 * have constant virtual addresses.
18 * The address of a resource will lie within the nouveau_bo referenced,
19 * and this bo should be added to the memory manager's validation list.
21 struct nvc0_resource
{
22 struct pipe_resource base
;
23 const struct u_resource_vtbl
*vtbl
;
27 struct nouveau_bo
*bo
;
33 int16_t score
; /* low if mapped very often, if high can move to VRAM */
35 struct nvc0_fence
*fence
;
36 struct nvc0_fence
*fence_wr
;
38 struct nvc0_mm_allocation
*mm
;
41 /* XXX: wait for fence (atm only using this for vertex push) */
43 nvc0_resource_map_offset(struct nvc0_resource
*res
, uint32_t offset
,
49 return res
->data
+ offset
;
51 if (nouveau_bo_map_range(res
->bo
, res
->offset
+ offset
,
52 res
->base
.width0
, flags
| NOUVEAU_BO_NOSYNC
))
55 /* With suballocation, the same bo can be mapped several times, so unmap
56 * immediately. Maps are guaranteed to persist. */
58 nouveau_bo_unmap(res
->bo
);
63 nvc0_resource_unmap(struct nvc0_resource
*res
)
65 if (res
->domain
!= 0 && 0)
66 nouveau_bo_unmap(res
->bo
);
69 #define NVC0_TILE_PITCH(m) (64 << ((m) & 0xf))
70 #define NVC0_TILE_HEIGHT(m) (8 << (((m) >> 4) & 0xf))
71 #define NVC0_TILE_DEPTH(m) (1 << ((m) >> 8))
73 #define NVC0_TILE_SIZE(m) \
74 (NVC0_TILE_PITCH(m) * NVC0_TILE_HEIGHT(m) * NVC0_TILE_DEPTH(m))
76 struct nvc0_miptree_level
{
82 #define NVC0_MAX_TEXTURE_LEVELS 16
85 struct nvc0_resource base
;
86 struct nvc0_miptree_level level
[NVC0_MAX_TEXTURE_LEVELS
];
88 uint32_t layer_stride
;
89 boolean layout_3d
; /* TRUE if layer count varies with mip level */
92 static INLINE
struct nvc0_miptree
*
93 nvc0_miptree(struct pipe_resource
*pt
)
95 return (struct nvc0_miptree
*)pt
;
98 static INLINE
struct nvc0_resource
*
99 nvc0_resource(struct pipe_resource
*resource
)
101 return (struct nvc0_resource
*)resource
;
104 /* is resource mapped into the GPU's address space (i.e. VRAM or GART) ? */
105 static INLINE boolean
106 nvc0_resource_mapped_by_gpu(struct pipe_resource
*resource
)
108 return nvc0_resource(resource
)->domain
!= 0;
112 nvc0_init_resource_functions(struct pipe_context
*pcontext
);
115 nvc0_screen_init_resource_functions(struct pipe_screen
*pscreen
);
117 /* Internal functions:
119 struct pipe_resource
*
120 nvc0_miptree_create(struct pipe_screen
*pscreen
,
121 const struct pipe_resource
*tmp
);
123 struct pipe_resource
*
124 nvc0_miptree_from_handle(struct pipe_screen
*pscreen
,
125 const struct pipe_resource
*template,
126 struct winsys_handle
*whandle
);
128 struct pipe_resource
*
129 nvc0_buffer_create(struct pipe_screen
*pscreen
,
130 const struct pipe_resource
*templ
);
132 struct pipe_resource
*
133 nvc0_user_buffer_create(struct pipe_screen
*screen
,
139 struct pipe_surface
*
140 nvc0_miptree_surface_new(struct pipe_context
*,
141 struct pipe_resource
*,
142 const struct pipe_surface
*templ
);
145 nvc0_miptree_surface_del(struct pipe_context
*, struct pipe_surface
*);
150 nvc0_buffer_migrate(struct nvc0_context
*,
151 struct nvc0_resource
*, unsigned domain
);
154 nvc0_migrate_vertices(struct nvc0_resource
*buf
, unsigned base
, unsigned size
);