b9f3f7b5d81d1d0f8f260f31c25c7fb46ab4de47
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_resource.h
1
2 #ifndef __NVC0_RESOURCE_H__
3 #define __NVC0_RESOURCE_H__
4
5 #include "util/u_transfer.h"
6 #include "util/u_double_list.h"
7 #define NOUVEAU_NVC0
8 #include "nouveau/nouveau_winsys.h"
9 #undef NOUVEAU_NVC0
10
11 #include "nvc0_fence.h"
12
13 struct pipe_resource;
14 struct nouveau_bo;
15
16 /* Resources, if mapped into the GPU's address space, are guaranteed to
17 * have constant virtual addresses.
18 * The address of a resource will lie within the nouveau_bo referenced,
19 * and this bo should be added to the memory manager's validation list.
20 */
21 struct nvc0_resource {
22 struct pipe_resource base;
23 const struct u_resource_vtbl *vtbl;
24 uint64_t address;
25
26 uint8_t *data;
27 struct nouveau_bo *bo;
28 uint32_t offset;
29
30 uint8_t status;
31 uint8_t domain;
32
33 int16_t score; /* low if mapped very often, if high can move to VRAM */
34
35 struct nvc0_fence *fence;
36 struct nvc0_fence *fence_wr;
37
38 struct nvc0_mm_allocation *mm;
39 };
40
41 /* XXX: wait for fence (atm only using this for vertex push) */
42 static INLINE void *
43 nvc0_resource_map_offset(struct nvc0_resource *res, uint32_t offset,
44 uint32_t flags)
45 {
46 void *map;
47
48 if (res->domain == 0)
49 return res->data + offset;
50
51 if (nouveau_bo_map_range(res->bo, res->offset + offset,
52 res->base.width0, flags | NOUVEAU_BO_NOSYNC))
53 return NULL;
54
55 /* With suballocation, the same bo can be mapped several times, so unmap
56 * immediately. Maps are guaranteed to persist. */
57 map = res->bo->map;
58 nouveau_bo_unmap(res->bo);
59 return map;
60 }
61
62 static INLINE void
63 nvc0_resource_unmap(struct nvc0_resource *res)
64 {
65 if (res->domain != 0 && 0)
66 nouveau_bo_unmap(res->bo);
67 }
68
69 #define NVC0_TILE_H(m) (8 << ((m >> 4) & 0xf))
70 #define NVC0_TILE_D(m) (1 << (m >> 8))
71
72 struct nvc0_miptree_level {
73 int *image_offset;
74 uint32_t pitch;
75 uint32_t tile_mode;
76 };
77
78 #define NVC0_MAX_TEXTURE_LEVELS 16
79
80 struct nvc0_miptree {
81 struct nvc0_resource base;
82 struct nvc0_miptree_level level[NVC0_MAX_TEXTURE_LEVELS];
83 int image_nr;
84 int total_size;
85 };
86
87 static INLINE struct nvc0_miptree *
88 nvc0_miptree(struct pipe_resource *pt)
89 {
90 return (struct nvc0_miptree *)pt;
91 }
92
93 static INLINE struct nvc0_resource *
94 nvc0_resource(struct pipe_resource *resource)
95 {
96 return (struct nvc0_resource *)resource;
97 }
98
99 /* is resource mapped into the GPU's address space (i.e. VRAM or GART) ? */
100 static INLINE boolean
101 nvc0_resource_mapped_by_gpu(struct pipe_resource *resource)
102 {
103 return nvc0_resource(resource)->domain != 0;
104 }
105
106 void
107 nvc0_init_resource_functions(struct pipe_context *pcontext);
108
109 void
110 nvc0_screen_init_resource_functions(struct pipe_screen *pscreen);
111
112 /* Internal functions:
113 */
114 struct pipe_resource *
115 nvc0_miptree_create(struct pipe_screen *pscreen,
116 const struct pipe_resource *tmp);
117
118 struct pipe_resource *
119 nvc0_miptree_from_handle(struct pipe_screen *pscreen,
120 const struct pipe_resource *template,
121 struct winsys_handle *whandle);
122
123 struct pipe_resource *
124 nvc0_buffer_create(struct pipe_screen *pscreen,
125 const struct pipe_resource *templ);
126
127 struct pipe_resource *
128 nvc0_user_buffer_create(struct pipe_screen *screen,
129 void *ptr,
130 unsigned bytes,
131 unsigned usage);
132
133
134 struct pipe_surface *
135 nvc0_miptree_surface_new(struct pipe_screen *pscreen, struct pipe_resource *pt,
136 unsigned face, unsigned level, unsigned zslice,
137 unsigned flags);
138
139 void
140 nvc0_miptree_surface_del(struct pipe_surface *ps);
141
142 struct nvc0_context;
143
144 boolean
145 nvc0_buffer_migrate(struct nvc0_context *,
146 struct nvc0_resource *, unsigned domain);
147
148 boolean
149 nvc0_migrate_vertices(struct nvc0_resource *buf, unsigned base, unsigned size);
150
151 #endif