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Squash-merge branch 'gallium-clip-state'
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "nvc0_context.h"
31 #include "nvc0_screen.h"
32
33 #include "nouveau/nv_object.xml.h"
34 #include "nvc0_graph_macros.h"
35
36 static boolean
37 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
38 enum pipe_format format,
39 enum pipe_texture_target target,
40 unsigned sample_count,
41 unsigned bindings)
42 {
43 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
44 return FALSE;
45
46 if (!util_format_is_supported(format, bindings))
47 return FALSE;
48
49 switch (format) {
50 case PIPE_FORMAT_R8G8B8A8_UNORM:
51 case PIPE_FORMAT_R8G8B8X8_UNORM:
52 /* HACK: GL requires equal formats for MS resolve and window is BGRA */
53 if (bindings & PIPE_BIND_RENDER_TARGET)
54 return FALSE;
55 default:
56 break;
57 }
58
59 /* transfers & shared are always supported */
60 bindings &= ~(PIPE_BIND_TRANSFER_READ |
61 PIPE_BIND_TRANSFER_WRITE |
62 PIPE_BIND_SHARED);
63
64 return (nvc0_format_table[format].usage & bindings) == bindings;
65 }
66
67 static int
68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
69 {
70 switch (param) {
71 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
72 return 64;
73 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
74 return 13;
75 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
76 return 10;
77 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
78 return 13;
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
80 return 8192;
81 case PIPE_CAP_MIN_TEXEL_OFFSET:
82 return -8;
83 case PIPE_CAP_MAX_TEXEL_OFFSET:
84 return 7;
85 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
86 case PIPE_CAP_TEXTURE_SWIZZLE:
87 case PIPE_CAP_TEXTURE_SHADOW_MAP:
88 case PIPE_CAP_NPOT_TEXTURES:
89 case PIPE_CAP_ANISOTROPIC_FILTER:
90 case PIPE_CAP_SEAMLESS_CUBE_MAP:
91 return 1;
92 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
93 return 0;
94 case PIPE_CAP_TWO_SIDED_STENCIL:
95 case PIPE_CAP_DEPTH_CLIP_DISABLE:
96 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
97 case PIPE_CAP_POINT_SPRITE:
98 return 1;
99 case PIPE_CAP_SM3:
100 return 1;
101 case PIPE_CAP_MAX_RENDER_TARGETS:
102 return 8;
103 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
104 return 1;
105 case PIPE_CAP_TIMER_QUERY:
106 case PIPE_CAP_OCCLUSION_QUERY:
107 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
108 return 1;
109 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
110 return 4;
111 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
112 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
113 return 128;
114 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
115 case PIPE_CAP_INDEP_BLEND_ENABLE:
116 case PIPE_CAP_INDEP_BLEND_FUNC:
117 return 1;
118 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
119 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
120 return 1;
121 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
122 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
123 return 0;
124 case PIPE_CAP_SHADER_STENCIL_EXPORT:
125 return 0;
126 case PIPE_CAP_PRIMITIVE_RESTART:
127 case PIPE_CAP_TGSI_INSTANCEID:
128 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
129 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
130 case PIPE_CAP_CONDITIONAL_RENDER:
131 case PIPE_CAP_TEXTURE_BARRIER:
132 return 1;
133 default:
134 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
135 return 0;
136 }
137 }
138
139 static int
140 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
141 enum pipe_shader_cap param)
142 {
143 switch (shader) {
144 case PIPE_SHADER_VERTEX:
145 /*
146 case PIPE_SHADER_TESSELLATION_CONTROL:
147 case PIPE_SHADER_TESSELLATION_EVALUATION:
148 */
149 case PIPE_SHADER_GEOMETRY:
150 case PIPE_SHADER_FRAGMENT:
151 break;
152 default:
153 return 0;
154 }
155
156 switch (param) {
157 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
158 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
159 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
160 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
161 return 16384;
162 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
163 return 16;
164 case PIPE_SHADER_CAP_MAX_INPUTS:
165 if (shader == PIPE_SHADER_VERTEX)
166 return 32;
167 return 0x300 / 16;
168 case PIPE_SHADER_CAP_MAX_CONSTS:
169 return 65536 / 16;
170 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
171 return 14;
172 case PIPE_SHADER_CAP_MAX_ADDRS:
173 return 1;
174 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
175 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
176 return shader != PIPE_SHADER_FRAGMENT;
177 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
178 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
179 return 1;
180 case PIPE_SHADER_CAP_MAX_PREDS:
181 return 0;
182 case PIPE_SHADER_CAP_MAX_TEMPS:
183 return NVC0_CAP_MAX_PROGRAM_TEMPS;
184 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
185 return 1;
186 case PIPE_SHADER_CAP_SUBROUTINES:
187 return 1; /* but inlining everything, we need function declarations */
188 case PIPE_SHADER_CAP_INTEGERS:
189 return 1;
190 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
191 return 32;
192 default:
193 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
194 return 0;
195 }
196 }
197
198 static float
199 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
200 {
201 switch (param) {
202 case PIPE_CAPF_MAX_LINE_WIDTH:
203 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
204 return 10.0f;
205 case PIPE_CAPF_MAX_POINT_WIDTH:
206 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
207 return 64.0f;
208 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
209 return 16.0f;
210 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
211 return 4.0f;
212 default:
213 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
214 return 0.0f;
215 }
216 }
217
218 static void
219 nvc0_screen_destroy(struct pipe_screen *pscreen)
220 {
221 struct nvc0_screen *screen = nvc0_screen(pscreen);
222
223 if (screen->base.fence.current) {
224 nouveau_fence_wait(screen->base.fence.current);
225 nouveau_fence_ref(NULL, &screen->base.fence.current);
226 }
227 if (screen->base.channel)
228 screen->base.channel->user_private = NULL;
229
230 if (screen->blitctx)
231 FREE(screen->blitctx);
232
233 nouveau_bo_ref(NULL, &screen->text);
234 nouveau_bo_ref(NULL, &screen->tls);
235 nouveau_bo_ref(NULL, &screen->txc);
236 nouveau_bo_ref(NULL, &screen->fence.bo);
237 nouveau_bo_ref(NULL, &screen->vfetch_cache);
238
239 nouveau_resource_destroy(&screen->lib_code);
240 nouveau_resource_destroy(&screen->text_heap);
241
242 if (screen->tic.entries)
243 FREE(screen->tic.entries);
244
245 nouveau_mm_destroy(screen->mm_VRAM_fe0);
246
247 nouveau_grobj_free(&screen->fermi);
248 nouveau_grobj_free(&screen->eng2d);
249 nouveau_grobj_free(&screen->m2mf);
250
251 nouveau_screen_fini(&screen->base);
252
253 FREE(screen);
254 }
255
256 static int
257 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
258 unsigned size, const uint32_t *data)
259 {
260 struct nouveau_channel *chan = screen->base.channel;
261
262 size /= 4;
263
264 BEGIN_RING(chan, RING_3D_(NVC0_GRAPH_MACRO_ID), 2);
265 OUT_RING (chan, (m - 0x3800) / 8);
266 OUT_RING (chan, pos);
267 BEGIN_RING_1I(chan, RING_3D_(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
268 OUT_RING (chan, pos);
269 OUT_RINGp (chan, data, size);
270
271 return pos + size;
272 }
273
274 static void
275 nvc0_magic_3d_init(struct nouveau_channel *chan)
276 {
277 BEGIN_RING(chan, RING_3D_(0x10cc), 1);
278 OUT_RING (chan, 0xff);
279 BEGIN_RING(chan, RING_3D_(0x10e0), 2);
280 OUT_RING(chan, 0xff);
281 OUT_RING(chan, 0xff);
282 BEGIN_RING(chan, RING_3D_(0x10ec), 2);
283 OUT_RING(chan, 0xff);
284 OUT_RING(chan, 0xff);
285 BEGIN_RING(chan, RING_3D_(0x074c), 1);
286 OUT_RING (chan, 0x3f);
287
288 BEGIN_RING(chan, RING_3D_(0x16a8), 1);
289 OUT_RING (chan, (3 << 16) | 3);
290 BEGIN_RING(chan, RING_3D_(0x1794), 1);
291 OUT_RING (chan, (2 << 16) | 2);
292 BEGIN_RING(chan, RING_3D_(0x0de8), 1);
293 OUT_RING (chan, 1);
294
295 #if 0 /* software method */
296 BEGIN_RING(chan, RING_3D_(0x1528), 1); /* MP poke */
297 OUT_RING (chan, 0);
298 #endif
299
300 BEGIN_RING(chan, RING_3D_(0x12ac), 1);
301 OUT_RING (chan, 0);
302 BEGIN_RING(chan, RING_3D_(0x0218), 1);
303 OUT_RING (chan, 0x10);
304 BEGIN_RING(chan, RING_3D_(0x10fc), 1);
305 OUT_RING (chan, 0x10);
306 BEGIN_RING(chan, RING_3D_(0x1290), 1);
307 OUT_RING (chan, 0x10);
308 BEGIN_RING(chan, RING_3D_(0x12d8), 2);
309 OUT_RING (chan, 0x10);
310 OUT_RING (chan, 0x10);
311 BEGIN_RING(chan, RING_3D_(0x06d4), 1);
312 OUT_RING (chan, 8);
313 BEGIN_RING(chan, RING_3D_(0x1140), 1);
314 OUT_RING (chan, 0x10);
315 BEGIN_RING(chan, RING_3D_(0x1610), 1);
316 OUT_RING (chan, 0xe);
317
318 BEGIN_RING(chan, RING_3D_(0x164c), 1);
319 OUT_RING (chan, 1 << 12);
320 BEGIN_RING(chan, RING_3D_(0x151c), 1);
321 OUT_RING (chan, 1);
322 BEGIN_RING(chan, RING_3D_(0x030c), 1);
323 OUT_RING (chan, 0);
324 BEGIN_RING(chan, RING_3D_(0x0300), 1);
325 OUT_RING (chan, 3);
326 #if 0 /* software method */
327 BEGIN_RING(chan, RING_3D_(0x1280), 1); /* PGRAPH poke */
328 OUT_RING (chan, 0);
329 #endif
330 BEGIN_RING(chan, RING_3D_(0x02d0), 1);
331 OUT_RING (chan, 0x1f40);
332 BEGIN_RING(chan, RING_3D_(0x00fdc), 1);
333 OUT_RING (chan, 1);
334 BEGIN_RING(chan, RING_3D_(0x19c0), 1);
335 OUT_RING (chan, 1);
336 BEGIN_RING(chan, RING_3D_(0x075c), 1);
337 OUT_RING (chan, 3);
338 }
339
340 static void
341 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
342 {
343 struct nvc0_screen *screen = nvc0_screen(pscreen);
344 struct nouveau_channel *chan = screen->base.channel;
345
346 MARK_RING (chan, 5, 2);
347
348 /* we need to do it after possible flush in MARK_RING */
349 *sequence = ++screen->base.fence.sequence;
350
351 BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
352 OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
353 OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
354 OUT_RING (chan, *sequence);
355 OUT_RING (chan, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
356 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
357 }
358
359 static u32
360 nvc0_screen_fence_update(struct pipe_screen *pscreen)
361 {
362 struct nvc0_screen *screen = nvc0_screen(pscreen);
363 return screen->fence.map[0];
364 }
365
366 #define FAIL_SCREEN_INIT(str, err) \
367 do { \
368 NOUVEAU_ERR(str, err); \
369 nvc0_screen_destroy(pscreen); \
370 return NULL; \
371 } while(0)
372
373 struct pipe_screen *
374 nvc0_screen_create(struct nouveau_device *dev)
375 {
376 struct nvc0_screen *screen;
377 struct nouveau_channel *chan;
378 struct pipe_screen *pscreen;
379 int ret;
380 unsigned i;
381
382 screen = CALLOC_STRUCT(nvc0_screen);
383 if (!screen)
384 return NULL;
385 pscreen = &screen->base.base;
386
387 screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
388
389 ret = nouveau_screen_init(&screen->base, dev);
390 if (ret) {
391 nvc0_screen_destroy(pscreen);
392 return NULL;
393 }
394 chan = screen->base.channel;
395 chan->user_private = screen;
396
397 pscreen->destroy = nvc0_screen_destroy;
398 pscreen->context_create = nvc0_create;
399 pscreen->is_format_supported = nvc0_screen_is_format_supported;
400 pscreen->get_param = nvc0_screen_get_param;
401 pscreen->get_shader_param = nvc0_screen_get_shader_param;
402 pscreen->get_paramf = nvc0_screen_get_paramf;
403
404 nvc0_screen_init_resource_functions(pscreen);
405
406 nouveau_screen_init_vdec(&screen->base);
407
408 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
409 &screen->fence.bo);
410 if (ret)
411 goto fail;
412 nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
413 screen->fence.map = screen->fence.bo->map;
414 nouveau_bo_unmap(screen->fence.bo);
415 screen->base.fence.emit = nvc0_screen_fence_emit;
416 screen->base.fence.update = nvc0_screen_fence_update;
417
418 for (i = 0; i < NVC0_SCRATCH_NR_BUFFERS; ++i) {
419 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, NVC0_SCRATCH_SIZE,
420 &screen->scratch.bo[i]);
421 if (ret)
422 goto fail;
423 }
424
425 ret = nouveau_grobj_alloc(chan, 0xbeef9039, NVC0_M2MF, &screen->m2mf);
426 if (ret)
427 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
428
429 BIND_RING (chan, screen->m2mf, NVC0_SUBCH_MF);
430 BEGIN_RING(chan, RING_MF(NOTIFY_ADDRESS_HIGH), 3);
431 OUT_RELOCh(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
432 OUT_RELOCl(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
433 OUT_RING (chan, 0);
434
435 ret = nouveau_grobj_alloc(chan, 0xbeef902d, NVC0_2D, &screen->eng2d);
436 if (ret)
437 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
438
439 BIND_RING (chan, screen->eng2d, NVC0_SUBCH_2D);
440 BEGIN_RING(chan, RING_2D(OPERATION), 1);
441 OUT_RING (chan, NVC0_2D_OPERATION_SRCCOPY);
442 BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
443 OUT_RING (chan, 0);
444 BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
445 OUT_RING (chan, 0);
446 BEGIN_RING(chan, RING_2D_(0x0884), 1);
447 OUT_RING (chan, 0x3f);
448 BEGIN_RING(chan, RING_2D_(0x0888), 1);
449 OUT_RING (chan, 1);
450
451 ret = nouveau_grobj_alloc(chan, 0xbeef9097, NVC0_3D, &screen->fermi);
452 if (ret)
453 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
454
455 BIND_RING (chan, screen->fermi, NVC0_SUBCH_3D);
456 BEGIN_RING(chan, RING_3D(NOTIFY_ADDRESS_HIGH), 3);
457 OUT_RELOCh(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
458 OUT_RELOCl(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
459 OUT_RING (chan, 0);
460
461 BEGIN_RING(chan, RING_3D(COND_MODE), 1);
462 OUT_RING (chan, NVC0_3D_COND_MODE_ALWAYS);
463
464 BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
465 OUT_RING (chan, 1);
466
467 BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
468 OUT_RING (chan, 0);
469 BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
470 OUT_RING (chan, 0);
471 BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
472 OUT_RING (chan, NVC0_3D_MULTISAMPLE_MODE_MS1);
473 BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
474 OUT_RING (chan, 0);
475 BEGIN_RING(chan, RING_3D(LINE_WIDTH_SEPARATE), 1);
476 OUT_RING (chan, 1);
477 BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
478 OUT_RING (chan, 0);
479 BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
480 OUT_RING (chan, 1);
481 BEGIN_RING(chan, RING_3D(BLEND_ENABLE_COMMON), 1);
482 OUT_RING (chan, 0);
483 BEGIN_RING(chan, RING_3D(TEX_MISC), 1);
484 OUT_RING (chan, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
485
486 nvc0_magic_3d_init(chan);
487
488 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, &screen->text);
489 if (ret)
490 goto fail;
491
492 /* XXX: getting a page fault at the end of the code buffer every few
493 * launches, don't use the last 256 bytes to work around them - prefetch ?
494 */
495 nouveau_resource_init(&screen->text_heap, 0, (1 << 20) - 0x100);
496
497 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16,
498 &screen->uniforms);
499 if (ret)
500 goto fail;
501
502 /* auxiliary constants (6 user clip planes, base instance id) */
503 BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
504 OUT_RING (chan, 256);
505 OUT_RELOCh(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
506 OUT_RELOCl(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
507 for (i = 0; i < 5; ++i) {
508 BEGIN_RING(chan, RING_3D(CB_BIND(i)), 1);
509 OUT_RING (chan, (15 << 4) | 1);
510 }
511
512 screen->tls_size = (16 * 32) * (NVC0_CAP_MAX_PROGRAM_TEMPS * 16);
513 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
514 screen->tls_size, &screen->tls);
515 if (ret)
516 goto fail;
517
518 BEGIN_RING(chan, RING_3D(CODE_ADDRESS_HIGH), 2);
519 OUT_RELOCh(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
520 OUT_RELOCl(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
521 BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 4);
522 OUT_RELOCh(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
523 OUT_RELOCl(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
524 OUT_RING (chan, screen->tls_size >> 32);
525 OUT_RING (chan, screen->tls_size);
526 BEGIN_RING(chan, RING_3D_(0x07a0), 1);
527 OUT_RING (chan, 0);
528 BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
529 OUT_RING (chan, 0);
530
531 for (i = 0; i < 5; ++i) {
532 BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
533 OUT_RING (chan, 0x54);
534 }
535 BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
536 OUT_RING (chan, 0);
537
538 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20,
539 &screen->vfetch_cache);
540 if (ret)
541 goto fail;
542
543 BEGIN_RING(chan, RING_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
544 OUT_RELOCh(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
545 OUT_RELOCl(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
546 OUT_RING (chan, 3);
547
548 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, &screen->txc);
549 if (ret)
550 goto fail;
551
552 BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
553 OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
554 OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
555 OUT_RING (chan, NVC0_TIC_MAX_ENTRIES - 1);
556
557 BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
558 OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
559 OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
560 OUT_RING (chan, NVC0_TSC_MAX_ENTRIES - 1);
561
562 BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
563 OUT_RING (chan, 0);
564 BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
565 OUT_RING (chan, 0);
566 OUT_RING (chan, 0);
567 BEGIN_RING(chan, RING_3D_(0x1590), 1); /* deactivate ZCULL */
568 OUT_RING (chan, 0x3f);
569
570 BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
571 OUT_RING (chan, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
572 BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
573 for (i = 0; i < 8 * 2; ++i)
574 OUT_RING(chan, 0);
575 BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
576 OUT_RING (chan, 0);
577 BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
578 OUT_RING (chan, 0);
579
580 /* neither scissors, viewport nor stencil mask should affect clears */
581 BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
582 OUT_RING (chan, 0);
583
584 BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
585 OUT_RING (chan, 1);
586 BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
587 OUT_RINGf (chan, 0.0f);
588 OUT_RINGf (chan, 1.0f);
589 BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
590 OUT_RING (chan, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
591
592 /* We use scissors instead of exact view volume clipping,
593 * so they're always enabled.
594 */
595 BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
596 OUT_RING (chan, 1);
597 OUT_RING (chan, 8192 << 16);
598 OUT_RING (chan, 8192 << 16);
599
600 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
601
602 i = 0;
603 MK_MACRO(NVC0_3D_BLEND_ENABLES, nvc0_9097_blend_enables);
604 MK_MACRO(NVC0_3D_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
605 MK_MACRO(NVC0_3D_TEP_SELECT, nvc0_9097_tep_select);
606 MK_MACRO(NVC0_3D_GP_SELECT, nvc0_9097_gp_select);
607 MK_MACRO(NVC0_3D_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
608 MK_MACRO(NVC0_3D_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
609
610 BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
611 OUT_RING (chan, 1);
612 BEGIN_RING(chan, RING_3D(RT_SEPARATE_FRAG_DATA), 1);
613 OUT_RING (chan, 1);
614 BEGIN_RING(chan, RING_3D(GP_SELECT), 1);
615 OUT_RING (chan, 0x40);
616 BEGIN_RING(chan, RING_3D(LAYER), 1);
617 OUT_RING (chan, 0);
618 BEGIN_RING(chan, RING_3D(TEP_SELECT), 1);
619 OUT_RING (chan, 0x30);
620 BEGIN_RING(chan, RING_3D(PATCH_VERTICES), 1);
621 OUT_RING (chan, 3);
622 BEGIN_RING(chan, RING_3D(SP_SELECT(2)), 1);
623 OUT_RING (chan, 0x20);
624 BEGIN_RING(chan, RING_3D(SP_SELECT(0)), 1);
625 OUT_RING (chan, 0x00);
626
627 BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
628 OUT_RING (chan, 0);
629 BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
630 OUT_RING (chan, NVC0_3D_POINT_RASTER_RULES_OGL);
631
632 BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
633 OUT_RING (chan, 1);
634
635 BEGIN_RING(chan, RING_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
636 OUT_RING (chan, 0xab);
637 OUT_RING (chan, 0x00000000);
638
639 FIRE_RING (chan);
640
641 screen->tic.entries = CALLOC(4096, sizeof(void *));
642 screen->tsc.entries = screen->tic.entries + 2048;
643
644 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
645
646 if (!nvc0_blitctx_create(screen))
647 goto fail;
648
649 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
650
651 return pscreen;
652
653 fail:
654 nvc0_screen_destroy(pscreen);
655 return NULL;
656 }
657
658 void
659 nvc0_screen_make_buffers_resident(struct nvc0_screen *screen)
660 {
661 struct nouveau_channel *chan = screen->base.channel;
662
663 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
664
665 MARK_RING(chan, 0, 5);
666 nouveau_bo_validate(chan, screen->text, flags);
667 nouveau_bo_validate(chan, screen->uniforms, flags);
668 nouveau_bo_validate(chan, screen->txc, flags);
669 nouveau_bo_validate(chan, screen->vfetch_cache, flags);
670
671 if (screen->cur_ctx && screen->cur_ctx->state.tls_required)
672 nouveau_bo_validate(chan, screen->tls, flags);
673 }
674
675 int
676 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
677 {
678 int i = screen->tic.next;
679
680 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
681 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
682
683 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
684
685 if (screen->tic.entries[i])
686 nv50_tic_entry(screen->tic.entries[i])->id = -1;
687
688 screen->tic.entries[i] = entry;
689 return i;
690 }
691
692 int
693 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
694 {
695 int i = screen->tsc.next;
696
697 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
698 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
699
700 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
701
702 if (screen->tsc.entries[i])
703 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
704
705 screen->tsc.entries[i] = entry;
706 return i;
707 }