src/gallium/drivers/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nvc0_context.h"
  31 #include "nvc0_screen.h"
  32
  33 #include "nvc0_graph_macros.h"
  34
  35 static boolean
  36 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  37                                 enum pipe_format format,
  38                                 enum pipe_texture_target target,
  39                                 unsigned sample_count,
  40                                 unsigned bindings)
  41 {
  42    if (sample_count > 8)
  43       return FALSE;
  44    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  45       return FALSE;
  46
  47    if (!util_format_is_supported(format, bindings))
  48       return FALSE;
  49
  50    switch (format) {
  51    case PIPE_FORMAT_R8G8B8A8_UNORM:
  52    case PIPE_FORMAT_R8G8B8X8_UNORM:
  53       /* HACK: GL requires equal formats for MS resolve and window is BGRA */
  54       if (bindings & PIPE_BIND_RENDER_TARGET)
  55          return FALSE;
  56    default:
  57       break;
  58    }
  59
  60    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  61       if (util_format_get_blocksizebits(format) == 3 * 32)
  62          return FALSE;
  63
  64    /* transfers & shared are always supported */
  65    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  66                  PIPE_BIND_TRANSFER_WRITE |
  67                  PIPE_BIND_SHARED);
  68
  69    return (nvc0_format_table[format].usage & bindings) == bindings;
  70 }
  71
  72 static boolean
  73 nvc0_screen_video_supported(struct pipe_screen *screen,
  74                             enum pipe_format format,
  75                             enum pipe_video_profile profile)
  76 {
  77    if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
  78       return format == PIPE_FORMAT_NV12;
  79
  80    return vl_video_buffer_is_format_supported(screen, format, profile);
  81 }
  82
  83
  84 static int
  85 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  86 {
  87    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  88
  89    switch (param) {
  90    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  91       return 16 * PIPE_SHADER_TYPES; /* NOTE: should not count COMPUTE */
  92    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  93    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  94       return 15;
  95    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  96       return 12;
  97    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  98       return 2048;
  99    case PIPE_CAP_MIN_TEXEL_OFFSET:
 100       return -8;
 101    case PIPE_CAP_MAX_TEXEL_OFFSET:
 102       return 7;
 103    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 104    case PIPE_CAP_TEXTURE_SWIZZLE:
 105    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 106    case PIPE_CAP_NPOT_TEXTURES:
 107    case PIPE_CAP_ANISOTROPIC_FILTER:
 108    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 109    case PIPE_CAP_CUBE_MAP_ARRAY:
 110    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 111       return 1;
 112    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 113       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 114    case PIPE_CAP_TWO_SIDED_STENCIL:
 115    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 116    case PIPE_CAP_POINT_SPRITE:
 117       return 1;
 118    case PIPE_CAP_SM3:
 119       return 1;
 120    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 121       return 150;
 122    case PIPE_CAP_MAX_RENDER_TARGETS:
 123       return 8;
 124    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 125       return 1;
 126    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 127    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 128    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 129       return 1;
 130    case PIPE_CAP_QUERY_TIMESTAMP:
 131    case PIPE_CAP_QUERY_TIME_ELAPSED:
 132    case PIPE_CAP_OCCLUSION_QUERY:
 133    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 134       return 1;
 135    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 136       return 4;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 138    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 139       return 128;
 140    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 141    case PIPE_CAP_INDEP_BLEND_ENABLE:
 142    case PIPE_CAP_INDEP_BLEND_FUNC:
 143       return 1;
 144    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 145    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 146       return 1;
 147    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 148    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 149       return 0;
 150    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 151       return 0;
 152    case PIPE_CAP_PRIMITIVE_RESTART:
 153    case PIPE_CAP_TGSI_INSTANCEID:
 154    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 155    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 156    case PIPE_CAP_CONDITIONAL_RENDER:
 157    case PIPE_CAP_TEXTURE_BARRIER:
 158    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 159    case PIPE_CAP_START_INSTANCE:
 160       return 1;
 161    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 162    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 163       return 0; /* state trackers will know better */
 164    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 165    case PIPE_CAP_USER_INDEX_BUFFERS:
 166    case PIPE_CAP_USER_VERTEX_BUFFERS:
 167       return 1;
 168    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 169       return 256;
 170    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 171       return 1; /* 256 for binding as RT, but that's not possible in GL */
 172    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 173       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 174    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 175    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 176    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 177    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 178       return 0;
 179    default:
 180       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 181       return 0;
 182    }
 183 }
 184
 185 static int
 186 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 187                              enum pipe_shader_cap param)
 188 {
 189    switch (shader) {
 190    case PIPE_SHADER_VERTEX:
 191       /*
 192    case PIPE_SHADER_TESSELLATION_CONTROL:
 193    case PIPE_SHADER_TESSELLATION_EVALUATION:
 194       */
 195    case PIPE_SHADER_GEOMETRY:
 196    case PIPE_SHADER_FRAGMENT:
 197       break;
 198    default:
 199       return 0;
 200    }
 201
 202    switch (param) {
 203    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 204    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 205    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 206    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 207       return 16384;
 208    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 209       return 16;
 210    case PIPE_SHADER_CAP_MAX_INPUTS:
 211       if (shader == PIPE_SHADER_VERTEX)
 212          return 32;
 213       if (shader == PIPE_SHADER_FRAGMENT)
 214          return (0x200 + 0x20 + 0x80) / 16; /* generic + colors + TexCoords */
 215       return (0x200 + 0x40 + 0x80) / 16; /* without 0x60 for per-patch inputs */
 216    case PIPE_SHADER_CAP_MAX_CONSTS:
 217       return 65536 / 16;
 218    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 219       return NVC0_MAX_PIPE_CONSTBUFS;
 220    case PIPE_SHADER_CAP_MAX_ADDRS:
 221       return 1;
 222    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 223    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 224       return shader != PIPE_SHADER_FRAGMENT;
 225    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 226    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 227       return 1;
 228    case PIPE_SHADER_CAP_MAX_PREDS:
 229       return 0;
 230    case PIPE_SHADER_CAP_MAX_TEMPS:
 231       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 232    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 233       return 1;
 234    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 235       return 0;
 236    case PIPE_SHADER_CAP_SUBROUTINES:
 237       return 1; /* but inlining everything, we need function declarations */
 238    case PIPE_SHADER_CAP_INTEGERS:
 239       return 1;
 240    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 241       return 16; /* would be 32 in linked (OpenGL-style) mode */
 242       /*
 243    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
 244       return 32;
 245       */
 246    default:
 247       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 248       return 0;
 249    }
 250 }
 251
 252 static float
 253 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 254 {
 255    switch (param) {
 256    case PIPE_CAPF_MAX_LINE_WIDTH:
 257    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 258       return 10.0f;
 259    case PIPE_CAPF_MAX_POINT_WIDTH:
 260       return 63.0f;
 261    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 262       return 63.375f;
 263    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 264       return 16.0f;
 265    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 266       return 15.0f;
 267    default:
 268       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 269       return 0.0f;
 270    }
 271 }
 272
 273 static void
 274 nvc0_screen_destroy(struct pipe_screen *pscreen)
 275 {
 276    struct nvc0_screen *screen = nvc0_screen(pscreen);
 277
 278    if (screen->base.fence.current) {
 279       nouveau_fence_wait(screen->base.fence.current);
 280       nouveau_fence_ref(NULL, &screen->base.fence.current);
 281    }
 282    if (screen->base.pushbuf)
 283       screen->base.pushbuf->user_priv = NULL;
 284
 285    if (screen->blitter)
 286       nvc0_blitter_destroy(screen);
 287
 288    nouveau_bo_ref(NULL, &screen->text);
 289    nouveau_bo_ref(NULL, &screen->uniform_bo);
 290    nouveau_bo_ref(NULL, &screen->tls);
 291    nouveau_bo_ref(NULL, &screen->txc);
 292    nouveau_bo_ref(NULL, &screen->fence.bo);
 293    nouveau_bo_ref(NULL, &screen->poly_cache);
 294
 295    nouveau_heap_destroy(&screen->lib_code);
 296    nouveau_heap_destroy(&screen->text_heap);
 297
 298    FREE(screen->tic.entries);
 299
 300    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 301
 302    nouveau_object_del(&screen->eng3d);
 303    nouveau_object_del(&screen->eng2d);
 304    nouveau_object_del(&screen->m2mf);
 305
 306    nouveau_screen_fini(&screen->base);
 307
 308    FREE(screen);
 309 }
 310
 311 static int
 312 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 313                      unsigned size, const uint32_t *data)
 314 {
 315    struct nouveau_pushbuf *push = screen->base.pushbuf;
 316
 317    size /= 4;
 318
 319    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 320    PUSH_DATA (push, (m - 0x3800) / 8);
 321    PUSH_DATA (push, pos);
 322    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 323    PUSH_DATA (push, pos);
 324    PUSH_DATAp(push, data, size);
 325
 326    return pos + size;
 327 }
 328
 329 static void
 330 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 331 {
 332    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 333    PUSH_DATA (push, 0xff);
 334    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 335    PUSH_DATA (push, 0xff);
 336    PUSH_DATA (push, 0xff);
 337    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 338    PUSH_DATA (push, 0xff);
 339    PUSH_DATA (push, 0xff);
 340    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 341    PUSH_DATA (push, 0x3f);
 342
 343    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 344    PUSH_DATA (push, (3 << 16) | 3);
 345    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 346    PUSH_DATA (push, (2 << 16) | 2);
 347    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
 348    PUSH_DATA (push, 1);
 349
 350    BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 351    PUSH_DATA (push, 0);
 352    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 353    PUSH_DATA (push, 0x10);
 354    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 355    PUSH_DATA (push, 0x10);
 356    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 357    PUSH_DATA (push, 0x10);
 358    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 359    PUSH_DATA (push, 0x10);
 360    PUSH_DATA (push, 0x10);
 361    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 362    PUSH_DATA (push, 0x10);
 363    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 364    PUSH_DATA (push, 0xe);
 365
 366    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 367    PUSH_DATA (push, 1 << 12);
 368    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 369    PUSH_DATA (push, 0);
 370    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 371    PUSH_DATA (push, 3);
 372
 373    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 374    PUSH_DATA (push, 0x3fffff);
 375    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 376    PUSH_DATA (push, 1);
 377    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 378    PUSH_DATA (push, 1);
 379    BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 380    PUSH_DATA (push, 3);
 381
 382    if (obj_class >= NVE4_3D_CLASS) {
 383       BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 384       PUSH_DATA (push, 1);
 385    }
 386
 387    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 388     * are supposed to do */
 389 }
 390
 391 static void
 392 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 393 {
 394    struct nvc0_screen *screen = nvc0_screen(pscreen);
 395    struct nouveau_pushbuf *push = screen->base.pushbuf;
 396
 397    /* we need to do it after possible flush in MARK_RING */
 398    *sequence = ++screen->base.fence.sequence;
 399
 400    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 401    PUSH_DATAh(push, screen->fence.bo->offset);
 402    PUSH_DATA (push, screen->fence.bo->offset);
 403    PUSH_DATA (push, *sequence);
 404    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 405               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 406 }
 407
 408 static u32
 409 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 410 {
 411    struct nvc0_screen *screen = nvc0_screen(pscreen);
 412    return screen->fence.map[0];
 413 }
 414
 415 #define FAIL_SCREEN_INIT(str, err)                    \
 416    do {                                               \
 417       NOUVEAU_ERR(str, err);                          \
 418       nvc0_screen_destroy(pscreen);                   \
 419       return NULL;                                    \
 420    } while(0)
 421
 422 struct pipe_screen *
 423 nvc0_screen_create(struct nouveau_device *dev)
 424 {
 425    struct nvc0_screen *screen;
 426    struct pipe_screen *pscreen;
 427    struct nouveau_object *chan;
 428    struct nouveau_pushbuf *push;
 429    uint32_t obj_class;
 430    int ret;
 431    unsigned i;
 432    union nouveau_bo_config mm_config;
 433
 434    switch (dev->chipset & ~0xf) {
 435    case 0xc0:
 436    case 0xd0:
 437    case 0xe0:
 438       break;
 439    default:
 440       return NULL;
 441    }
 442
 443    screen = CALLOC_STRUCT(nvc0_screen);
 444    if (!screen)
 445       return NULL;
 446    pscreen = &screen->base.base;
 447
 448    ret = nouveau_screen_init(&screen->base, dev);
 449    if (ret) {
 450       nvc0_screen_destroy(pscreen);
 451       return NULL;
 452    }
 453    chan = screen->base.channel;
 454    push = screen->base.pushbuf;
 455    push->user_priv = screen;
 456
 457    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 458       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 459    screen->base.sysmem_bindings |=
 460       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 461
 462    pscreen->destroy = nvc0_screen_destroy;
 463    pscreen->context_create = nvc0_create;
 464    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 465    pscreen->get_param = nvc0_screen_get_param;
 466    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 467    pscreen->get_paramf = nvc0_screen_get_paramf;
 468
 469    nvc0_screen_init_resource_functions(pscreen);
 470
 471    screen->base.base.get_video_param = nvc0_screen_get_video_param;
 472    screen->base.base.is_video_format_supported = nvc0_screen_video_supported;
 473
 474    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 475                         &screen->fence.bo);
 476    if (ret)
 477       goto fail;
 478    nouveau_bo_map(screen->fence.bo, 0, NULL);
 479    screen->fence.map = screen->fence.bo->map;
 480    screen->base.fence.emit = nvc0_screen_fence_emit;
 481    screen->base.fence.update = nvc0_screen_fence_update;
 482
 483    switch (dev->chipset & 0xf0) {
 484    case 0xe0:
 485       obj_class = NVE4_P2MF_CLASS;
 486       break;
 487    default:
 488       obj_class = NVC0_M2MF_CLASS;
 489       break;
 490    }
 491    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 492                             &screen->m2mf);
 493    if (ret)
 494       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 495
 496    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 497    PUSH_DATA (push, screen->m2mf->oclass);
 498    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 499       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 500       PUSH_DATA (push, 0xa0b5);
 501    }
 502
 503    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 504                             &screen->eng2d);
 505    if (ret)
 506       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 507
 508    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 509    PUSH_DATA (push, screen->eng2d->oclass);
 510    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 511    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 512    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 513    PUSH_DATA (push, 0);
 514    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 515    PUSH_DATA (push, 0);
 516    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 517    PUSH_DATA (push, 0x3f);
 518    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 519    PUSH_DATA (push, 1);
 520
 521    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 522    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 523    PUSH_DATA (push, screen->fence.bo->offset + 16);
 524
 525    switch (dev->chipset & 0xf0) {
 526    case 0xe0:
 527       obj_class = NVE4_3D_CLASS;
 528       break;
 529    case 0xd0:
 530    case 0xc0:
 531    default:
 532       switch (dev->chipset) {
 533       case 0xd9:
 534       case 0xc8:
 535          obj_class = NVC8_3D_CLASS;
 536          break;
 537       case 0xc1:
 538          obj_class = NVC1_3D_CLASS;
 539          break;
 540       default:
 541          obj_class = NVC0_3D_CLASS;
 542          break;
 543       }
 544       break;
 545    }
 546    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 547                             &screen->eng3d);
 548    if (ret)
 549       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 550    screen->base.class_3d = obj_class;
 551
 552    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 553    PUSH_DATA (push, screen->eng3d->oclass);
 554
 555    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 556    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 557
 558    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 559       /* kill shaders after about 1 second (at 100 MHz) */
 560       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 561       PUSH_DATA (push, 0x17);
 562    }
 563
 564    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 565    PUSH_DATA (push, 1);
 566
 567    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 568    PUSH_DATA (push, 0);
 569    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 570    PUSH_DATA (push, 0);
 571    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 572    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 573    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 574    PUSH_DATA (push, 0);
 575    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 576    PUSH_DATA (push, 1);
 577    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 578    PUSH_DATA (push, 0);
 579    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 580    PUSH_DATA (push, 1);
 581    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 582    PUSH_DATA (push, 0);
 583    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 584       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 585       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 586    } else {
 587       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 588       PUSH_DATA (push, 15);
 589    }
 590    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 591    PUSH_DATA (push, 8); /* 128 */
 592    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 593    PUSH_DATA (push, 1);
 594    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 595       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 596       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 597    }
 598
 599    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 600
 601    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 602                         &screen->text);
 603    if (ret)
 604       goto fail;
 605
 606    /* XXX: getting a page fault at the end of the code buffer every few
 607     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 608     */
 609    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 610
 611    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 612                         &screen->uniform_bo);
 613    if (ret)
 614       goto fail;
 615
 616    for (i = 0; i < 5; ++i) {
 617       /* TIC and TSC entries for each unit (nve4+ only) */
 618       /* auxiliary constants (6 user clip planes, base instance id) */
 619       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 620       PUSH_DATA (push, 512);
 621       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 622       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 623       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 624       PUSH_DATA (push, (15 << 4) | 1);
 625       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 626          unsigned j;
 627          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 628          PUSH_DATA (push, 0);
 629          for (j = 0; j < 8; ++j)
 630             PUSH_DATA(push, j);
 631       } else {
 632          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 633          PUSH_DATA (push, 0x54);
 634       }
 635    }
 636    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 637    PUSH_DATA (push, 0);
 638
 639    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 640    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 641    PUSH_DATA (push, 256);
 642    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 643    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 644    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 645    PUSH_DATA (push, 0);
 646    PUSH_DATAf(push, 0.0f);
 647    PUSH_DATAf(push, 0.0f);
 648    PUSH_DATAf(push, 0.0f);
 649    PUSH_DATAf(push, 0.0f);
 650    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 651    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 652    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 653
 654    /* max MPs * max warps per MP (TODO: ask kernel) */
 655    if (screen->eng3d->oclass >= NVE4_3D_CLASS)
 656       screen->tls_size = 8 * 64;
 657    else
 658       screen->tls_size = 16 * 48;
 659    screen->tls_size *= NVC0_CAP_MAX_PROGRAM_TEMPS * 16;
 660    screen->tls_size = align(screen->tls_size, 1 << 17);
 661
 662    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
 663                         screen->tls_size, NULL, &screen->tls);
 664    if (ret)
 665       goto fail;
 666
 667    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 668    PUSH_DATAh(push, screen->text->offset);
 669    PUSH_DATA (push, screen->text->offset);
 670    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 671    PUSH_DATAh(push, screen->tls->offset);
 672    PUSH_DATA (push, screen->tls->offset);
 673    PUSH_DATA (push, screen->tls_size >> 32);
 674    PUSH_DATA (push, screen->tls_size);
 675    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 676    PUSH_DATA (push, 0);
 677    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 678    PUSH_DATA (push, 0);
 679
 680    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 681                         &screen->poly_cache);
 682    if (ret)
 683       goto fail;
 684
 685    BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 686    PUSH_DATAh(push, screen->poly_cache->offset);
 687    PUSH_DATA (push, screen->poly_cache->offset);
 688    PUSH_DATA (push, 3);
 689
 690    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 691                         &screen->txc);
 692    if (ret)
 693       goto fail;
 694
 695    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 696    PUSH_DATAh(push, screen->txc->offset);
 697    PUSH_DATA (push, screen->txc->offset);
 698    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 699
 700    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 701    PUSH_DATAh(push, screen->txc->offset + 65536);
 702    PUSH_DATA (push, screen->txc->offset + 65536);
 703    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 704
 705    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 706    PUSH_DATA (push, 0);
 707    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 708    PUSH_DATA (push, 0);
 709    PUSH_DATA (push, 0);
 710    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 711    PUSH_DATA (push, 0x3f);
 712
 713    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 714    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 715    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 716    for (i = 0; i < 8 * 2; ++i)
 717       PUSH_DATA(push, 0);
 718    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 719    PUSH_DATA (push, 0);
 720    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 721    PUSH_DATA (push, 0);
 722
 723    /* neither scissors, viewport nor stencil mask should affect clears */
 724    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 725    PUSH_DATA (push, 0);
 726
 727    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 728    PUSH_DATA (push, 1);
 729    BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
 730    PUSH_DATAf(push, 0.0f);
 731    PUSH_DATAf(push, 1.0f);
 732    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 733    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 734
 735    /* We use scissors instead of exact view volume clipping,
 736     * so they're always enabled.
 737     */
 738    BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
 739    PUSH_DATA (push, 1);
 740    PUSH_DATA (push, 8192 << 16);
 741    PUSH_DATA (push, 8192 << 16);
 742
 743 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 744
 745    i = 0;
 746    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
 747    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
 748    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 749    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
 750    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
 751    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 752    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 753
 754    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 755    PUSH_DATA (push, 1);
 756    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 757    PUSH_DATA (push, 1);
 758    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 759    PUSH_DATA (push, 0x40);
 760    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 761    PUSH_DATA (push, 0);
 762    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 763    PUSH_DATA (push, 0x30);
 764    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 765    PUSH_DATA (push, 3);
 766    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 767    PUSH_DATA (push, 0x20);
 768    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 769    PUSH_DATA (push, 0x00);
 770
 771    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 772    PUSH_DATA (push, 0);
 773    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 774    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 775
 776    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 777
 778    PUSH_KICK (push);
 779
 780    screen->tic.entries = CALLOC(4096, sizeof(void *));
 781    screen->tsc.entries = screen->tic.entries + 2048;
 782
 783    mm_config.nvc0.tile_mode = 0;
 784    mm_config.nvc0.memtype = 0xfe0;
 785    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
 786
 787    if (!nvc0_blitter_create(screen))
 788       goto fail;
 789
 790    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 791
 792    return pscreen;
 793
 794 fail:
 795    nvc0_screen_destroy(pscreen);
 796    return NULL;
 797 }
 798
 799 int
 800 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 801 {
 802    int i = screen->tic.next;
 803
 804    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 805       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 806
 807    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 808
 809    if (screen->tic.entries[i])
 810       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 811
 812    screen->tic.entries[i] = entry;
 813    return i;
 814 }
 815
 816 int
 817 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 818 {
 819    int i = screen->tsc.next;
 820
 821    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 822       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 823
 824    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 825
 826    if (screen->tsc.entries[i])
 827       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 828
 829    screen->tsc.entries[i] = entry;
 830    return i;
 831 }