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gallium: Add PIPE_CAP_ENDIANNESS
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "nvc0_context.h"
31 #include "nvc0_screen.h"
32
33 #include "nvc0_graph_macros.h"
34
35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
37 #endif
38
39 static boolean
40 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
41 enum pipe_format format,
42 enum pipe_texture_target target,
43 unsigned sample_count,
44 unsigned bindings)
45 {
46 if (sample_count > 8)
47 return FALSE;
48 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
49 return FALSE;
50
51 if (!util_format_is_supported(format, bindings))
52 return FALSE;
53
54 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
55 if (util_format_get_blocksizebits(format) == 3 * 32)
56 return FALSE;
57
58 /* transfers & shared are always supported */
59 bindings &= ~(PIPE_BIND_TRANSFER_READ |
60 PIPE_BIND_TRANSFER_WRITE |
61 PIPE_BIND_SHARED);
62
63 return (nvc0_format_table[format].usage & bindings) == bindings;
64 }
65
66 static boolean
67 nvc0_screen_video_supported(struct pipe_screen *screen,
68 enum pipe_format format,
69 enum pipe_video_profile profile)
70 {
71 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
72 return format == PIPE_FORMAT_NV12;
73
74 return vl_video_buffer_is_format_supported(screen, format, profile);
75 }
76
77
78 static int
79 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
80 {
81 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
82
83 switch (param) {
84 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
85 return 16 * 5;
86 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
87 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
88 return 15;
89 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
90 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
91 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
92 return 2048;
93 case PIPE_CAP_MIN_TEXEL_OFFSET:
94 return -8;
95 case PIPE_CAP_MAX_TEXEL_OFFSET:
96 return 7;
97 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
98 case PIPE_CAP_TEXTURE_SWIZZLE:
99 case PIPE_CAP_TEXTURE_SHADOW_MAP:
100 case PIPE_CAP_NPOT_TEXTURES:
101 case PIPE_CAP_ANISOTROPIC_FILTER:
102 case PIPE_CAP_SEAMLESS_CUBE_MAP:
103 case PIPE_CAP_CUBE_MAP_ARRAY:
104 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
105 case PIPE_CAP_TEXTURE_MULTISAMPLE:
106 return 1;
107 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
108 return 65536;
109 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
110 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
111 case PIPE_CAP_TWO_SIDED_STENCIL:
112 case PIPE_CAP_DEPTH_CLIP_DISABLE:
113 case PIPE_CAP_POINT_SPRITE:
114 case PIPE_CAP_TGSI_TEXCOORD:
115 return 1;
116 case PIPE_CAP_SM3:
117 return 1;
118 case PIPE_CAP_GLSL_FEATURE_LEVEL:
119 return 150;
120 case PIPE_CAP_MAX_RENDER_TARGETS:
121 return 8;
122 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
123 return 1;
124 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
125 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
126 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
127 return 1;
128 case PIPE_CAP_QUERY_TIMESTAMP:
129 case PIPE_CAP_QUERY_TIME_ELAPSED:
130 case PIPE_CAP_OCCLUSION_QUERY:
131 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
132 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
133 return 1;
134 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
135 return 4;
136 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
137 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
138 return 128;
139 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
140 case PIPE_CAP_INDEP_BLEND_ENABLE:
141 case PIPE_CAP_INDEP_BLEND_FUNC:
142 return 1;
143 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
144 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
145 return 1;
146 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
147 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
148 return 0;
149 case PIPE_CAP_SHADER_STENCIL_EXPORT:
150 return 0;
151 case PIPE_CAP_PRIMITIVE_RESTART:
152 case PIPE_CAP_TGSI_INSTANCEID:
153 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
154 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
155 case PIPE_CAP_CONDITIONAL_RENDER:
156 case PIPE_CAP_TEXTURE_BARRIER:
157 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
158 case PIPE_CAP_START_INSTANCE:
159 return 1;
160 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
161 return 0; /* state trackers will know better */
162 case PIPE_CAP_USER_CONSTANT_BUFFERS:
163 case PIPE_CAP_USER_INDEX_BUFFERS:
164 case PIPE_CAP_USER_VERTEX_BUFFERS:
165 return 1;
166 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
167 return 256;
168 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
169 return 1; /* 256 for binding as RT, but that's not possible in GL */
170 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
171 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
172 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
173 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
174 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
175 return 0;
176 case PIPE_CAP_COMPUTE:
177 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
178 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
179 return 1;
180 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
181 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
182 case PIPE_CAP_ENDIANNESS:
183 return PIPE_ENDIAN_LITTLE;
184 default:
185 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
186 return 0;
187 }
188 }
189
190 static int
191 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
192 enum pipe_shader_cap param)
193 {
194 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
195
196 switch (shader) {
197 case PIPE_SHADER_VERTEX:
198 /*
199 case PIPE_SHADER_TESSELLATION_CONTROL:
200 case PIPE_SHADER_TESSELLATION_EVALUATION:
201 */
202 case PIPE_SHADER_GEOMETRY:
203 case PIPE_SHADER_FRAGMENT:
204 break;
205 case PIPE_SHADER_COMPUTE:
206 if (class_3d < NVE4_3D_CLASS)
207 return 0;
208 break;
209 default:
210 return 0;
211 }
212
213 switch (param) {
214 case PIPE_SHADER_CAP_PREFERRED_IR:
215 return PIPE_SHADER_IR_TGSI;
216 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
217 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
218 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
219 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
220 return 16384;
221 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
222 return 16;
223 case PIPE_SHADER_CAP_MAX_INPUTS:
224 if (shader == PIPE_SHADER_VERTEX)
225 return 32;
226 /* NOTE: These only count our slots for GENERIC varyings.
227 * The address space may be larger, but the actual hard limit seems to be
228 * less than what the address space layout permits, so don't add TEXCOORD,
229 * COLOR, etc. here.
230 */
231 if (shader == PIPE_SHADER_FRAGMENT)
232 return 0x1f0 / 16;
233 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
234 * and excludes 0x60 per-patch inputs.
235 */
236 return 0x200 / 16;
237 case PIPE_SHADER_CAP_MAX_CONSTS:
238 return 65536 / 16;
239 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
240 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
241 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
242 return NVC0_MAX_PIPE_CONSTBUFS;
243 case PIPE_SHADER_CAP_MAX_ADDRS:
244 return 1;
245 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
246 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
247 return shader != PIPE_SHADER_FRAGMENT;
248 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
249 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
250 return 1;
251 case PIPE_SHADER_CAP_MAX_PREDS:
252 return 0;
253 case PIPE_SHADER_CAP_MAX_TEMPS:
254 return NVC0_CAP_MAX_PROGRAM_TEMPS;
255 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
256 return 1;
257 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
258 return 0;
259 case PIPE_SHADER_CAP_SUBROUTINES:
260 return 1;
261 case PIPE_SHADER_CAP_INTEGERS:
262 return 1;
263 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
264 return 16; /* would be 32 in linked (OpenGL-style) mode */
265 /*
266 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
267 return 32;
268 */
269 default:
270 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
271 return 0;
272 }
273 }
274
275 static float
276 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
277 {
278 switch (param) {
279 case PIPE_CAPF_MAX_LINE_WIDTH:
280 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
281 return 10.0f;
282 case PIPE_CAPF_MAX_POINT_WIDTH:
283 return 63.0f;
284 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
285 return 63.375f;
286 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
287 return 16.0f;
288 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
289 return 15.0f;
290 default:
291 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
292 return 0.0f;
293 }
294 }
295
296 static int
297 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
298 enum pipe_compute_cap param, void *data)
299 {
300 uint64_t *data64 = (uint64_t *)data;
301 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
302
303 switch (param) {
304 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
305 data64[0] = 3;
306 return 8;
307 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
308 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
309 data64[1] = 65535;
310 data64[2] = 65535;
311 return 24;
312 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
313 data64[0] = 1024;
314 data64[1] = 1024;
315 data64[2] = 64;
316 return 24;
317 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
318 data64[0] = 1024;
319 return 8;
320 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
321 data64[0] = (uint64_t)1 << 40;
322 return 8;
323 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
324 data64[0] = 48 << 10;
325 return 8;
326 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
327 data64[0] = 512 << 10;
328 return 8;
329 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
330 data64[0] = 4096;
331 return 8;
332 default:
333 return 0;
334 }
335 }
336
337 static void
338 nvc0_screen_destroy(struct pipe_screen *pscreen)
339 {
340 struct nvc0_screen *screen = nvc0_screen(pscreen);
341
342 if (screen->base.fence.current) {
343 nouveau_fence_wait(screen->base.fence.current);
344 nouveau_fence_ref(NULL, &screen->base.fence.current);
345 }
346 if (screen->base.pushbuf)
347 screen->base.pushbuf->user_priv = NULL;
348
349 if (screen->blitter)
350 nvc0_blitter_destroy(screen);
351 if (screen->pm.prog) {
352 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
353 nvc0_program_destroy(NULL, screen->pm.prog);
354 }
355
356 nouveau_bo_ref(NULL, &screen->text);
357 nouveau_bo_ref(NULL, &screen->uniform_bo);
358 nouveau_bo_ref(NULL, &screen->tls);
359 nouveau_bo_ref(NULL, &screen->txc);
360 nouveau_bo_ref(NULL, &screen->fence.bo);
361 nouveau_bo_ref(NULL, &screen->poly_cache);
362 nouveau_bo_ref(NULL, &screen->parm);
363
364 nouveau_heap_destroy(&screen->lib_code);
365 nouveau_heap_destroy(&screen->text_heap);
366
367 FREE(screen->tic.entries);
368
369 nouveau_mm_destroy(screen->mm_VRAM_fe0);
370
371 nouveau_object_del(&screen->eng3d);
372 nouveau_object_del(&screen->eng2d);
373 nouveau_object_del(&screen->m2mf);
374
375 nouveau_screen_fini(&screen->base);
376
377 FREE(screen);
378 }
379
380 static int
381 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
382 unsigned size, const uint32_t *data)
383 {
384 struct nouveau_pushbuf *push = screen->base.pushbuf;
385
386 size /= 4;
387
388 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
389 PUSH_DATA (push, (m - 0x3800) / 8);
390 PUSH_DATA (push, pos);
391 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
392 PUSH_DATA (push, pos);
393 PUSH_DATAp(push, data, size);
394
395 return pos + size;
396 }
397
398 static void
399 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
400 {
401 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
402 PUSH_DATA (push, 0xff);
403 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
404 PUSH_DATA (push, 0xff);
405 PUSH_DATA (push, 0xff);
406 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
407 PUSH_DATA (push, 0xff);
408 PUSH_DATA (push, 0xff);
409 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
410 PUSH_DATA (push, 0x3f);
411
412 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
413 PUSH_DATA (push, (3 << 16) | 3);
414 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
415 PUSH_DATA (push, (2 << 16) | 2);
416 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
417 PUSH_DATA (push, 1);
418
419 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
420 PUSH_DATA (push, 0);
421 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
422 PUSH_DATA (push, 0x10);
423 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
424 PUSH_DATA (push, 0x10);
425 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
426 PUSH_DATA (push, 0x10);
427 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
428 PUSH_DATA (push, 0x10);
429 PUSH_DATA (push, 0x10);
430 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
431 PUSH_DATA (push, 0x10);
432 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
433 PUSH_DATA (push, 0xe);
434
435 BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
436 PUSH_DATA (push, 1 << 12);
437 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
438 PUSH_DATA (push, 0);
439 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
440 PUSH_DATA (push, 3);
441
442 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
443 PUSH_DATA (push, 0x3fffff);
444 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
445 PUSH_DATA (push, 1);
446 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
447 PUSH_DATA (push, 1);
448 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
449 PUSH_DATA (push, 3);
450
451 if (obj_class >= NVE4_3D_CLASS) {
452 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
453 PUSH_DATA (push, 1);
454 }
455
456 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
457 * are supposed to do */
458 }
459
460 static void
461 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
462 {
463 struct nvc0_screen *screen = nvc0_screen(pscreen);
464 struct nouveau_pushbuf *push = screen->base.pushbuf;
465
466 /* we need to do it after possible flush in MARK_RING */
467 *sequence = ++screen->base.fence.sequence;
468
469 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
470 PUSH_DATAh(push, screen->fence.bo->offset);
471 PUSH_DATA (push, screen->fence.bo->offset);
472 PUSH_DATA (push, *sequence);
473 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
474 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
475 }
476
477 static u32
478 nvc0_screen_fence_update(struct pipe_screen *pscreen)
479 {
480 struct nvc0_screen *screen = nvc0_screen(pscreen);
481 return screen->fence.map[0];
482 }
483
484 static int
485 nvc0_screen_init_compute(struct nvc0_screen *screen)
486 {
487 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
488
489 switch (screen->base.device->chipset & 0xf0) {
490 case 0xc0:
491 case 0xd0:
492 return 0;
493 case 0xe0:
494 case 0xf0:
495 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
496 default:
497 return -1;
498 }
499 }
500
501 boolean
502 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
503 uint32_t lpos, uint32_t lneg, uint32_t cstack)
504 {
505 struct nouveau_bo *bo = NULL;
506 int ret;
507 uint64_t size = (lpos + lneg) * 32 + cstack;
508
509 if (size >= (1 << 20)) {
510 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
511 return FALSE;
512 }
513
514 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
515 size *= screen->mp_count;
516
517 size = align(size, 1 << 17);
518
519 ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
520 NULL, &bo);
521 if (ret) {
522 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
523 return FALSE;
524 }
525 nouveau_bo_ref(NULL, &screen->tls);
526 screen->tls = bo;
527 return TRUE;
528 }
529
530 #define FAIL_SCREEN_INIT(str, err) \
531 do { \
532 NOUVEAU_ERR(str, err); \
533 nvc0_screen_destroy(pscreen); \
534 return NULL; \
535 } while(0)
536
537 struct pipe_screen *
538 nvc0_screen_create(struct nouveau_device *dev)
539 {
540 struct nvc0_screen *screen;
541 struct pipe_screen *pscreen;
542 struct nouveau_object *chan;
543 struct nouveau_pushbuf *push;
544 uint64_t value;
545 uint32_t obj_class;
546 int ret;
547 unsigned i;
548 union nouveau_bo_config mm_config;
549
550 switch (dev->chipset & ~0xf) {
551 case 0xc0:
552 case 0xd0:
553 case 0xe0:
554 case 0xf0:
555 break;
556 default:
557 return NULL;
558 }
559
560 screen = CALLOC_STRUCT(nvc0_screen);
561 if (!screen)
562 return NULL;
563 pscreen = &screen->base.base;
564
565 ret = nouveau_screen_init(&screen->base, dev);
566 if (ret) {
567 nvc0_screen_destroy(pscreen);
568 return NULL;
569 }
570 chan = screen->base.channel;
571 push = screen->base.pushbuf;
572 push->user_priv = screen;
573 push->rsvd_kick = 5;
574
575 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
576 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
577 screen->base.sysmem_bindings |=
578 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
579
580 pscreen->destroy = nvc0_screen_destroy;
581 pscreen->context_create = nvc0_create;
582 pscreen->is_format_supported = nvc0_screen_is_format_supported;
583 pscreen->get_param = nvc0_screen_get_param;
584 pscreen->get_shader_param = nvc0_screen_get_shader_param;
585 pscreen->get_paramf = nvc0_screen_get_paramf;
586 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
587
588 nvc0_screen_init_resource_functions(pscreen);
589
590 screen->base.base.get_video_param = nvc0_screen_get_video_param;
591 screen->base.base.is_video_format_supported = nvc0_screen_video_supported;
592
593 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
594 &screen->fence.bo);
595 if (ret)
596 goto fail;
597 nouveau_bo_map(screen->fence.bo, 0, NULL);
598 screen->fence.map = screen->fence.bo->map;
599 screen->base.fence.emit = nvc0_screen_fence_emit;
600 screen->base.fence.update = nvc0_screen_fence_update;
601
602 switch (dev->chipset & 0xf0) {
603 case 0xf0:
604 obj_class = NVF0_P2MF_CLASS;
605 break;
606 case 0xe0:
607 obj_class = NVE4_P2MF_CLASS;
608 break;
609 default:
610 obj_class = NVC0_M2MF_CLASS;
611 break;
612 }
613 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
614 &screen->m2mf);
615 if (ret)
616 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
617
618 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
619 PUSH_DATA (push, screen->m2mf->oclass);
620 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
621 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
622 PUSH_DATA (push, 0xa0b5);
623 }
624
625 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
626 &screen->eng2d);
627 if (ret)
628 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
629
630 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
631 PUSH_DATA (push, screen->eng2d->oclass);
632 BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
633 PUSH_DATA (push, 0);
634 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
635 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
636 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
637 PUSH_DATA (push, 0);
638 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
639 PUSH_DATA (push, 0);
640 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
641 PUSH_DATA (push, 0x3f);
642 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
643 PUSH_DATA (push, 1);
644
645 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
646 PUSH_DATAh(push, screen->fence.bo->offset + 16);
647 PUSH_DATA (push, screen->fence.bo->offset + 16);
648
649 switch (dev->chipset & 0xf0) {
650 case 0xf0:
651 obj_class = NVF0_3D_CLASS;
652 break;
653 case 0xe0:
654 obj_class = NVE4_3D_CLASS;
655 break;
656 case 0xd0:
657 case 0xc0:
658 default:
659 switch (dev->chipset) {
660 case 0xd9:
661 case 0xc8:
662 obj_class = NVC8_3D_CLASS;
663 break;
664 case 0xc1:
665 obj_class = NVC1_3D_CLASS;
666 break;
667 default:
668 obj_class = NVC0_3D_CLASS;
669 break;
670 }
671 break;
672 }
673 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
674 &screen->eng3d);
675 if (ret)
676 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
677 screen->base.class_3d = obj_class;
678
679 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
680 PUSH_DATA (push, screen->eng3d->oclass);
681
682 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
683 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
684
685 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
686 /* kill shaders after about 1 second (at 100 MHz) */
687 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
688 PUSH_DATA (push, 0x17);
689 }
690
691 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
692 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
693 for (i = 0; i < 8; ++i)
694 PUSH_DATA(push, dev->drm_version >= 0x01000101);
695
696 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
697 PUSH_DATA (push, 1);
698
699 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
700 PUSH_DATA (push, 0);
701 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
702 PUSH_DATA (push, 0);
703 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
704 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
705 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
706 PUSH_DATA (push, 0);
707 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
708 PUSH_DATA (push, 1);
709 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
710 PUSH_DATA (push, 0);
711 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
712 PUSH_DATA (push, 1);
713 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
714 PUSH_DATA (push, 0);
715 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
716 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
717 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
718 } else {
719 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
720 PUSH_DATA (push, 15);
721 }
722 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
723 PUSH_DATA (push, 8); /* 128 */
724 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
725 PUSH_DATA (push, 1);
726 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
727 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
728 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
729 }
730
731 nvc0_magic_3d_init(push, screen->eng3d->oclass);
732
733 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
734 &screen->text);
735 if (ret)
736 goto fail;
737
738 /* XXX: getting a page fault at the end of the code buffer every few
739 * launches, don't use the last 256 bytes to work around them - prefetch ?
740 */
741 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
742
743 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
744 &screen->uniform_bo);
745 if (ret)
746 goto fail;
747
748 for (i = 0; i < 5; ++i) {
749 /* TIC and TSC entries for each unit (nve4+ only) */
750 /* auxiliary constants (6 user clip planes, base instance id) */
751 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
752 PUSH_DATA (push, 512);
753 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
754 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
755 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
756 PUSH_DATA (push, (15 << 4) | 1);
757 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
758 unsigned j;
759 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
760 PUSH_DATA (push, 0);
761 for (j = 0; j < 8; ++j)
762 PUSH_DATA(push, j);
763 } else {
764 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
765 PUSH_DATA (push, 0x54);
766 }
767 }
768 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
769 PUSH_DATA (push, 0);
770
771 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
772 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
773 PUSH_DATA (push, 256);
774 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
775 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
776 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
777 PUSH_DATA (push, 0);
778 PUSH_DATAf(push, 0.0f);
779 PUSH_DATAf(push, 0.0f);
780 PUSH_DATAf(push, 0.0f);
781 PUSH_DATAf(push, 0.0f);
782 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
783 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
784 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
785
786 if (dev->drm_version >= 0x01000101) {
787 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
788 if (ret) {
789 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
790 goto fail;
791 }
792 } else {
793 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
794 value = (8 << 8) | 4;
795 else
796 value = (16 << 8) | 4;
797 }
798 screen->mp_count = value >> 8;
799 screen->mp_count_compute = screen->mp_count;
800
801 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
802
803 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
804 PUSH_DATAh(push, screen->text->offset);
805 PUSH_DATA (push, screen->text->offset);
806 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
807 PUSH_DATAh(push, screen->tls->offset);
808 PUSH_DATA (push, screen->tls->offset);
809 PUSH_DATA (push, screen->tls->size >> 32);
810 PUSH_DATA (push, screen->tls->size);
811 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
812 PUSH_DATA (push, 0);
813 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
814 PUSH_DATA (push, 0);
815
816 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
817 &screen->poly_cache);
818 if (ret)
819 goto fail;
820
821 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
822 PUSH_DATAh(push, screen->poly_cache->offset);
823 PUSH_DATA (push, screen->poly_cache->offset);
824 PUSH_DATA (push, 3);
825
826 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
827 &screen->txc);
828 if (ret)
829 goto fail;
830
831 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
832 PUSH_DATAh(push, screen->txc->offset);
833 PUSH_DATA (push, screen->txc->offset);
834 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
835
836 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
837 PUSH_DATAh(push, screen->txc->offset + 65536);
838 PUSH_DATA (push, screen->txc->offset + 65536);
839 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
840
841 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
842 PUSH_DATA (push, 0);
843 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
844 PUSH_DATA (push, 0);
845 PUSH_DATA (push, 0);
846 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
847 PUSH_DATA (push, 0x3f);
848
849 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
850 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
851 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
852 for (i = 0; i < 8 * 2; ++i)
853 PUSH_DATA(push, 0);
854 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
855 PUSH_DATA (push, 0);
856 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
857 PUSH_DATA (push, 0);
858
859 /* neither scissors, viewport nor stencil mask should affect clears */
860 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
861 PUSH_DATA (push, 0);
862
863 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
864 PUSH_DATA (push, 1);
865 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
866 PUSH_DATAf(push, 0.0f);
867 PUSH_DATAf(push, 1.0f);
868 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
869 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
870
871 /* We use scissors instead of exact view volume clipping,
872 * so they're always enabled.
873 */
874 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
875 PUSH_DATA (push, 1);
876 PUSH_DATA (push, 8192 << 16);
877 PUSH_DATA (push, 8192 << 16);
878
879 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
880
881 i = 0;
882 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
883 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
884 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
885 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
886 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
887 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
888 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
889
890 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
891 PUSH_DATA (push, 1);
892 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
893 PUSH_DATA (push, 1);
894 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
895 PUSH_DATA (push, 0x40);
896 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
897 PUSH_DATA (push, 0);
898 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
899 PUSH_DATA (push, 0x30);
900 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
901 PUSH_DATA (push, 3);
902 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
903 PUSH_DATA (push, 0x20);
904 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
905 PUSH_DATA (push, 0x00);
906
907 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
908 PUSH_DATA (push, 0);
909 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
910 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
911
912 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
913
914 if (nvc0_screen_init_compute(screen))
915 goto fail;
916
917 PUSH_KICK (push);
918
919 screen->tic.entries = CALLOC(4096, sizeof(void *));
920 screen->tsc.entries = screen->tic.entries + 2048;
921
922 mm_config.nvc0.tile_mode = 0;
923 mm_config.nvc0.memtype = 0xfe0;
924 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
925
926 if (!nvc0_blitter_create(screen))
927 goto fail;
928
929 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
930
931 return pscreen;
932
933 fail:
934 nvc0_screen_destroy(pscreen);
935 return NULL;
936 }
937
938 int
939 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
940 {
941 int i = screen->tic.next;
942
943 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
944 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
945
946 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
947
948 if (screen->tic.entries[i])
949 nv50_tic_entry(screen->tic.entries[i])->id = -1;
950
951 screen->tic.entries[i] = entry;
952 return i;
953 }
954
955 int
956 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
957 {
958 int i = screen->tsc.next;
959
960 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
961 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
962
963 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
964
965 if (screen->tsc.entries[i])
966 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
967
968 screen->tsc.entries[i] = entry;
969 return i;
970 }