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[mesa.git] / src / gallium / drivers / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "nvc0_context.h"
31 #include "nvc0_screen.h"
32
33 #include "nvc0_graph_macros.h"
34
35 static boolean
36 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
37 enum pipe_format format,
38 enum pipe_texture_target target,
39 unsigned sample_count,
40 unsigned bindings)
41 {
42 if (sample_count > 8)
43 return FALSE;
44 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
45 return FALSE;
46
47 if (!util_format_is_supported(format, bindings))
48 return FALSE;
49
50 switch (format) {
51 case PIPE_FORMAT_R8G8B8A8_UNORM:
52 case PIPE_FORMAT_R8G8B8X8_UNORM:
53 /* HACK: GL requires equal formats for MS resolve and window is BGRA */
54 if (bindings & PIPE_BIND_RENDER_TARGET)
55 return FALSE;
56 default:
57 break;
58 }
59
60 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
61 if (util_format_get_blocksizebits(format) == 3 * 32)
62 return FALSE;
63
64 /* transfers & shared are always supported */
65 bindings &= ~(PIPE_BIND_TRANSFER_READ |
66 PIPE_BIND_TRANSFER_WRITE |
67 PIPE_BIND_SHARED);
68
69 return (nvc0_format_table[format].usage & bindings) == bindings;
70 }
71
72 static boolean
73 nvc0_screen_video_supported(struct pipe_screen *screen,
74 enum pipe_format format,
75 enum pipe_video_profile profile)
76 {
77 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
78 return format == PIPE_FORMAT_NV12;
79
80 return vl_video_buffer_is_format_supported(screen, format, profile);
81 }
82
83
84 static int
85 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
86 {
87 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
88
89 switch (param) {
90 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
91 return 16 * 5;
92 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
93 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
94 return 15;
95 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
96 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
97 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
98 return 2048;
99 case PIPE_CAP_MIN_TEXEL_OFFSET:
100 return -8;
101 case PIPE_CAP_MAX_TEXEL_OFFSET:
102 return 7;
103 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
104 case PIPE_CAP_TEXTURE_SWIZZLE:
105 case PIPE_CAP_TEXTURE_SHADOW_MAP:
106 case PIPE_CAP_NPOT_TEXTURES:
107 case PIPE_CAP_ANISOTROPIC_FILTER:
108 case PIPE_CAP_SEAMLESS_CUBE_MAP:
109 case PIPE_CAP_CUBE_MAP_ARRAY:
110 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
111 return 1;
112 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
113 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
114 case PIPE_CAP_TWO_SIDED_STENCIL:
115 case PIPE_CAP_DEPTH_CLIP_DISABLE:
116 case PIPE_CAP_POINT_SPRITE:
117 return 1;
118 case PIPE_CAP_SM3:
119 return 1;
120 case PIPE_CAP_GLSL_FEATURE_LEVEL:
121 return 150;
122 case PIPE_CAP_MAX_RENDER_TARGETS:
123 return 8;
124 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
125 return 1;
126 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
127 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
128 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
129 return 1;
130 case PIPE_CAP_QUERY_TIMESTAMP:
131 case PIPE_CAP_QUERY_TIME_ELAPSED:
132 case PIPE_CAP_OCCLUSION_QUERY:
133 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
134 return 1;
135 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
136 return 4;
137 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
138 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
139 return 128;
140 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
141 case PIPE_CAP_INDEP_BLEND_ENABLE:
142 case PIPE_CAP_INDEP_BLEND_FUNC:
143 return 1;
144 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
145 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
146 return 1;
147 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
148 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
149 return 0;
150 case PIPE_CAP_SHADER_STENCIL_EXPORT:
151 return 0;
152 case PIPE_CAP_PRIMITIVE_RESTART:
153 case PIPE_CAP_TGSI_INSTANCEID:
154 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
155 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
156 case PIPE_CAP_CONDITIONAL_RENDER:
157 case PIPE_CAP_TEXTURE_BARRIER:
158 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
159 case PIPE_CAP_START_INSTANCE:
160 return 1;
161 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
162 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
163 return 0; /* state trackers will know better */
164 case PIPE_CAP_USER_CONSTANT_BUFFERS:
165 case PIPE_CAP_USER_INDEX_BUFFERS:
166 case PIPE_CAP_USER_VERTEX_BUFFERS:
167 return 1;
168 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
169 return 256;
170 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
171 return 1; /* 256 for binding as RT, but that's not possible in GL */
172 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
173 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
174 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
175 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
176 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
177 case PIPE_CAP_TEXTURE_MULTISAMPLE:
178 return 0;
179 case PIPE_CAP_COMPUTE:
180 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
181 default:
182 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
183 return 0;
184 }
185 }
186
187 static int
188 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
189 enum pipe_shader_cap param)
190 {
191 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
192
193 switch (shader) {
194 case PIPE_SHADER_VERTEX:
195 /*
196 case PIPE_SHADER_TESSELLATION_CONTROL:
197 case PIPE_SHADER_TESSELLATION_EVALUATION:
198 */
199 case PIPE_SHADER_GEOMETRY:
200 case PIPE_SHADER_FRAGMENT:
201 break;
202 case PIPE_SHADER_COMPUTE:
203 if (class_3d < NVE4_3D_CLASS)
204 return 0;
205 break;
206 default:
207 return 0;
208 }
209
210 switch (param) {
211 case PIPE_SHADER_CAP_PREFERRED_IR:
212 return PIPE_SHADER_IR_TGSI;
213 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
214 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
215 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
216 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
217 return 16384;
218 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
219 return 16;
220 case PIPE_SHADER_CAP_MAX_INPUTS:
221 if (shader == PIPE_SHADER_VERTEX)
222 return 32;
223 if (shader == PIPE_SHADER_FRAGMENT)
224 return (0x200 + 0x20 + 0x80) / 16; /* generic + colors + TexCoords */
225 return (0x200 + 0x40 + 0x80) / 16; /* without 0x60 for per-patch inputs */
226 case PIPE_SHADER_CAP_MAX_CONSTS:
227 return 65536 / 16;
228 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
229 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
230 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
231 return NVC0_MAX_PIPE_CONSTBUFS;
232 case PIPE_SHADER_CAP_MAX_ADDRS:
233 return 1;
234 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
235 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
236 return shader != PIPE_SHADER_FRAGMENT;
237 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
238 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
239 return 1;
240 case PIPE_SHADER_CAP_MAX_PREDS:
241 return 0;
242 case PIPE_SHADER_CAP_MAX_TEMPS:
243 return NVC0_CAP_MAX_PROGRAM_TEMPS;
244 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
245 return 1;
246 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
247 return 0;
248 case PIPE_SHADER_CAP_SUBROUTINES:
249 return 1;
250 case PIPE_SHADER_CAP_INTEGERS:
251 return 1;
252 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
253 return 16; /* would be 32 in linked (OpenGL-style) mode */
254 /*
255 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
256 return 32;
257 */
258 default:
259 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
260 return 0;
261 }
262 }
263
264 static float
265 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
266 {
267 switch (param) {
268 case PIPE_CAPF_MAX_LINE_WIDTH:
269 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
270 return 10.0f;
271 case PIPE_CAPF_MAX_POINT_WIDTH:
272 return 63.0f;
273 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
274 return 63.375f;
275 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
276 return 16.0f;
277 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
278 return 15.0f;
279 default:
280 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
281 return 0.0f;
282 }
283 }
284
285 static int
286 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
287 enum pipe_compute_cap param, void *data)
288 {
289 uint64_t *data64 = (uint64_t *)data;
290 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
291
292 switch (param) {
293 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
294 data64[0] = 3;
295 return 8;
296 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
297 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
298 data64[1] = 65535;
299 data64[2] = 65535;
300 return 24;
301 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
302 data64[0] = 1024;
303 data64[1] = 1024;
304 data64[2] = 64;
305 return 24;
306 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
307 data64[0] = 1024;
308 return 8;
309 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
310 data64[0] = (uint64_t)1 << 40;
311 return 8;
312 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
313 data64[0] = 48 << 10;
314 return 8;
315 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
316 data64[0] = 512 << 10;
317 return 8;
318 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
319 data64[0] = 4096;
320 return 8;
321 default:
322 return 0;
323 }
324 }
325
326 static void
327 nvc0_screen_destroy(struct pipe_screen *pscreen)
328 {
329 struct nvc0_screen *screen = nvc0_screen(pscreen);
330
331 if (screen->base.fence.current) {
332 nouveau_fence_wait(screen->base.fence.current);
333 nouveau_fence_ref(NULL, &screen->base.fence.current);
334 }
335 if (screen->base.pushbuf)
336 screen->base.pushbuf->user_priv = NULL;
337
338 if (screen->blitter)
339 nvc0_blitter_destroy(screen);
340
341 nouveau_bo_ref(NULL, &screen->text);
342 nouveau_bo_ref(NULL, &screen->uniform_bo);
343 nouveau_bo_ref(NULL, &screen->tls);
344 nouveau_bo_ref(NULL, &screen->txc);
345 nouveau_bo_ref(NULL, &screen->fence.bo);
346 nouveau_bo_ref(NULL, &screen->poly_cache);
347 nouveau_bo_ref(NULL, &screen->parm);
348
349 nouveau_heap_destroy(&screen->lib_code);
350 nouveau_heap_destroy(&screen->text_heap);
351
352 FREE(screen->tic.entries);
353
354 nouveau_mm_destroy(screen->mm_VRAM_fe0);
355
356 nouveau_object_del(&screen->eng3d);
357 nouveau_object_del(&screen->eng2d);
358 nouveau_object_del(&screen->m2mf);
359
360 nouveau_screen_fini(&screen->base);
361
362 FREE(screen);
363 }
364
365 static int
366 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
367 unsigned size, const uint32_t *data)
368 {
369 struct nouveau_pushbuf *push = screen->base.pushbuf;
370
371 size /= 4;
372
373 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
374 PUSH_DATA (push, (m - 0x3800) / 8);
375 PUSH_DATA (push, pos);
376 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
377 PUSH_DATA (push, pos);
378 PUSH_DATAp(push, data, size);
379
380 return pos + size;
381 }
382
383 static void
384 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
385 {
386 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
387 PUSH_DATA (push, 0xff);
388 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
389 PUSH_DATA (push, 0xff);
390 PUSH_DATA (push, 0xff);
391 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
392 PUSH_DATA (push, 0xff);
393 PUSH_DATA (push, 0xff);
394 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
395 PUSH_DATA (push, 0x3f);
396
397 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
398 PUSH_DATA (push, (3 << 16) | 3);
399 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
400 PUSH_DATA (push, (2 << 16) | 2);
401 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
402 PUSH_DATA (push, 1);
403
404 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
405 PUSH_DATA (push, 0);
406 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
407 PUSH_DATA (push, 0x10);
408 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
409 PUSH_DATA (push, 0x10);
410 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
411 PUSH_DATA (push, 0x10);
412 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
413 PUSH_DATA (push, 0x10);
414 PUSH_DATA (push, 0x10);
415 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
416 PUSH_DATA (push, 0x10);
417 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
418 PUSH_DATA (push, 0xe);
419
420 BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
421 PUSH_DATA (push, 1 << 12);
422 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
423 PUSH_DATA (push, 0);
424 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
425 PUSH_DATA (push, 3);
426
427 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
428 PUSH_DATA (push, 0x3fffff);
429 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
430 PUSH_DATA (push, 1);
431 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
432 PUSH_DATA (push, 1);
433 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
434 PUSH_DATA (push, 3);
435
436 if (obj_class >= NVE4_3D_CLASS) {
437 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
438 PUSH_DATA (push, 1);
439 }
440
441 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
442 * are supposed to do */
443 }
444
445 static void
446 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
447 {
448 struct nvc0_screen *screen = nvc0_screen(pscreen);
449 struct nouveau_pushbuf *push = screen->base.pushbuf;
450
451 /* we need to do it after possible flush in MARK_RING */
452 *sequence = ++screen->base.fence.sequence;
453
454 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
455 PUSH_DATAh(push, screen->fence.bo->offset);
456 PUSH_DATA (push, screen->fence.bo->offset);
457 PUSH_DATA (push, *sequence);
458 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
459 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
460 }
461
462 static u32
463 nvc0_screen_fence_update(struct pipe_screen *pscreen)
464 {
465 struct nvc0_screen *screen = nvc0_screen(pscreen);
466 return screen->fence.map[0];
467 }
468
469 static int
470 nvc0_screen_init_compute(struct nvc0_screen *screen)
471 {
472 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
473
474 switch (screen->base.device->chipset & 0xf0) {
475 case 0xc0:
476 case 0xd0:
477 return 0;
478 case 0xe0:
479 case 0xf0:
480 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
481 default:
482 return -1;
483 }
484 }
485
486 #define FAIL_SCREEN_INIT(str, err) \
487 do { \
488 NOUVEAU_ERR(str, err); \
489 nvc0_screen_destroy(pscreen); \
490 return NULL; \
491 } while(0)
492
493 struct pipe_screen *
494 nvc0_screen_create(struct nouveau_device *dev)
495 {
496 struct nvc0_screen *screen;
497 struct pipe_screen *pscreen;
498 struct nouveau_object *chan;
499 struct nouveau_pushbuf *push;
500 uint32_t obj_class;
501 int ret;
502 unsigned i;
503 union nouveau_bo_config mm_config;
504
505 switch (dev->chipset & ~0xf) {
506 case 0xc0:
507 case 0xd0:
508 case 0xe0:
509 break;
510 default:
511 return NULL;
512 }
513
514 screen = CALLOC_STRUCT(nvc0_screen);
515 if (!screen)
516 return NULL;
517 pscreen = &screen->base.base;
518
519 ret = nouveau_screen_init(&screen->base, dev);
520 if (ret) {
521 nvc0_screen_destroy(pscreen);
522 return NULL;
523 }
524 chan = screen->base.channel;
525 push = screen->base.pushbuf;
526 push->user_priv = screen;
527
528 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
529 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
530 screen->base.sysmem_bindings |=
531 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
532
533 pscreen->destroy = nvc0_screen_destroy;
534 pscreen->context_create = nvc0_create;
535 pscreen->is_format_supported = nvc0_screen_is_format_supported;
536 pscreen->get_param = nvc0_screen_get_param;
537 pscreen->get_shader_param = nvc0_screen_get_shader_param;
538 pscreen->get_paramf = nvc0_screen_get_paramf;
539
540 nvc0_screen_init_resource_functions(pscreen);
541
542 screen->base.base.get_video_param = nvc0_screen_get_video_param;
543 screen->base.base.is_video_format_supported = nvc0_screen_video_supported;
544
545 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
546 &screen->fence.bo);
547 if (ret)
548 goto fail;
549 nouveau_bo_map(screen->fence.bo, 0, NULL);
550 screen->fence.map = screen->fence.bo->map;
551 screen->base.fence.emit = nvc0_screen_fence_emit;
552 screen->base.fence.update = nvc0_screen_fence_update;
553
554 switch (dev->chipset & 0xf0) {
555 case 0xe0:
556 obj_class = NVE4_P2MF_CLASS;
557 break;
558 default:
559 obj_class = NVC0_M2MF_CLASS;
560 break;
561 }
562 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
563 &screen->m2mf);
564 if (ret)
565 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
566
567 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
568 PUSH_DATA (push, screen->m2mf->oclass);
569 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
570 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
571 PUSH_DATA (push, 0xa0b5);
572 }
573
574 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
575 &screen->eng2d);
576 if (ret)
577 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
578
579 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
580 PUSH_DATA (push, screen->eng2d->oclass);
581 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
582 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
583 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
584 PUSH_DATA (push, 0);
585 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
586 PUSH_DATA (push, 0);
587 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
588 PUSH_DATA (push, 0x3f);
589 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
590 PUSH_DATA (push, 1);
591
592 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
593 PUSH_DATAh(push, screen->fence.bo->offset + 16);
594 PUSH_DATA (push, screen->fence.bo->offset + 16);
595
596 switch (dev->chipset & 0xf0) {
597 case 0xe0:
598 obj_class = NVE4_3D_CLASS;
599 break;
600 case 0xd0:
601 case 0xc0:
602 default:
603 switch (dev->chipset) {
604 case 0xd9:
605 case 0xc8:
606 obj_class = NVC8_3D_CLASS;
607 break;
608 case 0xc1:
609 obj_class = NVC1_3D_CLASS;
610 break;
611 default:
612 obj_class = NVC0_3D_CLASS;
613 break;
614 }
615 break;
616 }
617 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
618 &screen->eng3d);
619 if (ret)
620 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
621 screen->base.class_3d = obj_class;
622
623 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
624 PUSH_DATA (push, screen->eng3d->oclass);
625
626 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
627 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
628
629 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
630 /* kill shaders after about 1 second (at 100 MHz) */
631 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
632 PUSH_DATA (push, 0x17);
633 }
634
635 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
636 PUSH_DATA (push, 1);
637
638 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
639 PUSH_DATA (push, 0);
640 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
641 PUSH_DATA (push, 0);
642 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
643 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
644 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
645 PUSH_DATA (push, 0);
646 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
647 PUSH_DATA (push, 1);
648 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
649 PUSH_DATA (push, 0);
650 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
651 PUSH_DATA (push, 1);
652 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
653 PUSH_DATA (push, 0);
654 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
655 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
656 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
657 } else {
658 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
659 PUSH_DATA (push, 15);
660 }
661 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
662 PUSH_DATA (push, 8); /* 128 */
663 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
664 PUSH_DATA (push, 1);
665 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
666 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
667 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
668 }
669
670 nvc0_magic_3d_init(push, screen->eng3d->oclass);
671
672 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
673 &screen->text);
674 if (ret)
675 goto fail;
676
677 /* XXX: getting a page fault at the end of the code buffer every few
678 * launches, don't use the last 256 bytes to work around them - prefetch ?
679 */
680 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
681
682 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
683 &screen->uniform_bo);
684 if (ret)
685 goto fail;
686
687 for (i = 0; i < 5; ++i) {
688 /* TIC and TSC entries for each unit (nve4+ only) */
689 /* auxiliary constants (6 user clip planes, base instance id) */
690 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
691 PUSH_DATA (push, 512);
692 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
693 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
694 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
695 PUSH_DATA (push, (15 << 4) | 1);
696 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
697 unsigned j;
698 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
699 PUSH_DATA (push, 0);
700 for (j = 0; j < 8; ++j)
701 PUSH_DATA(push, j);
702 } else {
703 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
704 PUSH_DATA (push, 0x54);
705 }
706 }
707 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
708 PUSH_DATA (push, 0);
709
710 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
711 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
712 PUSH_DATA (push, 256);
713 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
714 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
715 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
716 PUSH_DATA (push, 0);
717 PUSH_DATAf(push, 0.0f);
718 PUSH_DATAf(push, 0.0f);
719 PUSH_DATAf(push, 0.0f);
720 PUSH_DATAf(push, 0.0f);
721 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
722 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
723 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
724
725 /* max MPs * max warps per MP (TODO: ask kernel) */
726 if (screen->eng3d->oclass >= NVE4_3D_CLASS)
727 screen->tls_size = 8 * 64 * 32;
728 else
729 screen->tls_size = 16 * 48 * 32;
730 screen->tls_size *= NVC0_CAP_MAX_PROGRAM_TEMPS * 16;
731 screen->tls_size = align(screen->tls_size, 1 << 17);
732
733 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
734 screen->tls_size, NULL, &screen->tls);
735 if (ret)
736 goto fail;
737
738 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
739 PUSH_DATAh(push, screen->text->offset);
740 PUSH_DATA (push, screen->text->offset);
741 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
742 PUSH_DATAh(push, screen->tls->offset);
743 PUSH_DATA (push, screen->tls->offset);
744 PUSH_DATA (push, screen->tls_size >> 32);
745 PUSH_DATA (push, screen->tls_size);
746 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
747 PUSH_DATA (push, 0);
748 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
749 PUSH_DATA (push, 0);
750
751 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
752 &screen->poly_cache);
753 if (ret)
754 goto fail;
755
756 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
757 PUSH_DATAh(push, screen->poly_cache->offset);
758 PUSH_DATA (push, screen->poly_cache->offset);
759 PUSH_DATA (push, 3);
760
761 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
762 &screen->txc);
763 if (ret)
764 goto fail;
765
766 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
767 PUSH_DATAh(push, screen->txc->offset);
768 PUSH_DATA (push, screen->txc->offset);
769 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
770
771 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
772 PUSH_DATAh(push, screen->txc->offset + 65536);
773 PUSH_DATA (push, screen->txc->offset + 65536);
774 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
775
776 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
777 PUSH_DATA (push, 0);
778 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
779 PUSH_DATA (push, 0);
780 PUSH_DATA (push, 0);
781 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
782 PUSH_DATA (push, 0x3f);
783
784 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
785 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
786 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
787 for (i = 0; i < 8 * 2; ++i)
788 PUSH_DATA(push, 0);
789 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
790 PUSH_DATA (push, 0);
791 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
792 PUSH_DATA (push, 0);
793
794 /* neither scissors, viewport nor stencil mask should affect clears */
795 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
796 PUSH_DATA (push, 0);
797
798 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
799 PUSH_DATA (push, 1);
800 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
801 PUSH_DATAf(push, 0.0f);
802 PUSH_DATAf(push, 1.0f);
803 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
804 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
805
806 /* We use scissors instead of exact view volume clipping,
807 * so they're always enabled.
808 */
809 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
810 PUSH_DATA (push, 1);
811 PUSH_DATA (push, 8192 << 16);
812 PUSH_DATA (push, 8192 << 16);
813
814 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
815
816 i = 0;
817 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
818 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
819 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
820 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
821 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
822 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
823 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
824
825 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
826 PUSH_DATA (push, 1);
827 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
828 PUSH_DATA (push, 1);
829 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
830 PUSH_DATA (push, 0x40);
831 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
832 PUSH_DATA (push, 0);
833 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
834 PUSH_DATA (push, 0x30);
835 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
836 PUSH_DATA (push, 3);
837 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
838 PUSH_DATA (push, 0x20);
839 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
840 PUSH_DATA (push, 0x00);
841
842 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
843 PUSH_DATA (push, 0);
844 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
845 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
846
847 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
848
849 if (nvc0_screen_init_compute(screen))
850 goto fail;
851
852 PUSH_KICK (push);
853
854 screen->tic.entries = CALLOC(4096, sizeof(void *));
855 screen->tsc.entries = screen->tic.entries + 2048;
856
857 mm_config.nvc0.tile_mode = 0;
858 mm_config.nvc0.memtype = 0xfe0;
859 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
860
861 if (!nvc0_blitter_create(screen))
862 goto fail;
863
864 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
865
866 return pscreen;
867
868 fail:
869 nvc0_screen_destroy(pscreen);
870 return NULL;
871 }
872
873 int
874 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
875 {
876 int i = screen->tic.next;
877
878 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
879 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
880
881 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
882
883 if (screen->tic.entries[i])
884 nv50_tic_entry(screen->tic.entries[i])->id = -1;
885
886 screen->tic.entries[i] = entry;
887 return i;
888 }
889
890 int
891 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
892 {
893 int i = screen->tsc.next;
894
895 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
896 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
897
898 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
899
900 if (screen->tsc.entries[i])
901 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
902
903 screen->tsc.entries[i] = entry;
904 return i;
905 }