src/gallium/drivers/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nvc0_context.h"
  31 #include "nvc0_screen.h"
  32
  33 #include "nvc0_graph_macros.h"
  34
  35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  37 #endif
  38
  39 static boolean
  40 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings)
  45 {
  46    if (sample_count > 8)
  47       return FALSE;
  48    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  49       return FALSE;
  50
  51    if (!util_format_is_supported(format, bindings))
  52       return FALSE;
  53
  54    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  55       if (util_format_get_blocksizebits(format) == 3 * 32)
  56          return FALSE;
  57
  58    /* transfers & shared are always supported */
  59    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  60                  PIPE_BIND_TRANSFER_WRITE |
  61                  PIPE_BIND_SHARED);
  62
  63    return (nvc0_format_table[format].usage & bindings) == bindings;
  64 }
  65
  66 static boolean
  67 nvc0_screen_video_supported(struct pipe_screen *screen,
  68                             enum pipe_format format,
  69                             enum pipe_video_profile profile)
  70 {
  71    if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
  72       return format == PIPE_FORMAT_NV12;
  73
  74    return vl_video_buffer_is_format_supported(screen, format, profile);
  75 }
  76
  77
  78 static int
  79 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  80 {
  81    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  82
  83    switch (param) {
  84    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  85       return 16 * 5;
  86    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  87    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  88       return 15;
  89    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  90       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  91    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  92       return 2048;
  93    case PIPE_CAP_MIN_TEXEL_OFFSET:
  94       return -8;
  95    case PIPE_CAP_MAX_TEXEL_OFFSET:
  96       return 7;
  97    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  98    case PIPE_CAP_TEXTURE_SWIZZLE:
  99    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 100    case PIPE_CAP_NPOT_TEXTURES:
 101    case PIPE_CAP_ANISOTROPIC_FILTER:
 102    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 103    case PIPE_CAP_CUBE_MAP_ARRAY:
 104    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 105    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 106       return 1;
 107    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 108       return 65536;
 109    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 110       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 111    case PIPE_CAP_TWO_SIDED_STENCIL:
 112    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 113    case PIPE_CAP_POINT_SPRITE:
 114    case PIPE_CAP_TGSI_TEXCOORD:
 115       return 1;
 116    case PIPE_CAP_SM3:
 117       return 1;
 118    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 119       return 150;
 120    case PIPE_CAP_MAX_RENDER_TARGETS:
 121       return 8;
 122    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 123       return 1;
 124    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 125    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 126    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 127       return 1;
 128    case PIPE_CAP_QUERY_TIMESTAMP:
 129    case PIPE_CAP_QUERY_TIME_ELAPSED:
 130    case PIPE_CAP_OCCLUSION_QUERY:
 131    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 132    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 133       return 1;
 134    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 135       return 4;
 136    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 138       return 128;
 139    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 140    case PIPE_CAP_INDEP_BLEND_ENABLE:
 141    case PIPE_CAP_INDEP_BLEND_FUNC:
 142       return 1;
 143    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 144    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 145       return 1;
 146    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 147    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 148       return 0;
 149    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 150       return 0;
 151    case PIPE_CAP_PRIMITIVE_RESTART:
 152    case PIPE_CAP_TGSI_INSTANCEID:
 153    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 154    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 155    case PIPE_CAP_CONDITIONAL_RENDER:
 156    case PIPE_CAP_TEXTURE_BARRIER:
 157    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 158    case PIPE_CAP_START_INSTANCE:
 159       return 1;
 160    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 161    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 162       return 0; /* state trackers will know better */
 163    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 164    case PIPE_CAP_USER_INDEX_BUFFERS:
 165    case PIPE_CAP_USER_VERTEX_BUFFERS:
 166       return 1;
 167    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 168       return 256;
 169    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 170       return 1; /* 256 for binding as RT, but that's not possible in GL */
 171    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 172       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 173    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 174    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 175    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 176       return 0;
 177    case PIPE_CAP_COMPUTE:
 178       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 179    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 180       return 1;
 181    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 182       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 183    default:
 184       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 185       return 0;
 186    }
 187 }
 188
 189 static int
 190 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 191                              enum pipe_shader_cap param)
 192 {
 193    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 194
 195    switch (shader) {
 196    case PIPE_SHADER_VERTEX:
 197       /*
 198    case PIPE_SHADER_TESSELLATION_CONTROL:
 199    case PIPE_SHADER_TESSELLATION_EVALUATION:
 200       */
 201    case PIPE_SHADER_GEOMETRY:
 202    case PIPE_SHADER_FRAGMENT:
 203       break;
 204    case PIPE_SHADER_COMPUTE:
 205       if (class_3d < NVE4_3D_CLASS)
 206          return 0;
 207       break;
 208    default:
 209       return 0;
 210    }
 211
 212    switch (param) {
 213    case PIPE_SHADER_CAP_PREFERRED_IR:
 214       return PIPE_SHADER_IR_TGSI;
 215    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 216    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 217    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 218    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 219       return 16384;
 220    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 221       return 16;
 222    case PIPE_SHADER_CAP_MAX_INPUTS:
 223       if (shader == PIPE_SHADER_VERTEX)
 224          return 32;
 225       /* NOTE: These only count our slots for GENERIC varyings.
 226        * The address space may be larger, but the actual hard limit seems to be
 227        * less than what the address space layout permits, so don't add TEXCOORD,
 228        * COLOR, etc. here.
 229        */
 230       if (shader == PIPE_SHADER_FRAGMENT)
 231          return 0x1f0 / 16;
 232       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 233        * and excludes 0x60 per-patch inputs.
 234        */
 235       return 0x200 / 16;
 236    case PIPE_SHADER_CAP_MAX_CONSTS:
 237       return 65536 / 16;
 238    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 239       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
 240          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
 241       return NVC0_MAX_PIPE_CONSTBUFS;
 242    case PIPE_SHADER_CAP_MAX_ADDRS:
 243       return 1;
 244    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 245    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 246       return shader != PIPE_SHADER_FRAGMENT;
 247    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 248    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 249       return 1;
 250    case PIPE_SHADER_CAP_MAX_PREDS:
 251       return 0;
 252    case PIPE_SHADER_CAP_MAX_TEMPS:
 253       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 254    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 255       return 1;
 256    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 257       return 0;
 258    case PIPE_SHADER_CAP_SUBROUTINES:
 259       return 1;
 260    case PIPE_SHADER_CAP_INTEGERS:
 261       return 1;
 262    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 263       return 16; /* would be 32 in linked (OpenGL-style) mode */
 264       /*
 265    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
 266       return 32;
 267       */
 268    default:
 269       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 270       return 0;
 271    }
 272 }
 273
 274 static float
 275 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 276 {
 277    switch (param) {
 278    case PIPE_CAPF_MAX_LINE_WIDTH:
 279    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 280       return 10.0f;
 281    case PIPE_CAPF_MAX_POINT_WIDTH:
 282       return 63.0f;
 283    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 284       return 63.375f;
 285    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 286       return 16.0f;
 287    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 288       return 15.0f;
 289    default:
 290       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 291       return 0.0f;
 292    }
 293 }
 294
 295 static int
 296 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 297                               enum pipe_compute_cap param, void *data)
 298 {
 299    uint64_t *data64 = (uint64_t *)data;
 300    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
 301
 302    switch (param) {
 303    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 304       data64[0] = 3;
 305       return 8;
 306    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 307       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
 308       data64[1] = 65535;
 309       data64[2] = 65535;
 310       return 24;
 311    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 312       data64[0] = 1024;
 313       data64[1] = 1024;
 314       data64[2] = 64;
 315       return 24;
 316    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 317       data64[0] = 1024;
 318       return 8;
 319    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 320       data64[0] = (uint64_t)1 << 40;
 321       return 8;
 322    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 323       data64[0] = 48 << 10;
 324       return 8;
 325    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 326       data64[0] = 512 << 10;
 327       return 8;
 328    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 329       data64[0] = 4096;
 330       return 8;
 331    default:
 332       return 0;
 333    }
 334 }
 335
 336 static void
 337 nvc0_screen_destroy(struct pipe_screen *pscreen)
 338 {
 339    struct nvc0_screen *screen = nvc0_screen(pscreen);
 340
 341    if (screen->base.fence.current) {
 342       nouveau_fence_wait(screen->base.fence.current);
 343       nouveau_fence_ref(NULL, &screen->base.fence.current);
 344    }
 345    if (screen->base.pushbuf)
 346       screen->base.pushbuf->user_priv = NULL;
 347
 348    if (screen->blitter)
 349       nvc0_blitter_destroy(screen);
 350    if (screen->pm.prog) {
 351       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 352       nvc0_program_destroy(NULL, screen->pm.prog);
 353    }
 354
 355    nouveau_bo_ref(NULL, &screen->text);
 356    nouveau_bo_ref(NULL, &screen->uniform_bo);
 357    nouveau_bo_ref(NULL, &screen->tls);
 358    nouveau_bo_ref(NULL, &screen->txc);
 359    nouveau_bo_ref(NULL, &screen->fence.bo);
 360    nouveau_bo_ref(NULL, &screen->poly_cache);
 361    nouveau_bo_ref(NULL, &screen->parm);
 362
 363    nouveau_heap_destroy(&screen->lib_code);
 364    nouveau_heap_destroy(&screen->text_heap);
 365
 366    FREE(screen->tic.entries);
 367
 368    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 369
 370    nouveau_object_del(&screen->eng3d);
 371    nouveau_object_del(&screen->eng2d);
 372    nouveau_object_del(&screen->m2mf);
 373
 374    nouveau_screen_fini(&screen->base);
 375
 376    FREE(screen);
 377 }
 378
 379 static int
 380 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 381                      unsigned size, const uint32_t *data)
 382 {
 383    struct nouveau_pushbuf *push = screen->base.pushbuf;
 384
 385    size /= 4;
 386
 387    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 388    PUSH_DATA (push, (m - 0x3800) / 8);
 389    PUSH_DATA (push, pos);
 390    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 391    PUSH_DATA (push, pos);
 392    PUSH_DATAp(push, data, size);
 393
 394    return pos + size;
 395 }
 396
 397 static void
 398 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 399 {
 400    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 401    PUSH_DATA (push, 0xff);
 402    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 403    PUSH_DATA (push, 0xff);
 404    PUSH_DATA (push, 0xff);
 405    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 406    PUSH_DATA (push, 0xff);
 407    PUSH_DATA (push, 0xff);
 408    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 409    PUSH_DATA (push, 0x3f);
 410
 411    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 412    PUSH_DATA (push, (3 << 16) | 3);
 413    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 414    PUSH_DATA (push, (2 << 16) | 2);
 415    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
 416    PUSH_DATA (push, 1);
 417
 418    BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 419    PUSH_DATA (push, 0);
 420    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 421    PUSH_DATA (push, 0x10);
 422    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 423    PUSH_DATA (push, 0x10);
 424    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 425    PUSH_DATA (push, 0x10);
 426    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 427    PUSH_DATA (push, 0x10);
 428    PUSH_DATA (push, 0x10);
 429    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 430    PUSH_DATA (push, 0x10);
 431    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 432    PUSH_DATA (push, 0xe);
 433
 434    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
 435    PUSH_DATA (push, 1 << 12);
 436    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 437    PUSH_DATA (push, 0);
 438    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 439    PUSH_DATA (push, 3);
 440
 441    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 442    PUSH_DATA (push, 0x3fffff);
 443    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 444    PUSH_DATA (push, 1);
 445    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 446    PUSH_DATA (push, 1);
 447    BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 448    PUSH_DATA (push, 3);
 449
 450    if (obj_class >= NVE4_3D_CLASS) {
 451       BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 452       PUSH_DATA (push, 1);
 453    }
 454
 455    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 456     * are supposed to do */
 457 }
 458
 459 static void
 460 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 461 {
 462    struct nvc0_screen *screen = nvc0_screen(pscreen);
 463    struct nouveau_pushbuf *push = screen->base.pushbuf;
 464
 465    /* we need to do it after possible flush in MARK_RING */
 466    *sequence = ++screen->base.fence.sequence;
 467
 468    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
 469    PUSH_DATAh(push, screen->fence.bo->offset);
 470    PUSH_DATA (push, screen->fence.bo->offset);
 471    PUSH_DATA (push, *sequence);
 472    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 473               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 474 }
 475
 476 static u32
 477 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 478 {
 479    struct nvc0_screen *screen = nvc0_screen(pscreen);
 480    return screen->fence.map[0];
 481 }
 482
 483 static int
 484 nvc0_screen_init_compute(struct nvc0_screen *screen)
 485 {
 486    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 487
 488    switch (screen->base.device->chipset & 0xf0) {
 489    case 0xc0:
 490    case 0xd0:
 491       return 0;
 492    case 0xe0:
 493    case 0xf0:
 494       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 495    default:
 496       return -1;
 497    }
 498 }
 499
 500 boolean
 501 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 502                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 503 {
 504    struct nouveau_bo *bo = NULL;
 505    int ret;
 506    uint64_t size = (lpos + lneg) * 32 + cstack;
 507
 508    if (size >= (1 << 20)) {
 509       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 510       return FALSE;
 511    }
 512
 513    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 514    size *= screen->mp_count;
 515
 516    size = align(size, 1 << 17);
 517
 518    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
 519                         NULL, &bo);
 520    if (ret) {
 521       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 522       return FALSE;
 523    }
 524    nouveau_bo_ref(NULL, &screen->tls);
 525    screen->tls = bo;
 526    return TRUE;
 527 }
 528
 529 #define FAIL_SCREEN_INIT(str, err)                    \
 530    do {                                               \
 531       NOUVEAU_ERR(str, err);                          \
 532       nvc0_screen_destroy(pscreen);                   \
 533       return NULL;                                    \
 534    } while(0)
 535
 536 struct pipe_screen *
 537 nvc0_screen_create(struct nouveau_device *dev)
 538 {
 539    struct nvc0_screen *screen;
 540    struct pipe_screen *pscreen;
 541    struct nouveau_object *chan;
 542    struct nouveau_pushbuf *push;
 543    uint64_t value;
 544    uint32_t obj_class;
 545    int ret;
 546    unsigned i;
 547    union nouveau_bo_config mm_config;
 548
 549    switch (dev->chipset & ~0xf) {
 550    case 0xc0:
 551    case 0xd0:
 552    case 0xe0:
 553       break;
 554    default:
 555       return NULL;
 556    }
 557
 558    screen = CALLOC_STRUCT(nvc0_screen);
 559    if (!screen)
 560       return NULL;
 561    pscreen = &screen->base.base;
 562
 563    ret = nouveau_screen_init(&screen->base, dev);
 564    if (ret) {
 565       nvc0_screen_destroy(pscreen);
 566       return NULL;
 567    }
 568    chan = screen->base.channel;
 569    push = screen->base.pushbuf;
 570    push->user_priv = screen;
 571
 572    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 573       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 574    screen->base.sysmem_bindings |=
 575       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 576
 577    pscreen->destroy = nvc0_screen_destroy;
 578    pscreen->context_create = nvc0_create;
 579    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 580    pscreen->get_param = nvc0_screen_get_param;
 581    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 582    pscreen->get_paramf = nvc0_screen_get_paramf;
 583    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 584
 585    nvc0_screen_init_resource_functions(pscreen);
 586
 587    screen->base.base.get_video_param = nvc0_screen_get_video_param;
 588    screen->base.base.is_video_format_supported = nvc0_screen_video_supported;
 589
 590    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
 591                         &screen->fence.bo);
 592    if (ret)
 593       goto fail;
 594    nouveau_bo_map(screen->fence.bo, 0, NULL);
 595    screen->fence.map = screen->fence.bo->map;
 596    screen->base.fence.emit = nvc0_screen_fence_emit;
 597    screen->base.fence.update = nvc0_screen_fence_update;
 598
 599    switch (dev->chipset & 0xf0) {
 600    case 0xe0:
 601       obj_class = NVE4_P2MF_CLASS;
 602       break;
 603    default:
 604       obj_class = NVC0_M2MF_CLASS;
 605       break;
 606    }
 607    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 608                             &screen->m2mf);
 609    if (ret)
 610       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 611
 612    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 613    PUSH_DATA (push, screen->m2mf->oclass);
 614    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 615       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 616       PUSH_DATA (push, 0xa0b5);
 617    }
 618
 619    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 620                             &screen->eng2d);
 621    if (ret)
 622       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 623
 624    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 625    PUSH_DATA (push, screen->eng2d->oclass);
 626    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
 627    PUSH_DATA (push, 0);
 628    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 629    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
 630    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 631    PUSH_DATA (push, 0);
 632    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 633    PUSH_DATA (push, 0);
 634    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 635    PUSH_DATA (push, 0x3f);
 636    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 637    PUSH_DATA (push, 1);
 638
 639    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 640    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 641    PUSH_DATA (push, screen->fence.bo->offset + 16);
 642
 643    switch (dev->chipset & 0xf0) {
 644    case 0xe0:
 645       obj_class = NVE4_3D_CLASS;
 646       break;
 647    case 0xd0:
 648    case 0xc0:
 649    default:
 650       switch (dev->chipset) {
 651       case 0xd9:
 652       case 0xc8:
 653          obj_class = NVC8_3D_CLASS;
 654          break;
 655       case 0xc1:
 656          obj_class = NVC1_3D_CLASS;
 657          break;
 658       default:
 659          obj_class = NVC0_3D_CLASS;
 660          break;
 661       }
 662       break;
 663    }
 664    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 665                             &screen->eng3d);
 666    if (ret)
 667       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 668    screen->base.class_3d = obj_class;
 669
 670    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 671    PUSH_DATA (push, screen->eng3d->oclass);
 672
 673    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 674    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 675
 676    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 677       /* kill shaders after about 1 second (at 100 MHz) */
 678       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 679       PUSH_DATA (push, 0x17);
 680    }
 681
 682    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
 683    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 684    for (i = 0; i < 8; ++i)
 685            PUSH_DATA(push, dev->drm_version >= 0x01000101);
 686
 687    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 688    PUSH_DATA (push, 1);
 689
 690    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 691    PUSH_DATA (push, 0);
 692    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 693    PUSH_DATA (push, 0);
 694    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 695    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 696    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 697    PUSH_DATA (push, 0);
 698    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 699    PUSH_DATA (push, 1);
 700    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
 701    PUSH_DATA (push, 0);
 702    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 703    PUSH_DATA (push, 1);
 704    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 705    PUSH_DATA (push, 0);
 706    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 707       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
 708       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 709    } else {
 710       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 711       PUSH_DATA (push, 15);
 712    }
 713    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 714    PUSH_DATA (push, 8); /* 128 */
 715    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 716    PUSH_DATA (push, 1);
 717    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 718       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 719       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 720    }
 721
 722    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 723
 724    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 725                         &screen->text);
 726    if (ret)
 727       goto fail;
 728
 729    /* XXX: getting a page fault at the end of the code buffer every few
 730     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 731     */
 732    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 733
 734    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
 735                         &screen->uniform_bo);
 736    if (ret)
 737       goto fail;
 738
 739    for (i = 0; i < 5; ++i) {
 740       /* TIC and TSC entries for each unit (nve4+ only) */
 741       /* auxiliary constants (6 user clip planes, base instance id) */
 742       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 743       PUSH_DATA (push, 512);
 744       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 745       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
 746       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 747       PUSH_DATA (push, (15 << 4) | 1);
 748       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 749          unsigned j;
 750          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 751          PUSH_DATA (push, 0);
 752          for (j = 0; j < 8; ++j)
 753             PUSH_DATA(push, j);
 754       } else {
 755          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 756          PUSH_DATA (push, 0x54);
 757       }
 758    }
 759    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 760    PUSH_DATA (push, 0);
 761
 762    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 763    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 764    PUSH_DATA (push, 256);
 765    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 766    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 767    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 768    PUSH_DATA (push, 0);
 769    PUSH_DATAf(push, 0.0f);
 770    PUSH_DATAf(push, 0.0f);
 771    PUSH_DATAf(push, 0.0f);
 772    PUSH_DATAf(push, 0.0f);
 773    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 774    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 775    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
 776
 777    if (dev->drm_version >= 0x01000101) {
 778       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 779       if (ret) {
 780          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 781          goto fail;
 782       }
 783    } else {
 784       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 785          value = (8 << 8) | 4;
 786       else
 787          value = (16 << 8) | 4;
 788    }
 789    screen->mp_count = value >> 8;
 790    screen->mp_count_compute = screen->mp_count;
 791
 792    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
 793
 794    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 795    PUSH_DATAh(push, screen->text->offset);
 796    PUSH_DATA (push, screen->text->offset);
 797    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
 798    PUSH_DATAh(push, screen->tls->offset);
 799    PUSH_DATA (push, screen->tls->offset);
 800    PUSH_DATA (push, screen->tls->size >> 32);
 801    PUSH_DATA (push, screen->tls->size);
 802    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
 803    PUSH_DATA (push, 0);
 804    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
 805    PUSH_DATA (push, 0);
 806
 807    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
 808                         &screen->poly_cache);
 809    if (ret)
 810       goto fail;
 811
 812    BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 813    PUSH_DATAh(push, screen->poly_cache->offset);
 814    PUSH_DATA (push, screen->poly_cache->offset);
 815    PUSH_DATA (push, 3);
 816
 817    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
 818                         &screen->txc);
 819    if (ret)
 820       goto fail;
 821
 822    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
 823    PUSH_DATAh(push, screen->txc->offset);
 824    PUSH_DATA (push, screen->txc->offset);
 825    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 826
 827    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
 828    PUSH_DATAh(push, screen->txc->offset + 65536);
 829    PUSH_DATA (push, screen->txc->offset + 65536);
 830    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 831
 832    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
 833    PUSH_DATA (push, 0);
 834    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
 835    PUSH_DATA (push, 0);
 836    PUSH_DATA (push, 0);
 837    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 838    PUSH_DATA (push, 0x3f);
 839
 840    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
 841    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 842    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 843    for (i = 0; i < 8 * 2; ++i)
 844       PUSH_DATA(push, 0);
 845    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
 846    PUSH_DATA (push, 0);
 847    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
 848    PUSH_DATA (push, 0);
 849
 850    /* neither scissors, viewport nor stencil mask should affect clears */
 851    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
 852    PUSH_DATA (push, 0);
 853
 854    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
 855    PUSH_DATA (push, 1);
 856    BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
 857    PUSH_DATAf(push, 0.0f);
 858    PUSH_DATAf(push, 1.0f);
 859    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 860    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 861
 862    /* We use scissors instead of exact view volume clipping,
 863     * so they're always enabled.
 864     */
 865    BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
 866    PUSH_DATA (push, 1);
 867    PUSH_DATA (push, 8192 << 16);
 868    PUSH_DATA (push, 8192 << 16);
 869
 870 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 871
 872    i = 0;
 873    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
 874    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
 875    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 876    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
 877    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
 878    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 879    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 880
 881    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
 882    PUSH_DATA (push, 1);
 883    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
 884    PUSH_DATA (push, 1);
 885    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
 886    PUSH_DATA (push, 0x40);
 887    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
 888    PUSH_DATA (push, 0);
 889    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
 890    PUSH_DATA (push, 0x30);
 891    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
 892    PUSH_DATA (push, 3);
 893    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
 894    PUSH_DATA (push, 0x20);
 895    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
 896    PUSH_DATA (push, 0x00);
 897
 898    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
 899    PUSH_DATA (push, 0);
 900    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
 901    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
 902
 903    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
 904
 905    if (nvc0_screen_init_compute(screen))
 906       goto fail;
 907
 908    PUSH_KICK (push);
 909
 910    screen->tic.entries = CALLOC(4096, sizeof(void *));
 911    screen->tsc.entries = screen->tic.entries + 2048;
 912
 913    mm_config.nvc0.tile_mode = 0;
 914    mm_config.nvc0.memtype = 0xfe0;
 915    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
 916
 917    if (!nvc0_blitter_create(screen))
 918       goto fail;
 919
 920    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 921
 922    return pscreen;
 923
 924 fail:
 925    nvc0_screen_destroy(pscreen);
 926    return NULL;
 927 }
 928
 929 int
 930 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 931 {
 932    int i = screen->tic.next;
 933
 934    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 935       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 936
 937    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 938
 939    if (screen->tic.entries[i])
 940       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 941
 942    screen->tic.entries[i] = entry;
 943    return i;
 944 }
 945
 946 int
 947 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 948 {
 949    int i = screen->tsc.next;
 950
 951    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 952       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 953
 954    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 955
 956    if (screen->tsc.entries[i])
 957       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 958
 959    screen->tsc.entries[i] = entry;
 960    return i;
 961 }