2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
30 #include "nvc0_context.h"
31 #include "nvc0_screen.h"
33 #include "nvc0_graph_macros.h"
36 nvc0_screen_is_format_supported(struct pipe_screen
*pscreen
,
37 enum pipe_format format
,
38 enum pipe_texture_target target
,
39 unsigned sample_count
,
42 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
45 if (!util_format_is_supported(format
, bindings
))
49 case PIPE_FORMAT_R8G8B8A8_UNORM
:
50 case PIPE_FORMAT_R8G8B8X8_UNORM
:
51 /* HACK: GL requires equal formats for MS resolve and window is BGRA */
52 if (bindings
& PIPE_BIND_RENDER_TARGET
)
58 /* transfers & shared are always supported */
59 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
60 PIPE_BIND_TRANSFER_WRITE
|
63 return (nvc0_format_table
[format
].usage
& bindings
) == bindings
;
67 nvc0_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
69 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
72 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
73 return 16 * PIPE_SHADER_TYPES
; /* NOTE: should not count COMPUTE */
74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
81 case PIPE_CAP_MIN_TEXEL_OFFSET
:
83 case PIPE_CAP_MAX_TEXEL_OFFSET
:
85 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
86 case PIPE_CAP_TEXTURE_SWIZZLE
:
87 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
88 case PIPE_CAP_NPOT_TEXTURES
:
89 case PIPE_CAP_ANISOTROPIC_FILTER
:
90 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
92 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
93 return (class_3d
>= NVE4_3D_CLASS
) ? 1 : 0;
94 case PIPE_CAP_TWO_SIDED_STENCIL
:
95 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
96 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
97 case PIPE_CAP_POINT_SPRITE
:
101 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
103 case PIPE_CAP_MAX_RENDER_TARGETS
:
105 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
107 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
108 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
109 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
111 case PIPE_CAP_QUERY_TIMESTAMP
:
112 case PIPE_CAP_TIMER_QUERY
:
113 case PIPE_CAP_OCCLUSION_QUERY
:
114 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
116 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
118 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
119 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
121 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
122 case PIPE_CAP_INDEP_BLEND_ENABLE
:
123 case PIPE_CAP_INDEP_BLEND_FUNC
:
125 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
126 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
128 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
129 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
131 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
133 case PIPE_CAP_PRIMITIVE_RESTART
:
134 case PIPE_CAP_TGSI_INSTANCEID
:
135 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
136 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
137 case PIPE_CAP_CONDITIONAL_RENDER
:
138 case PIPE_CAP_TEXTURE_BARRIER
:
139 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
140 case PIPE_CAP_START_INSTANCE
:
142 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS
:
143 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
144 return 0; /* state trackers will know better */
145 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
146 case PIPE_CAP_USER_INDEX_BUFFERS
:
147 case PIPE_CAP_USER_VERTEX_BUFFERS
:
149 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
151 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
152 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
153 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
156 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
162 nvc0_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
163 enum pipe_shader_cap param
)
166 case PIPE_SHADER_VERTEX
:
168 case PIPE_SHADER_TESSELLATION_CONTROL:
169 case PIPE_SHADER_TESSELLATION_EVALUATION:
171 case PIPE_SHADER_GEOMETRY
:
172 case PIPE_SHADER_FRAGMENT
:
179 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
180 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
181 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
182 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
184 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
186 case PIPE_SHADER_CAP_MAX_INPUTS
:
187 if (shader
== PIPE_SHADER_VERTEX
)
189 if (shader
== PIPE_SHADER_FRAGMENT
)
190 return (0x200 + 0x20 + 0x80) / 16; /* generic + colors + TexCoords */
191 return (0x200 + 0x40 + 0x80) / 16; /* without 0x60 for per-patch inputs */
192 case PIPE_SHADER_CAP_MAX_CONSTS
:
194 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
195 return NVC0_MAX_PIPE_CONSTBUFS
;
196 case PIPE_SHADER_CAP_MAX_ADDRS
:
198 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
199 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
200 return shader
!= PIPE_SHADER_FRAGMENT
;
201 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
202 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
204 case PIPE_SHADER_CAP_MAX_PREDS
:
206 case PIPE_SHADER_CAP_MAX_TEMPS
:
207 return NVC0_CAP_MAX_PROGRAM_TEMPS
;
208 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
210 case PIPE_SHADER_CAP_SUBROUTINES
:
211 return 1; /* but inlining everything, we need function declarations */
212 case PIPE_SHADER_CAP_INTEGERS
:
214 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
215 return 16; /* would be 32 in linked (OpenGL-style) mode */
217 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
221 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
227 nvc0_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
230 case PIPE_CAPF_MAX_LINE_WIDTH
:
231 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
233 case PIPE_CAPF_MAX_POINT_WIDTH
:
235 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
237 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
239 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
242 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
248 nvc0_screen_destroy(struct pipe_screen
*pscreen
)
250 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
252 if (screen
->base
.fence
.current
) {
253 nouveau_fence_wait(screen
->base
.fence
.current
);
254 nouveau_fence_ref(NULL
, &screen
->base
.fence
.current
);
256 if (screen
->base
.pushbuf
)
257 screen
->base
.pushbuf
->user_priv
= NULL
;
259 FREE(screen
->blitctx
);
261 nouveau_bo_ref(NULL
, &screen
->text
);
262 nouveau_bo_ref(NULL
, &screen
->uniform_bo
);
263 nouveau_bo_ref(NULL
, &screen
->tls
);
264 nouveau_bo_ref(NULL
, &screen
->txc
);
265 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
266 nouveau_bo_ref(NULL
, &screen
->poly_cache
);
268 nouveau_heap_destroy(&screen
->lib_code
);
269 nouveau_heap_destroy(&screen
->text_heap
);
271 FREE(screen
->tic
.entries
);
273 nouveau_mm_destroy(screen
->mm_VRAM_fe0
);
275 nouveau_object_del(&screen
->eng3d
);
276 nouveau_object_del(&screen
->eng2d
);
277 nouveau_object_del(&screen
->m2mf
);
279 nouveau_screen_fini(&screen
->base
);
285 nvc0_graph_set_macro(struct nvc0_screen
*screen
, uint32_t m
, unsigned pos
,
286 unsigned size
, const uint32_t *data
)
288 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
292 BEGIN_NVC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_ID
), 2);
293 PUSH_DATA (push
, (m
- 0x3800) / 8);
294 PUSH_DATA (push
, pos
);
295 BEGIN_1IC0(push
, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS
), size
+ 1);
296 PUSH_DATA (push
, pos
);
297 PUSH_DATAp(push
, data
, size
);
303 nvc0_magic_3d_init(struct nouveau_pushbuf
*push
, uint16_t obj_class
)
305 BEGIN_NVC0(push
, SUBC_3D(0x10cc), 1);
306 PUSH_DATA (push
, 0xff);
307 BEGIN_NVC0(push
, SUBC_3D(0x10e0), 2);
308 PUSH_DATA (push
, 0xff);
309 PUSH_DATA (push
, 0xff);
310 BEGIN_NVC0(push
, SUBC_3D(0x10ec), 2);
311 PUSH_DATA (push
, 0xff);
312 PUSH_DATA (push
, 0xff);
313 BEGIN_NVC0(push
, SUBC_3D(0x074c), 1);
314 PUSH_DATA (push
, 0x3f);
316 BEGIN_NVC0(push
, SUBC_3D(0x16a8), 1);
317 PUSH_DATA (push
, (3 << 16) | 3);
318 BEGIN_NVC0(push
, SUBC_3D(0x1794), 1);
319 PUSH_DATA (push
, (2 << 16) | 2);
320 BEGIN_NVC0(push
, SUBC_3D(0x0de8), 1);
323 BEGIN_NVC0(push
, SUBC_3D(0x12ac), 1);
325 BEGIN_NVC0(push
, SUBC_3D(0x0218), 1);
326 PUSH_DATA (push
, 0x10);
327 BEGIN_NVC0(push
, SUBC_3D(0x10fc), 1);
328 PUSH_DATA (push
, 0x10);
329 BEGIN_NVC0(push
, SUBC_3D(0x1290), 1);
330 PUSH_DATA (push
, 0x10);
331 BEGIN_NVC0(push
, SUBC_3D(0x12d8), 2);
332 PUSH_DATA (push
, 0x10);
333 PUSH_DATA (push
, 0x10);
334 BEGIN_NVC0(push
, SUBC_3D(0x1140), 1);
335 PUSH_DATA (push
, 0x10);
336 BEGIN_NVC0(push
, SUBC_3D(0x1610), 1);
337 PUSH_DATA (push
, 0xe);
339 BEGIN_NVC0(push
, SUBC_3D(0x164c), 1);
340 PUSH_DATA (push
, 1 << 12);
341 BEGIN_NVC0(push
, SUBC_3D(0x030c), 1);
343 BEGIN_NVC0(push
, SUBC_3D(0x0300), 1);
346 BEGIN_NVC0(push
, SUBC_3D(0x02d0), 1);
347 PUSH_DATA (push
, 0x3fffff);
348 BEGIN_NVC0(push
, SUBC_3D(0x0fdc), 1);
350 BEGIN_NVC0(push
, SUBC_3D(0x19c0), 1);
352 BEGIN_NVC0(push
, SUBC_3D(0x075c), 1);
355 if (obj_class
>= NVE4_3D_CLASS
) {
356 BEGIN_NVC0(push
, SUBC_3D(0x07fc), 1);
360 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
361 * are supposed to do */
365 nvc0_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
367 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
368 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
370 /* we need to do it after possible flush in MARK_RING */
371 *sequence
= ++screen
->base
.fence
.sequence
;
373 BEGIN_NVC0(push
, NVC0_3D(QUERY_ADDRESS_HIGH
), 4);
374 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
375 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
376 PUSH_DATA (push
, *sequence
);
377 PUSH_DATA (push
, NVC0_3D_QUERY_GET_FENCE
| NVC0_3D_QUERY_GET_SHORT
|
378 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT
));
382 nvc0_screen_fence_update(struct pipe_screen
*pscreen
)
384 struct nvc0_screen
*screen
= nvc0_screen(pscreen
);
385 return screen
->fence
.map
[0];
388 #define FAIL_SCREEN_INIT(str, err) \
390 NOUVEAU_ERR(str, err); \
391 nvc0_screen_destroy(pscreen); \
396 nvc0_screen_create(struct nouveau_device
*dev
)
398 struct nvc0_screen
*screen
;
399 struct pipe_screen
*pscreen
;
400 struct nouveau_object
*chan
;
401 struct nouveau_pushbuf
*push
;
405 union nouveau_bo_config mm_config
;
407 switch (dev
->chipset
& ~0xf) {
416 screen
= CALLOC_STRUCT(nvc0_screen
);
419 pscreen
= &screen
->base
.base
;
421 ret
= nouveau_screen_init(&screen
->base
, dev
);
423 nvc0_screen_destroy(pscreen
);
426 chan
= screen
->base
.channel
;
427 push
= screen
->base
.pushbuf
;
428 push
->user_priv
= screen
;
430 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
431 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
432 screen
->base
.sysmem_bindings
|=
433 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
435 pscreen
->destroy
= nvc0_screen_destroy
;
436 pscreen
->context_create
= nvc0_create
;
437 pscreen
->is_format_supported
= nvc0_screen_is_format_supported
;
438 pscreen
->get_param
= nvc0_screen_get_param
;
439 pscreen
->get_shader_param
= nvc0_screen_get_shader_param
;
440 pscreen
->get_paramf
= nvc0_screen_get_paramf
;
442 nvc0_screen_init_resource_functions(pscreen
);
444 nouveau_screen_init_vdec(&screen
->base
);
446 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096, NULL
,
450 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
451 screen
->fence
.map
= screen
->fence
.bo
->map
;
452 screen
->base
.fence
.emit
= nvc0_screen_fence_emit
;
453 screen
->base
.fence
.update
= nvc0_screen_fence_update
;
455 switch (dev
->chipset
& 0xf0) {
457 obj_class
= NVE4_P2MF_CLASS
;
460 obj_class
= NVC0_M2MF_CLASS
;
463 ret
= nouveau_object_new(chan
, 0xbeef323f, obj_class
, NULL
, 0,
466 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret
);
468 BEGIN_NVC0(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
469 PUSH_DATA (push
, screen
->m2mf
->oclass
);
470 if (screen
->m2mf
->oclass
== NVE4_P2MF_CLASS
) {
471 BEGIN_NVC0(push
, SUBC_COPY(NV01_SUBCHAN_OBJECT
), 1);
472 PUSH_DATA (push
, 0xa0b5);
475 ret
= nouveau_object_new(chan
, 0xbeef902d, NVC0_2D_CLASS
, NULL
, 0,
478 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret
);
480 BEGIN_NVC0(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
481 PUSH_DATA (push
, screen
->eng2d
->oclass
);
482 BEGIN_NVC0(push
, NVC0_2D(OPERATION
), 1);
483 PUSH_DATA (push
, NVC0_2D_OPERATION_SRCCOPY
);
484 BEGIN_NVC0(push
, NVC0_2D(CLIP_ENABLE
), 1);
486 BEGIN_NVC0(push
, NVC0_2D(COLOR_KEY_ENABLE
), 1);
488 BEGIN_NVC0(push
, SUBC_2D(0x0884), 1);
489 PUSH_DATA (push
, 0x3f);
490 BEGIN_NVC0(push
, SUBC_2D(0x0888), 1);
493 BEGIN_NVC0(push
, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH
), 2);
494 PUSH_DATAh(push
, screen
->fence
.bo
->offset
+ 16);
495 PUSH_DATA (push
, screen
->fence
.bo
->offset
+ 16);
497 switch (dev
->chipset
& 0xf0) {
499 obj_class
= NVE4_3D_CLASS
;
504 switch (dev
->chipset
) {
507 obj_class
= NVC8_3D_CLASS
;
510 obj_class
= NVC1_3D_CLASS
;
513 obj_class
= NVC0_3D_CLASS
;
518 ret
= nouveau_object_new(chan
, 0xbeef003d, obj_class
, NULL
, 0,
521 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret
);
522 screen
->base
.class_3d
= obj_class
;
524 BEGIN_NVC0(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
525 PUSH_DATA (push
, screen
->eng3d
->oclass
);
527 BEGIN_NVC0(push
, NVC0_3D(COND_MODE
), 1);
528 PUSH_DATA (push
, NVC0_3D_COND_MODE_ALWAYS
);
530 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE
)) {
531 /* kill shaders after about 1 second (at 100 MHz) */
532 BEGIN_NVC0(push
, NVC0_3D(WATCHDOG_TIMER
), 1);
533 PUSH_DATA (push
, 0x17);
536 BEGIN_NVC0(push
, NVC0_3D(RT_CONTROL
), 1);
539 BEGIN_NVC0(push
, NVC0_3D(CSAA_ENABLE
), 1);
541 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_ENABLE
), 1);
543 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_MODE
), 1);
544 PUSH_DATA (push
, NVC0_3D_MULTISAMPLE_MODE_MS1
);
545 BEGIN_NVC0(push
, NVC0_3D(MULTISAMPLE_CTRL
), 1);
547 BEGIN_NVC0(push
, NVC0_3D(LINE_WIDTH_SEPARATE
), 1);
549 BEGIN_NVC0(push
, NVC0_3D(LINE_LAST_PIXEL
), 1);
551 BEGIN_NVC0(push
, NVC0_3D(BLEND_SEPARATE_ALPHA
), 1);
553 BEGIN_NVC0(push
, NVC0_3D(BLEND_ENABLE_COMMON
), 1);
555 if (screen
->eng3d
->oclass
< NVE4_3D_CLASS
) {
556 BEGIN_NVC0(push
, NVC0_3D(TEX_MISC
), 1);
557 PUSH_DATA (push
, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
559 BEGIN_NVC0(push
, NVE4_3D(TEX_CB_INDEX
), 1);
560 PUSH_DATA (push
, 15);
562 BEGIN_NVC0(push
, NVC0_3D(CALL_LIMIT_LOG
), 1);
563 PUSH_DATA (push
, 8); /* 128 */
564 BEGIN_NVC0(push
, NVC0_3D(ZCULL_STATCTRS_ENABLE
), 1);
566 if (screen
->eng3d
->oclass
>= NVC1_3D_CLASS
) {
567 BEGIN_NVC0(push
, NVC0_3D(CACHE_SPLIT
), 1);
568 PUSH_DATA (push
, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1
);
571 nvc0_magic_3d_init(push
, screen
->eng3d
->oclass
);
573 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 20, NULL
,
578 /* XXX: getting a page fault at the end of the code buffer every few
579 * launches, don't use the last 256 bytes to work around them - prefetch ?
581 nouveau_heap_init(&screen
->text_heap
, 0, (1 << 20) - 0x100);
583 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 12, 6 << 16, NULL
,
584 &screen
->uniform_bo
);
588 for (i
= 0; i
< 5; ++i
) {
589 /* TIC and TSC entries for each unit (nve4+ only) */
590 /* auxiliary constants (6 user clip planes, base instance id */
591 BEGIN_NVC0(push
, NVC0_3D(CB_SIZE
), 3);
592 PUSH_DATA (push
, 512);
593 PUSH_DATAh(push
, screen
->uniform_bo
->offset
+ (5 << 16) + (i
<< 9));
594 PUSH_DATA (push
, screen
->uniform_bo
->offset
+ (5 << 16) + (i
<< 9));
595 BEGIN_NVC0(push
, NVC0_3D(CB_BIND(i
)), 1);
596 PUSH_DATA (push
, (15 << 4) | 1);
597 if (screen
->eng3d
->oclass
>= NVE4_3D_CLASS
) {
599 BEGIN_1IC0(push
, NVC0_3D(CB_POS
), 9);
601 for (j
= 0; j
< 8; ++j
)
604 BEGIN_NVC0(push
, NVC0_3D(TEX_LIMITS(i
)), 1);
605 PUSH_DATA (push
, 0x54);
608 BEGIN_NVC0(push
, NVC0_3D(LINKED_TSC
), 1);
611 /* max MPs * max warps per MP (TODO: ask kernel) */
612 if (screen
->eng3d
->oclass
>= NVE4_3D_CLASS
)
613 screen
->tls_size
= 8 * 64;
615 screen
->tls_size
= 16 * 48;
616 screen
->tls_size
*= NVC0_CAP_MAX_PROGRAM_TEMPS
* 16;
617 screen
->tls_size
= align(screen
->tls_size
, 1 << 17);
619 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17,
620 screen
->tls_size
, NULL
, &screen
->tls
);
624 BEGIN_NVC0(push
, NVC0_3D(CODE_ADDRESS_HIGH
), 2);
625 PUSH_DATAh(push
, screen
->text
->offset
);
626 PUSH_DATA (push
, screen
->text
->offset
);
627 BEGIN_NVC0(push
, NVC0_3D(TEMP_ADDRESS_HIGH
), 4);
628 PUSH_DATAh(push
, screen
->tls
->offset
);
629 PUSH_DATA (push
, screen
->tls
->offset
);
630 PUSH_DATA (push
, screen
->tls_size
>> 32);
631 PUSH_DATA (push
, screen
->tls_size
);
632 BEGIN_NVC0(push
, NVC0_3D(WARP_TEMP_ALLOC
), 1);
634 BEGIN_NVC0(push
, NVC0_3D(LOCAL_BASE
), 1);
637 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 20, NULL
,
638 &screen
->poly_cache
);
642 BEGIN_NVC0(push
, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH
), 3);
643 PUSH_DATAh(push
, screen
->poly_cache
->offset
);
644 PUSH_DATA (push
, screen
->poly_cache
->offset
);
647 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 17, 1 << 17, NULL
,
652 BEGIN_NVC0(push
, NVC0_3D(TIC_ADDRESS_HIGH
), 3);
653 PUSH_DATAh(push
, screen
->txc
->offset
);
654 PUSH_DATA (push
, screen
->txc
->offset
);
655 PUSH_DATA (push
, NVC0_TIC_MAX_ENTRIES
- 1);
657 BEGIN_NVC0(push
, NVC0_3D(TSC_ADDRESS_HIGH
), 3);
658 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
659 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
660 PUSH_DATA (push
, NVC0_TSC_MAX_ENTRIES
- 1);
662 BEGIN_NVC0(push
, NVC0_3D(SCREEN_Y_CONTROL
), 1);
664 BEGIN_NVC0(push
, NVC0_3D(WINDOW_OFFSET_X
), 2);
667 BEGIN_NVC0(push
, NVC0_3D(ZCULL_REGION
), 1); /* deactivate ZCULL */
668 PUSH_DATA (push
, 0x3f);
670 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_MODE
), 1);
671 PUSH_DATA (push
, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
672 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
673 for (i
= 0; i
< 8 * 2; ++i
)
675 BEGIN_NVC0(push
, NVC0_3D(CLIP_RECTS_EN
), 1);
677 BEGIN_NVC0(push
, NVC0_3D(CLIPID_ENABLE
), 1);
680 /* neither scissors, viewport nor stencil mask should affect clears */
681 BEGIN_NVC0(push
, NVC0_3D(CLEAR_FLAGS
), 1);
684 BEGIN_NVC0(push
, NVC0_3D(VIEWPORT_TRANSFORM_EN
), 1);
686 BEGIN_NVC0(push
, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
687 PUSH_DATAf(push
, 0.0f
);
688 PUSH_DATAf(push
, 1.0f
);
689 BEGIN_NVC0(push
, NVC0_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
690 PUSH_DATA (push
, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
);
692 /* We use scissors instead of exact view volume clipping,
693 * so they're always enabled.
695 BEGIN_NVC0(push
, NVC0_3D(SCISSOR_ENABLE(0)), 3);
697 PUSH_DATA (push
, 8192 << 16);
698 PUSH_DATA (push
, 8192 << 16);
700 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
703 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE
, nvc0_9097_per_instance_bf
);
704 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES
, nvc0_9097_blend_enables
);
705 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT
, nvc0_9097_vertex_array_select
);
706 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT
, nvc0_9097_tep_select
);
707 MK_MACRO(NVC0_3D_MACRO_GP_SELECT
, nvc0_9097_gp_select
);
708 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT
, nvc0_9097_poly_mode_front
);
709 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK
, nvc0_9097_poly_mode_back
);
711 BEGIN_NVC0(push
, NVC0_3D(RASTERIZE_ENABLE
), 1);
713 BEGIN_NVC0(push
, NVC0_3D(RT_SEPARATE_FRAG_DATA
), 1);
715 BEGIN_NVC0(push
, NVC0_3D(MACRO_GP_SELECT
), 1);
716 PUSH_DATA (push
, 0x40);
717 BEGIN_NVC0(push
, NVC0_3D(LAYER
), 1);
719 BEGIN_NVC0(push
, NVC0_3D(MACRO_TEP_SELECT
), 1);
720 PUSH_DATA (push
, 0x30);
721 BEGIN_NVC0(push
, NVC0_3D(PATCH_VERTICES
), 1);
723 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(2)), 1);
724 PUSH_DATA (push
, 0x20);
725 BEGIN_NVC0(push
, NVC0_3D(SP_SELECT(0)), 1);
726 PUSH_DATA (push
, 0x00);
728 BEGIN_NVC0(push
, NVC0_3D(POINT_COORD_REPLACE
), 1);
730 BEGIN_NVC0(push
, NVC0_3D(POINT_RASTER_RULES
), 1);
731 PUSH_DATA (push
, NVC0_3D_POINT_RASTER_RULES_OGL
);
733 IMMED_NVC0(push
, NVC0_3D(EDGEFLAG
), 1);
735 BEGIN_NVC0(push
, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH
), 2);
736 PUSH_DATA (push
, 0xab);
737 PUSH_DATA (push
, 0x00000000);
741 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
742 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
744 mm_config
.nvc0
.tile_mode
= 0;
745 mm_config
.nvc0
.memtype
= 0xfe0;
746 screen
->mm_VRAM_fe0
= nouveau_mm_create(dev
, NOUVEAU_BO_VRAM
, &mm_config
);
748 if (!nvc0_blitctx_create(screen
))
751 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);
756 nvc0_screen_destroy(pscreen
);
761 nvc0_screen_tic_alloc(struct nvc0_screen
*screen
, void *entry
)
763 int i
= screen
->tic
.next
;
765 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
766 i
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
768 screen
->tic
.next
= (i
+ 1) & (NVC0_TIC_MAX_ENTRIES
- 1);
770 if (screen
->tic
.entries
[i
])
771 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
773 screen
->tic
.entries
[i
] = entry
;
778 nvc0_screen_tsc_alloc(struct nvc0_screen
*screen
, void *entry
)
780 int i
= screen
->tsc
.next
;
782 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
783 i
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
785 screen
->tsc
.next
= (i
+ 1) & (NVC0_TSC_MAX_ENTRIES
- 1);
787 if (screen
->tsc
.entries
[i
])
788 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
790 screen
->tsc
.entries
[i
] = entry
;