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gallium: add TGSI_SEMANTIC_TEXCOORD,PCOORD v3
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "nvc0_context.h"
31 #include "nvc0_screen.h"
32
33 #include "nvc0_graph_macros.h"
34
35 static boolean
36 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
37 enum pipe_format format,
38 enum pipe_texture_target target,
39 unsigned sample_count,
40 unsigned bindings)
41 {
42 if (sample_count > 8)
43 return FALSE;
44 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
45 return FALSE;
46
47 if (!util_format_is_supported(format, bindings))
48 return FALSE;
49
50 switch (format) {
51 case PIPE_FORMAT_R8G8B8A8_UNORM:
52 case PIPE_FORMAT_R8G8B8X8_UNORM:
53 /* HACK: GL requires equal formats for MS resolve and window is BGRA */
54 if (bindings & PIPE_BIND_RENDER_TARGET)
55 return FALSE;
56 default:
57 break;
58 }
59
60 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
61 if (util_format_get_blocksizebits(format) == 3 * 32)
62 return FALSE;
63
64 /* transfers & shared are always supported */
65 bindings &= ~(PIPE_BIND_TRANSFER_READ |
66 PIPE_BIND_TRANSFER_WRITE |
67 PIPE_BIND_SHARED);
68
69 return (nvc0_format_table[format].usage & bindings) == bindings;
70 }
71
72 static boolean
73 nvc0_screen_video_supported(struct pipe_screen *screen,
74 enum pipe_format format,
75 enum pipe_video_profile profile)
76 {
77 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
78 return format == PIPE_FORMAT_NV12;
79
80 return vl_video_buffer_is_format_supported(screen, format, profile);
81 }
82
83
84 static int
85 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
86 {
87 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
88
89 switch (param) {
90 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
91 return 16 * 5;
92 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
93 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
94 return 15;
95 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
96 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
97 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
98 return 2048;
99 case PIPE_CAP_MIN_TEXEL_OFFSET:
100 return -8;
101 case PIPE_CAP_MAX_TEXEL_OFFSET:
102 return 7;
103 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
104 case PIPE_CAP_TEXTURE_SWIZZLE:
105 case PIPE_CAP_TEXTURE_SHADOW_MAP:
106 case PIPE_CAP_NPOT_TEXTURES:
107 case PIPE_CAP_ANISOTROPIC_FILTER:
108 case PIPE_CAP_SEAMLESS_CUBE_MAP:
109 case PIPE_CAP_CUBE_MAP_ARRAY:
110 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
111 return 1;
112 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
113 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
114 case PIPE_CAP_TWO_SIDED_STENCIL:
115 case PIPE_CAP_DEPTH_CLIP_DISABLE:
116 case PIPE_CAP_POINT_SPRITE:
117 case PIPE_CAP_TGSI_TEXCOORD:
118 return 1;
119 case PIPE_CAP_SM3:
120 return 1;
121 case PIPE_CAP_GLSL_FEATURE_LEVEL:
122 return 150;
123 case PIPE_CAP_MAX_RENDER_TARGETS:
124 return 8;
125 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
126 return 1;
127 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
128 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
129 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
130 return 1;
131 case PIPE_CAP_QUERY_TIMESTAMP:
132 case PIPE_CAP_QUERY_TIME_ELAPSED:
133 case PIPE_CAP_OCCLUSION_QUERY:
134 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
135 return 1;
136 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
137 return 4;
138 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
139 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
140 return 128;
141 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
142 case PIPE_CAP_INDEP_BLEND_ENABLE:
143 case PIPE_CAP_INDEP_BLEND_FUNC:
144 return 1;
145 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
146 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
147 return 1;
148 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
149 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
150 return 0;
151 case PIPE_CAP_SHADER_STENCIL_EXPORT:
152 return 0;
153 case PIPE_CAP_PRIMITIVE_RESTART:
154 case PIPE_CAP_TGSI_INSTANCEID:
155 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
156 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
157 case PIPE_CAP_CONDITIONAL_RENDER:
158 case PIPE_CAP_TEXTURE_BARRIER:
159 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
160 case PIPE_CAP_START_INSTANCE:
161 return 1;
162 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
163 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
164 return 0; /* state trackers will know better */
165 case PIPE_CAP_USER_CONSTANT_BUFFERS:
166 case PIPE_CAP_USER_INDEX_BUFFERS:
167 case PIPE_CAP_USER_VERTEX_BUFFERS:
168 return 1;
169 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
170 return 256;
171 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
172 return 1; /* 256 for binding as RT, but that's not possible in GL */
173 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
174 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
175 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
176 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
177 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
178 case PIPE_CAP_TEXTURE_MULTISAMPLE:
179 return 0;
180 case PIPE_CAP_COMPUTE:
181 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
182 default:
183 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
184 return 0;
185 }
186 }
187
188 static int
189 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
190 enum pipe_shader_cap param)
191 {
192 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
193
194 switch (shader) {
195 case PIPE_SHADER_VERTEX:
196 /*
197 case PIPE_SHADER_TESSELLATION_CONTROL:
198 case PIPE_SHADER_TESSELLATION_EVALUATION:
199 */
200 case PIPE_SHADER_GEOMETRY:
201 case PIPE_SHADER_FRAGMENT:
202 break;
203 case PIPE_SHADER_COMPUTE:
204 if (class_3d < NVE4_3D_CLASS)
205 return 0;
206 break;
207 default:
208 return 0;
209 }
210
211 switch (param) {
212 case PIPE_SHADER_CAP_PREFERRED_IR:
213 return PIPE_SHADER_IR_TGSI;
214 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
215 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
216 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
217 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
218 return 16384;
219 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
220 return 16;
221 case PIPE_SHADER_CAP_MAX_INPUTS:
222 if (shader == PIPE_SHADER_VERTEX)
223 return 32;
224 if (shader == PIPE_SHADER_FRAGMENT)
225 return (0x200 + 0x20 + 0x80) / 16; /* generic + colors + TexCoords */
226 return (0x200 + 0x40 + 0x80) / 16; /* without 0x60 for per-patch inputs */
227 case PIPE_SHADER_CAP_MAX_CONSTS:
228 return 65536 / 16;
229 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
230 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
231 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
232 return NVC0_MAX_PIPE_CONSTBUFS;
233 case PIPE_SHADER_CAP_MAX_ADDRS:
234 return 1;
235 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
236 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
237 return shader != PIPE_SHADER_FRAGMENT;
238 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
239 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
240 return 1;
241 case PIPE_SHADER_CAP_MAX_PREDS:
242 return 0;
243 case PIPE_SHADER_CAP_MAX_TEMPS:
244 return NVC0_CAP_MAX_PROGRAM_TEMPS;
245 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
246 return 1;
247 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
248 return 0;
249 case PIPE_SHADER_CAP_SUBROUTINES:
250 return 1;
251 case PIPE_SHADER_CAP_INTEGERS:
252 return 1;
253 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
254 return 16; /* would be 32 in linked (OpenGL-style) mode */
255 /*
256 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
257 return 32;
258 */
259 default:
260 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
261 return 0;
262 }
263 }
264
265 static float
266 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
267 {
268 switch (param) {
269 case PIPE_CAPF_MAX_LINE_WIDTH:
270 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
271 return 10.0f;
272 case PIPE_CAPF_MAX_POINT_WIDTH:
273 return 63.0f;
274 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
275 return 63.375f;
276 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
277 return 16.0f;
278 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
279 return 15.0f;
280 default:
281 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
282 return 0.0f;
283 }
284 }
285
286 static int
287 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
288 enum pipe_compute_cap param, void *data)
289 {
290 uint64_t *data64 = (uint64_t *)data;
291 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
292
293 switch (param) {
294 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
295 data64[0] = 3;
296 return 8;
297 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
298 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
299 data64[1] = 65535;
300 data64[2] = 65535;
301 return 24;
302 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
303 data64[0] = 1024;
304 data64[1] = 1024;
305 data64[2] = 64;
306 return 24;
307 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
308 data64[0] = 1024;
309 return 8;
310 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
311 data64[0] = (uint64_t)1 << 40;
312 return 8;
313 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
314 data64[0] = 48 << 10;
315 return 8;
316 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
317 data64[0] = 512 << 10;
318 return 8;
319 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
320 data64[0] = 4096;
321 return 8;
322 default:
323 return 0;
324 }
325 }
326
327 static void
328 nvc0_screen_destroy(struct pipe_screen *pscreen)
329 {
330 struct nvc0_screen *screen = nvc0_screen(pscreen);
331
332 if (screen->base.fence.current) {
333 nouveau_fence_wait(screen->base.fence.current);
334 nouveau_fence_ref(NULL, &screen->base.fence.current);
335 }
336 if (screen->base.pushbuf)
337 screen->base.pushbuf->user_priv = NULL;
338
339 if (screen->blitter)
340 nvc0_blitter_destroy(screen);
341
342 nouveau_bo_ref(NULL, &screen->text);
343 nouveau_bo_ref(NULL, &screen->uniform_bo);
344 nouveau_bo_ref(NULL, &screen->tls);
345 nouveau_bo_ref(NULL, &screen->txc);
346 nouveau_bo_ref(NULL, &screen->fence.bo);
347 nouveau_bo_ref(NULL, &screen->poly_cache);
348 nouveau_bo_ref(NULL, &screen->parm);
349
350 nouveau_heap_destroy(&screen->lib_code);
351 nouveau_heap_destroy(&screen->text_heap);
352
353 FREE(screen->tic.entries);
354
355 nouveau_mm_destroy(screen->mm_VRAM_fe0);
356
357 nouveau_object_del(&screen->eng3d);
358 nouveau_object_del(&screen->eng2d);
359 nouveau_object_del(&screen->m2mf);
360
361 nouveau_screen_fini(&screen->base);
362
363 FREE(screen);
364 }
365
366 static int
367 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
368 unsigned size, const uint32_t *data)
369 {
370 struct nouveau_pushbuf *push = screen->base.pushbuf;
371
372 size /= 4;
373
374 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
375 PUSH_DATA (push, (m - 0x3800) / 8);
376 PUSH_DATA (push, pos);
377 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
378 PUSH_DATA (push, pos);
379 PUSH_DATAp(push, data, size);
380
381 return pos + size;
382 }
383
384 static void
385 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
386 {
387 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
388 PUSH_DATA (push, 0xff);
389 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
390 PUSH_DATA (push, 0xff);
391 PUSH_DATA (push, 0xff);
392 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
393 PUSH_DATA (push, 0xff);
394 PUSH_DATA (push, 0xff);
395 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
396 PUSH_DATA (push, 0x3f);
397
398 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
399 PUSH_DATA (push, (3 << 16) | 3);
400 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
401 PUSH_DATA (push, (2 << 16) | 2);
402 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
403 PUSH_DATA (push, 1);
404
405 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
406 PUSH_DATA (push, 0);
407 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
408 PUSH_DATA (push, 0x10);
409 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
410 PUSH_DATA (push, 0x10);
411 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
412 PUSH_DATA (push, 0x10);
413 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
414 PUSH_DATA (push, 0x10);
415 PUSH_DATA (push, 0x10);
416 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
417 PUSH_DATA (push, 0x10);
418 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
419 PUSH_DATA (push, 0xe);
420
421 BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
422 PUSH_DATA (push, 1 << 12);
423 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
424 PUSH_DATA (push, 0);
425 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
426 PUSH_DATA (push, 3);
427
428 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
429 PUSH_DATA (push, 0x3fffff);
430 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
431 PUSH_DATA (push, 1);
432 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
433 PUSH_DATA (push, 1);
434 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
435 PUSH_DATA (push, 3);
436
437 if (obj_class >= NVE4_3D_CLASS) {
438 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
439 PUSH_DATA (push, 1);
440 }
441
442 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
443 * are supposed to do */
444 }
445
446 static void
447 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
448 {
449 struct nvc0_screen *screen = nvc0_screen(pscreen);
450 struct nouveau_pushbuf *push = screen->base.pushbuf;
451
452 /* we need to do it after possible flush in MARK_RING */
453 *sequence = ++screen->base.fence.sequence;
454
455 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
456 PUSH_DATAh(push, screen->fence.bo->offset);
457 PUSH_DATA (push, screen->fence.bo->offset);
458 PUSH_DATA (push, *sequence);
459 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
460 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
461 }
462
463 static u32
464 nvc0_screen_fence_update(struct pipe_screen *pscreen)
465 {
466 struct nvc0_screen *screen = nvc0_screen(pscreen);
467 return screen->fence.map[0];
468 }
469
470 static int
471 nvc0_screen_init_compute(struct nvc0_screen *screen)
472 {
473 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
474
475 switch (screen->base.device->chipset & 0xf0) {
476 case 0xc0:
477 case 0xd0:
478 return 0;
479 case 0xe0:
480 case 0xf0:
481 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
482 default:
483 return -1;
484 }
485 }
486
487 #define FAIL_SCREEN_INIT(str, err) \
488 do { \
489 NOUVEAU_ERR(str, err); \
490 nvc0_screen_destroy(pscreen); \
491 return NULL; \
492 } while(0)
493
494 struct pipe_screen *
495 nvc0_screen_create(struct nouveau_device *dev)
496 {
497 struct nvc0_screen *screen;
498 struct pipe_screen *pscreen;
499 struct nouveau_object *chan;
500 struct nouveau_pushbuf *push;
501 uint32_t obj_class;
502 int ret;
503 unsigned i;
504 union nouveau_bo_config mm_config;
505
506 switch (dev->chipset & ~0xf) {
507 case 0xc0:
508 case 0xd0:
509 case 0xe0:
510 break;
511 default:
512 return NULL;
513 }
514
515 screen = CALLOC_STRUCT(nvc0_screen);
516 if (!screen)
517 return NULL;
518 pscreen = &screen->base.base;
519
520 ret = nouveau_screen_init(&screen->base, dev);
521 if (ret) {
522 nvc0_screen_destroy(pscreen);
523 return NULL;
524 }
525 chan = screen->base.channel;
526 push = screen->base.pushbuf;
527 push->user_priv = screen;
528
529 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
530 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
531 screen->base.sysmem_bindings |=
532 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
533
534 pscreen->destroy = nvc0_screen_destroy;
535 pscreen->context_create = nvc0_create;
536 pscreen->is_format_supported = nvc0_screen_is_format_supported;
537 pscreen->get_param = nvc0_screen_get_param;
538 pscreen->get_shader_param = nvc0_screen_get_shader_param;
539 pscreen->get_paramf = nvc0_screen_get_paramf;
540
541 nvc0_screen_init_resource_functions(pscreen);
542
543 screen->base.base.get_video_param = nvc0_screen_get_video_param;
544 screen->base.base.is_video_format_supported = nvc0_screen_video_supported;
545
546 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
547 &screen->fence.bo);
548 if (ret)
549 goto fail;
550 nouveau_bo_map(screen->fence.bo, 0, NULL);
551 screen->fence.map = screen->fence.bo->map;
552 screen->base.fence.emit = nvc0_screen_fence_emit;
553 screen->base.fence.update = nvc0_screen_fence_update;
554
555 switch (dev->chipset & 0xf0) {
556 case 0xe0:
557 obj_class = NVE4_P2MF_CLASS;
558 break;
559 default:
560 obj_class = NVC0_M2MF_CLASS;
561 break;
562 }
563 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
564 &screen->m2mf);
565 if (ret)
566 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
567
568 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
569 PUSH_DATA (push, screen->m2mf->oclass);
570 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
571 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
572 PUSH_DATA (push, 0xa0b5);
573 }
574
575 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
576 &screen->eng2d);
577 if (ret)
578 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
579
580 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
581 PUSH_DATA (push, screen->eng2d->oclass);
582 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
583 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
584 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
585 PUSH_DATA (push, 0);
586 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
587 PUSH_DATA (push, 0);
588 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
589 PUSH_DATA (push, 0x3f);
590 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
591 PUSH_DATA (push, 1);
592
593 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
594 PUSH_DATAh(push, screen->fence.bo->offset + 16);
595 PUSH_DATA (push, screen->fence.bo->offset + 16);
596
597 switch (dev->chipset & 0xf0) {
598 case 0xe0:
599 obj_class = NVE4_3D_CLASS;
600 break;
601 case 0xd0:
602 case 0xc0:
603 default:
604 switch (dev->chipset) {
605 case 0xd9:
606 case 0xc8:
607 obj_class = NVC8_3D_CLASS;
608 break;
609 case 0xc1:
610 obj_class = NVC1_3D_CLASS;
611 break;
612 default:
613 obj_class = NVC0_3D_CLASS;
614 break;
615 }
616 break;
617 }
618 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
619 &screen->eng3d);
620 if (ret)
621 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
622 screen->base.class_3d = obj_class;
623
624 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
625 PUSH_DATA (push, screen->eng3d->oclass);
626
627 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
628 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
629
630 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
631 /* kill shaders after about 1 second (at 100 MHz) */
632 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
633 PUSH_DATA (push, 0x17);
634 }
635
636 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
637 PUSH_DATA (push, 1);
638
639 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
640 PUSH_DATA (push, 0);
641 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
642 PUSH_DATA (push, 0);
643 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
644 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
645 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
646 PUSH_DATA (push, 0);
647 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
648 PUSH_DATA (push, 1);
649 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
650 PUSH_DATA (push, 0);
651 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
652 PUSH_DATA (push, 1);
653 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
654 PUSH_DATA (push, 0);
655 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
656 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
657 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
658 } else {
659 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
660 PUSH_DATA (push, 15);
661 }
662 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
663 PUSH_DATA (push, 8); /* 128 */
664 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
665 PUSH_DATA (push, 1);
666 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
667 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
668 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
669 }
670
671 nvc0_magic_3d_init(push, screen->eng3d->oclass);
672
673 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
674 &screen->text);
675 if (ret)
676 goto fail;
677
678 /* XXX: getting a page fault at the end of the code buffer every few
679 * launches, don't use the last 256 bytes to work around them - prefetch ?
680 */
681 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
682
683 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
684 &screen->uniform_bo);
685 if (ret)
686 goto fail;
687
688 for (i = 0; i < 5; ++i) {
689 /* TIC and TSC entries for each unit (nve4+ only) */
690 /* auxiliary constants (6 user clip planes, base instance id) */
691 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
692 PUSH_DATA (push, 512);
693 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
694 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
695 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
696 PUSH_DATA (push, (15 << 4) | 1);
697 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
698 unsigned j;
699 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
700 PUSH_DATA (push, 0);
701 for (j = 0; j < 8; ++j)
702 PUSH_DATA(push, j);
703 } else {
704 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
705 PUSH_DATA (push, 0x54);
706 }
707 }
708 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
709 PUSH_DATA (push, 0);
710
711 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
712 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
713 PUSH_DATA (push, 256);
714 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
715 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
716 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
717 PUSH_DATA (push, 0);
718 PUSH_DATAf(push, 0.0f);
719 PUSH_DATAf(push, 0.0f);
720 PUSH_DATAf(push, 0.0f);
721 PUSH_DATAf(push, 0.0f);
722 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
723 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
724 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
725
726 /* max MPs * max warps per MP (TODO: ask kernel) */
727 if (screen->eng3d->oclass >= NVE4_3D_CLASS)
728 screen->tls_size = 8 * 64 * 32;
729 else
730 screen->tls_size = 16 * 48 * 32;
731 screen->tls_size *= NVC0_CAP_MAX_PROGRAM_TEMPS * 16;
732 screen->tls_size = align(screen->tls_size, 1 << 17);
733
734 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
735 screen->tls_size, NULL, &screen->tls);
736 if (ret)
737 goto fail;
738
739 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
740 PUSH_DATAh(push, screen->text->offset);
741 PUSH_DATA (push, screen->text->offset);
742 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
743 PUSH_DATAh(push, screen->tls->offset);
744 PUSH_DATA (push, screen->tls->offset);
745 PUSH_DATA (push, screen->tls_size >> 32);
746 PUSH_DATA (push, screen->tls_size);
747 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
748 PUSH_DATA (push, 0);
749 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
750 PUSH_DATA (push, 0);
751
752 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
753 &screen->poly_cache);
754 if (ret)
755 goto fail;
756
757 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
758 PUSH_DATAh(push, screen->poly_cache->offset);
759 PUSH_DATA (push, screen->poly_cache->offset);
760 PUSH_DATA (push, 3);
761
762 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
763 &screen->txc);
764 if (ret)
765 goto fail;
766
767 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
768 PUSH_DATAh(push, screen->txc->offset);
769 PUSH_DATA (push, screen->txc->offset);
770 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
771
772 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
773 PUSH_DATAh(push, screen->txc->offset + 65536);
774 PUSH_DATA (push, screen->txc->offset + 65536);
775 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
776
777 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
778 PUSH_DATA (push, 0);
779 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
780 PUSH_DATA (push, 0);
781 PUSH_DATA (push, 0);
782 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
783 PUSH_DATA (push, 0x3f);
784
785 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
786 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
787 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
788 for (i = 0; i < 8 * 2; ++i)
789 PUSH_DATA(push, 0);
790 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
791 PUSH_DATA (push, 0);
792 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
793 PUSH_DATA (push, 0);
794
795 /* neither scissors, viewport nor stencil mask should affect clears */
796 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
797 PUSH_DATA (push, 0);
798
799 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
800 PUSH_DATA (push, 1);
801 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
802 PUSH_DATAf(push, 0.0f);
803 PUSH_DATAf(push, 1.0f);
804 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
805 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
806
807 /* We use scissors instead of exact view volume clipping,
808 * so they're always enabled.
809 */
810 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
811 PUSH_DATA (push, 1);
812 PUSH_DATA (push, 8192 << 16);
813 PUSH_DATA (push, 8192 << 16);
814
815 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
816
817 i = 0;
818 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
819 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
820 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
821 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
822 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
823 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
824 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
825
826 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
827 PUSH_DATA (push, 1);
828 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
829 PUSH_DATA (push, 1);
830 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
831 PUSH_DATA (push, 0x40);
832 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
833 PUSH_DATA (push, 0);
834 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
835 PUSH_DATA (push, 0x30);
836 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
837 PUSH_DATA (push, 3);
838 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
839 PUSH_DATA (push, 0x20);
840 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
841 PUSH_DATA (push, 0x00);
842
843 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
844 PUSH_DATA (push, 0);
845 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
846 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
847
848 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
849
850 if (nvc0_screen_init_compute(screen))
851 goto fail;
852
853 PUSH_KICK (push);
854
855 screen->tic.entries = CALLOC(4096, sizeof(void *));
856 screen->tsc.entries = screen->tic.entries + 2048;
857
858 mm_config.nvc0.tile_mode = 0;
859 mm_config.nvc0.memtype = 0xfe0;
860 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
861
862 if (!nvc0_blitter_create(screen))
863 goto fail;
864
865 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
866
867 return pscreen;
868
869 fail:
870 nvc0_screen_destroy(pscreen);
871 return NULL;
872 }
873
874 int
875 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
876 {
877 int i = screen->tic.next;
878
879 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
880 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
881
882 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
883
884 if (screen->tic.entries[i])
885 nv50_tic_entry(screen->tic.entries[i])->id = -1;
886
887 screen->tic.entries[i] = entry;
888 return i;
889 }
890
891 int
892 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
893 {
894 int i = screen->tsc.next;
895
896 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
897 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
898
899 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
900
901 if (screen->tsc.entries[i])
902 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
903
904 screen->tsc.entries[i] = entry;
905 return i;
906 }