src/gallium/drivers/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29
  30 #include "nvc0_context.h"
  31 #include "nvc0_screen.h"
  32
  33 #include "nouveau/nv_object.xml.h"
  34 #include "nvc0_graph_macros.h"
  35
  36 static boolean
  37 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  38                                 enum pipe_format format,
  39                                 enum pipe_texture_target target,
  40                                 unsigned sample_count,
  41                                 unsigned bindings)
  42 {
  43    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  44       return FALSE;
  45
  46    if (!util_format_is_supported(format, bindings))
  47       return FALSE;
  48
  49    switch (format) {
  50    case PIPE_FORMAT_R8G8B8A8_UNORM:
  51    case PIPE_FORMAT_R8G8B8X8_UNORM:
  52       /* HACK: GL requires equal formats for MS resolve and window is BGRA */
  53       if (bindings & PIPE_BIND_RENDER_TARGET)
  54          return FALSE;
  55    default:
  56       break;
  57    }
  58
  59    /* transfers & shared are always supported */
  60    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  61                  PIPE_BIND_TRANSFER_WRITE |
  62                  PIPE_BIND_SHARED);
  63
  64    return (nvc0_format_table[format].usage & bindings) == bindings;
  65 }
  66
  67 static int
  68 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  69 {
  70    switch (param) {
  71    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  72       return 16 * PIPE_SHADER_TYPES; /* NOTE: should not count COMPUTE */
  73    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  74    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  75       return 15;
  76    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  77       return 12;
  78    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  79       return 2048;
  80    case PIPE_CAP_MIN_TEXEL_OFFSET:
  81       return -8;
  82    case PIPE_CAP_MAX_TEXEL_OFFSET:
  83       return 7;
  84    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  85    case PIPE_CAP_TEXTURE_SWIZZLE:
  86    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  87    case PIPE_CAP_NPOT_TEXTURES:
  88    case PIPE_CAP_ANISOTROPIC_FILTER:
  89    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  90       return 1;
  91    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  92       return 0;
  93    case PIPE_CAP_TWO_SIDED_STENCIL:
  94    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  95    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  96    case PIPE_CAP_POINT_SPRITE:
  97       return 1;
  98    case PIPE_CAP_SM3:
  99       return 1;
 100    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 101       return 150;
 102    case PIPE_CAP_MAX_RENDER_TARGETS:
 103       return 8;
 104    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 105    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 106    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 107       return 1;
 108    case PIPE_CAP_TIMER_QUERY:
 109    case PIPE_CAP_OCCLUSION_QUERY:
 110    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 111       return 1;
 112    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 113       return 4;
 114    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 115    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 116       return 128;
 117    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 118    case PIPE_CAP_INDEP_BLEND_ENABLE:
 119    case PIPE_CAP_INDEP_BLEND_FUNC:
 120       return 1;
 121    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 122    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 123       return 1;
 124    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 125    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 126       return 0;
 127    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 128       return 0;
 129    case PIPE_CAP_PRIMITIVE_RESTART:
 130    case PIPE_CAP_TGSI_INSTANCEID:
 131    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 132    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 133    case PIPE_CAP_CONDITIONAL_RENDER:
 134    case PIPE_CAP_TEXTURE_BARRIER:
 135    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 136       return 1;
 137    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 138    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 139       return 0; /* state trackers will know better */
 140    default:
 141       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 142       return 0;
 143    }
 144 }
 145
 146 static int
 147 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 148                              enum pipe_shader_cap param)
 149 {
 150    switch (shader) {
 151    case PIPE_SHADER_VERTEX:
 152       /*
 153    case PIPE_SHADER_TESSELLATION_CONTROL:
 154    case PIPE_SHADER_TESSELLATION_EVALUATION:
 155       */
 156    case PIPE_SHADER_GEOMETRY:
 157    case PIPE_SHADER_FRAGMENT:
 158       break;
 159    default:
 160       return 0;
 161    }
 162
 163    switch (param) {
 164    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 165    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 166    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 167    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 168       return 16384;
 169    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 170       return 16;
 171    case PIPE_SHADER_CAP_MAX_INPUTS:
 172       if (shader == PIPE_SHADER_VERTEX)
 173          return 32;
 174       if (shader == PIPE_SHADER_FRAGMENT)
 175          return (0x200 + 0x20 + 0x80) / 16; /* generic + colors + TexCoords */
 176       return (0x200 + 0x40 + 0x80) / 16; /* without 0x60 for per-patch inputs */
 177    case PIPE_SHADER_CAP_MAX_CONSTS:
 178       return 65536 / 16;
 179    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 180       return 14;
 181    case PIPE_SHADER_CAP_MAX_ADDRS:
 182       return 1;
 183    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 184    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 185       return shader != PIPE_SHADER_FRAGMENT;
 186    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 187    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 188       return 1;
 189    case PIPE_SHADER_CAP_MAX_PREDS:
 190       return 0;
 191    case PIPE_SHADER_CAP_MAX_TEMPS:
 192       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 193    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 194       return 1;
 195    case PIPE_SHADER_CAP_SUBROUTINES:
 196       return 1; /* but inlining everything, we need function declarations */
 197    case PIPE_SHADER_CAP_INTEGERS:
 198       return 1;
 199    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 200       return 16; /* would be 32 in linked (OpenGL-style) mode */
 201       /*
 202    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
 203       return 32;
 204       */
 205    default:
 206       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 207       return 0;
 208    }
 209 }
 210
 211 static float
 212 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 213 {
 214    switch (param) {
 215    case PIPE_CAPF_MAX_LINE_WIDTH:
 216    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 217       return 10.0f;
 218    case PIPE_CAPF_MAX_POINT_WIDTH:
 219       return 63.0f;
 220    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 221       return 63.375f;
 222    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 223       return 16.0f;
 224    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 225       return 15.0f;
 226    default:
 227       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 228       return 0.0f;
 229    }
 230 }
 231
 232 static void
 233 nvc0_screen_destroy(struct pipe_screen *pscreen)
 234 {
 235    struct nvc0_screen *screen = nvc0_screen(pscreen);
 236
 237    if (screen->base.fence.current) {
 238       nouveau_fence_wait(screen->base.fence.current);
 239       nouveau_fence_ref(NULL, &screen->base.fence.current);
 240    }
 241    if (screen->base.channel)
 242       screen->base.channel->user_private = NULL;
 243
 244    if (screen->blitctx)
 245       FREE(screen->blitctx);
 246
 247    nouveau_bo_ref(NULL, &screen->text);
 248    nouveau_bo_ref(NULL, &screen->tls);
 249    nouveau_bo_ref(NULL, &screen->txc);
 250    nouveau_bo_ref(NULL, &screen->fence.bo);
 251    nouveau_bo_ref(NULL, &screen->vfetch_cache);
 252
 253    nouveau_resource_destroy(&screen->lib_code);
 254    nouveau_resource_destroy(&screen->text_heap);
 255
 256    if (screen->tic.entries)
 257       FREE(screen->tic.entries);
 258
 259    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 260
 261    nouveau_grobj_free(&screen->fermi);
 262    nouveau_grobj_free(&screen->eng2d);
 263    nouveau_grobj_free(&screen->m2mf);
 264
 265    nouveau_screen_fini(&screen->base);
 266
 267    FREE(screen);
 268 }
 269
 270 static int
 271 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 272                      unsigned size, const uint32_t *data)
 273 {
 274    struct nouveau_channel *chan = screen->base.channel;
 275
 276    size /= 4;
 277
 278    BEGIN_RING(chan, RING_3D_(NVC0_GRAPH_MACRO_ID), 2);
 279    OUT_RING  (chan, (m - 0x3800) / 8);
 280    OUT_RING  (chan, pos);
 281    BEGIN_RING_1I(chan, RING_3D_(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 282    OUT_RING  (chan, pos);
 283    OUT_RINGp (chan, data, size);
 284
 285    return pos + size;
 286 }
 287
 288 static void
 289 nvc0_magic_3d_init(struct nouveau_channel *chan)
 290 {
 291    BEGIN_RING(chan, RING_3D_(0x10cc), 1);
 292    OUT_RING  (chan, 0xff);
 293    BEGIN_RING(chan, RING_3D_(0x10e0), 2);
 294    OUT_RING(chan, 0xff);
 295    OUT_RING(chan, 0xff);
 296    BEGIN_RING(chan, RING_3D_(0x10ec), 2);
 297    OUT_RING(chan, 0xff);
 298    OUT_RING(chan, 0xff);
 299    BEGIN_RING(chan, RING_3D_(0x074c), 1);
 300    OUT_RING  (chan, 0x3f);
 301
 302    BEGIN_RING(chan, RING_3D_(0x16a8), 1);
 303    OUT_RING  (chan, (3 << 16) | 3);
 304    BEGIN_RING(chan, RING_3D_(0x1794), 1);
 305    OUT_RING  (chan, (2 << 16) | 2);
 306    BEGIN_RING(chan, RING_3D_(0x0de8), 1);
 307    OUT_RING  (chan, 1);
 308
 309 #if 0 /* software method */
 310    BEGIN_RING(chan, RING_3D_(0x1528), 1); /* MP poke */
 311    OUT_RING  (chan, 0);
 312 #endif
 313
 314    BEGIN_RING(chan, RING_3D_(0x12ac), 1);
 315    OUT_RING  (chan, 0);
 316    BEGIN_RING(chan, RING_3D_(0x0218), 1);
 317    OUT_RING  (chan, 0x10);
 318    BEGIN_RING(chan, RING_3D_(0x10fc), 1);
 319    OUT_RING  (chan, 0x10);
 320    BEGIN_RING(chan, RING_3D_(0x1290), 1);
 321    OUT_RING  (chan, 0x10);
 322    BEGIN_RING(chan, RING_3D_(0x12d8), 2);
 323    OUT_RING  (chan, 0x10);
 324    OUT_RING  (chan, 0x10);
 325    BEGIN_RING(chan, RING_3D_(0x06d4), 1);
 326    OUT_RING  (chan, 8);
 327    BEGIN_RING(chan, RING_3D_(0x1140), 1);
 328    OUT_RING  (chan, 0x10);
 329    BEGIN_RING(chan, RING_3D_(0x1610), 1);
 330    OUT_RING  (chan, 0xe);
 331
 332    BEGIN_RING(chan, RING_3D_(0x164c), 1);
 333    OUT_RING  (chan, 1 << 12);
 334    BEGIN_RING(chan, RING_3D_(0x151c), 1);
 335    OUT_RING  (chan, 1);
 336    BEGIN_RING(chan, RING_3D_(0x030c), 1);
 337    OUT_RING  (chan, 0);
 338    BEGIN_RING(chan, RING_3D_(0x0300), 1);
 339    OUT_RING  (chan, 3);
 340 #if 0 /* software method */
 341    BEGIN_RING(chan, RING_3D_(0x1280), 1); /* PGRAPH poke */
 342    OUT_RING  (chan, 0);
 343 #endif
 344    BEGIN_RING(chan, RING_3D_(0x02d0), 1);
 345    OUT_RING  (chan, 0x1f40);
 346    BEGIN_RING(chan, RING_3D_(0x00fdc), 1);
 347    OUT_RING  (chan, 1);
 348    BEGIN_RING(chan, RING_3D_(0x19c0), 1);
 349    OUT_RING  (chan, 1);
 350    BEGIN_RING(chan, RING_3D_(0x075c), 1);
 351    OUT_RING  (chan, 3);
 352 }
 353
 354 static void
 355 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 356 {
 357    struct nvc0_screen *screen = nvc0_screen(pscreen);
 358    struct nouveau_channel *chan = screen->base.channel;
 359
 360    MARK_RING (chan, 5, 2);
 361
 362    /* we need to do it after possible flush in MARK_RING */
 363    *sequence = ++screen->base.fence.sequence;
 364
 365    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 366    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 367    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 368    OUT_RING  (chan, *sequence);
 369    OUT_RING  (chan, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 370               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 371 }
 372
 373 static u32
 374 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 375 {
 376    struct nvc0_screen *screen = nvc0_screen(pscreen);
 377    return screen->fence.map[0];
 378 }
 379
 380 #define FAIL_SCREEN_INIT(str, err)                    \
 381    do {                                               \
 382       NOUVEAU_ERR(str, err);                          \
 383       nvc0_screen_destroy(pscreen);                   \
 384       return NULL;                                    \
 385    } while(0)
 386
 387 struct pipe_screen *
 388 nvc0_screen_create(struct nouveau_device *dev)
 389 {
 390    struct nvc0_screen *screen;
 391    struct nouveau_channel *chan;
 392    struct pipe_screen *pscreen;
 393    int ret;
 394    unsigned i;
 395
 396    screen = CALLOC_STRUCT(nvc0_screen);
 397    if (!screen)
 398       return NULL;
 399    pscreen = &screen->base.base;
 400
 401    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 402
 403    ret = nouveau_screen_init(&screen->base, dev);
 404    if (ret) {
 405       nvc0_screen_destroy(pscreen);
 406       return NULL;
 407    }
 408    chan = screen->base.channel;
 409    chan->user_private = screen;
 410
 411    pscreen->destroy = nvc0_screen_destroy;
 412    pscreen->context_create = nvc0_create;
 413    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 414    pscreen->get_param = nvc0_screen_get_param;
 415    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 416    pscreen->get_paramf = nvc0_screen_get_paramf;
 417
 418    nvc0_screen_init_resource_functions(pscreen);
 419
 420    nouveau_screen_init_vdec(&screen->base);
 421
 422    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 423                         &screen->fence.bo);
 424    if (ret)
 425       goto fail;
 426    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 427    screen->fence.map = screen->fence.bo->map;
 428    nouveau_bo_unmap(screen->fence.bo);
 429    screen->base.fence.emit = nvc0_screen_fence_emit;
 430    screen->base.fence.update = nvc0_screen_fence_update;
 431
 432    for (i = 0; i < NVC0_SCRATCH_NR_BUFFERS; ++i) {
 433       ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, NVC0_SCRATCH_SIZE,
 434                            &screen->scratch.bo[i]);
 435       if (ret)
 436          goto fail;
 437    }
 438
 439    ret = nouveau_grobj_alloc(chan, 0xbeef9039, NVC0_M2MF, &screen->m2mf);
 440    if (ret)
 441       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 442
 443    BIND_RING (chan, screen->m2mf, NVC0_SUBCH_MF);
 444    BEGIN_RING(chan, RING_MF(NOTIFY_ADDRESS_HIGH), 3);
 445    OUT_RELOCh(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 446    OUT_RELOCl(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 447    OUT_RING  (chan, 0);
 448
 449    ret = nouveau_grobj_alloc(chan, 0xbeef902d, NVC0_2D, &screen->eng2d);
 450    if (ret)
 451       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 452
 453    BIND_RING (chan, screen->eng2d, NVC0_SUBCH_2D);
 454    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 455    OUT_RING  (chan, NVC0_2D_OPERATION_SRCCOPY);
 456    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 457    OUT_RING  (chan, 0);
 458    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 459    OUT_RING  (chan, 0);
 460    BEGIN_RING(chan, RING_2D_(0x0884), 1);
 461    OUT_RING  (chan, 0x3f);
 462    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 463    OUT_RING  (chan, 1);
 464
 465    ret = nouveau_grobj_alloc(chan, 0xbeef9097, NVC0_3D, &screen->fermi);
 466    if (ret)
 467       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 468
 469    BIND_RING (chan, screen->fermi, NVC0_SUBCH_3D);
 470    BEGIN_RING(chan, RING_3D(NOTIFY_ADDRESS_HIGH), 3);
 471    OUT_RELOCh(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 472    OUT_RELOCl(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 473    OUT_RING  (chan, 0);
 474
 475    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 476    OUT_RING  (chan, NVC0_3D_COND_MODE_ALWAYS);
 477
 478    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 479       /* kill shaders after about 1 second (at 100 MHz) */
 480       BEGIN_RING(chan, RING_3D(WATCHDOG_TIMER), 1);
 481       OUT_RING  (chan, 0x17);
 482    }
 483
 484    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 485    OUT_RING  (chan, 1);
 486
 487    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 488    OUT_RING  (chan, 0);
 489    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 490    OUT_RING  (chan, 0);
 491    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 492    OUT_RING  (chan, NVC0_3D_MULTISAMPLE_MODE_MS1);
 493    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 494    OUT_RING  (chan, 0);
 495    BEGIN_RING(chan, RING_3D(LINE_WIDTH_SEPARATE), 1);
 496    OUT_RING  (chan, 1);
 497    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 498    OUT_RING  (chan, 0);
 499    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 500    OUT_RING  (chan, 1);
 501    BEGIN_RING(chan, RING_3D(BLEND_ENABLE_COMMON), 1);
 502    OUT_RING  (chan, 0);
 503    BEGIN_RING(chan, RING_3D(TEX_MISC), 1);
 504    OUT_RING  (chan, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 505
 506    nvc0_magic_3d_init(chan);
 507
 508    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, &screen->text);
 509    if (ret)
 510       goto fail;
 511
 512    /* XXX: getting a page fault at the end of the code buffer every few
 513     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 514     */
 515    nouveau_resource_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 516
 517    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16,
 518                         &screen->uniforms);
 519    if (ret)
 520       goto fail;
 521
 522    /* auxiliary constants (6 user clip planes, base instance id) */
 523    BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 524    OUT_RING  (chan, 256);
 525    OUT_RELOCh(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 526    OUT_RELOCl(chan, screen->uniforms, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 527    for (i = 0; i < 5; ++i) {
 528       BEGIN_RING(chan, RING_3D(CB_BIND(i)), 1);
 529       OUT_RING  (chan, (15 << 4) | 1);
 530    }
 531
 532    screen->tls_size = (16 * 32) * (NVC0_CAP_MAX_PROGRAM_TEMPS * 16);
 533    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
 534                         screen->tls_size, &screen->tls);
 535    if (ret)
 536       goto fail;
 537
 538    BEGIN_RING(chan, RING_3D(CODE_ADDRESS_HIGH), 2);
 539    OUT_RELOCh(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 540    OUT_RELOCl(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 541    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 4);
 542    OUT_RELOCh(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 543    OUT_RELOCl(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 544    OUT_RING  (chan, screen->tls_size >> 32);
 545    OUT_RING  (chan, screen->tls_size);
 546    BEGIN_RING(chan, RING_3D_(0x07a0), 1);
 547    OUT_RING  (chan, 0);
 548    BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
 549    OUT_RING  (chan, 0);
 550
 551    for (i = 0; i < 5; ++i) {
 552       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 553       OUT_RING  (chan, 0x54);
 554    }
 555    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 556    OUT_RING  (chan, 0);
 557
 558    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20,
 559                         &screen->vfetch_cache);
 560    if (ret)
 561       goto fail;
 562
 563    BEGIN_RING(chan, RING_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
 564    OUT_RELOCh(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 565    OUT_RELOCl(chan, screen->vfetch_cache, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 566    OUT_RING  (chan, 3);
 567
 568    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, &screen->txc);
 569    if (ret)
 570       goto fail;
 571
 572    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 573    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 574    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 575    OUT_RING  (chan, NVC0_TIC_MAX_ENTRIES - 1);
 576
 577    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 578    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 579    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 580    OUT_RING  (chan, NVC0_TSC_MAX_ENTRIES - 1);
 581
 582    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 583    OUT_RING  (chan, 0);
 584    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 585    OUT_RING  (chan, 0);
 586    OUT_RING  (chan, 0);
 587    BEGIN_RING(chan, RING_3D_(0x1590), 1); /* deactivate ZCULL */
 588    OUT_RING  (chan, 0x3f);
 589
 590    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 591    OUT_RING  (chan, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 592    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 593    for (i = 0; i < 8 * 2; ++i)
 594       OUT_RING(chan, 0);
 595    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 596    OUT_RING  (chan, 0);
 597    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 598    OUT_RING  (chan, 0);
 599
 600    /* neither scissors, viewport nor stencil mask should affect clears */
 601    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 602    OUT_RING  (chan, 0);
 603
 604    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 605    OUT_RING  (chan, 1);
 606    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 607    OUT_RINGf (chan, 0.0f);
 608    OUT_RINGf (chan, 1.0f);
 609    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 610    OUT_RING  (chan, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
 611
 612    /* We use scissors instead of exact view volume clipping,
 613     * so they're always enabled.
 614     */
 615    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 616    OUT_RING  (chan, 1);
 617    OUT_RING  (chan, 8192 << 16);
 618    OUT_RING  (chan, 8192 << 16);
 619
 620 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 621
 622    i = 0;
 623    MK_MACRO(NVC0_3D_BLEND_ENABLES, nvc0_9097_blend_enables);
 624    MK_MACRO(NVC0_3D_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 625    MK_MACRO(NVC0_3D_TEP_SELECT, nvc0_9097_tep_select);
 626    MK_MACRO(NVC0_3D_GP_SELECT, nvc0_9097_gp_select);
 627    MK_MACRO(NVC0_3D_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 628    MK_MACRO(NVC0_3D_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 629
 630    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 631    OUT_RING  (chan, 1);
 632    BEGIN_RING(chan, RING_3D(RT_SEPARATE_FRAG_DATA), 1);
 633    OUT_RING  (chan, 1);
 634    BEGIN_RING(chan, RING_3D(GP_SELECT), 1);
 635    OUT_RING  (chan, 0x40);
 636    BEGIN_RING(chan, RING_3D(LAYER), 1);
 637    OUT_RING  (chan, 0);
 638    BEGIN_RING(chan, RING_3D(TEP_SELECT), 1);
 639    OUT_RING  (chan, 0x30);
 640    BEGIN_RING(chan, RING_3D(PATCH_VERTICES), 1);
 641    OUT_RING  (chan, 3);
 642    BEGIN_RING(chan, RING_3D(SP_SELECT(2)), 1);
 643    OUT_RING  (chan, 0x20);
 644    BEGIN_RING(chan, RING_3D(SP_SELECT(0)), 1);
 645    OUT_RING  (chan, 0x00);
 646
 647    BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
 648    OUT_RING  (chan, 0);
 649    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 650    OUT_RING  (chan, NVC0_3D_POINT_RASTER_RULES_OGL);
 651
 652    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 653    OUT_RING  (chan, 1);
 654
 655    BEGIN_RING(chan, RING_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 656    OUT_RING  (chan, 0xab);
 657    OUT_RING  (chan, 0x00000000);
 658
 659    FIRE_RING (chan);
 660
 661    screen->tic.entries = CALLOC(4096, sizeof(void *));
 662    screen->tsc.entries = screen->tic.entries + 2048;
 663
 664    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 665
 666    if (!nvc0_blitctx_create(screen))
 667       goto fail;
 668
 669    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 670
 671    return pscreen;
 672
 673 fail:
 674    nvc0_screen_destroy(pscreen);
 675    return NULL;
 676 }
 677
 678 void
 679 nvc0_screen_make_buffers_resident(struct nvc0_screen *screen)
 680 {
 681    struct nouveau_channel *chan = screen->base.channel;
 682
 683    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 684
 685    MARK_RING(chan, 0, 5);
 686    nouveau_bo_validate(chan, screen->text, flags);
 687    nouveau_bo_validate(chan, screen->uniforms, flags);
 688    nouveau_bo_validate(chan, screen->txc, flags);
 689    nouveau_bo_validate(chan, screen->vfetch_cache, flags);
 690
 691    if (screen->cur_ctx && screen->cur_ctx->state.tls_required)
 692       nouveau_bo_validate(chan, screen->tls, flags);
 693 }
 694
 695 int
 696 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 697 {
 698    int i = screen->tic.next;
 699
 700    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 701       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 702
 703    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 704
 705    if (screen->tic.entries[i])
 706       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 707
 708    screen->tic.entries[i] = entry;
 709    return i;
 710 }
 711
 712 int
 713 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 714 {
 715    int i = screen->tsc.next;
 716
 717    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 718       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 719
 720    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 721
 722    if (screen->tsc.entries[i])
 723       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 724
 725    screen->tsc.entries[i] = entry;
 726    return i;
 727 }