src/gallium/drivers/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nvc0_fence.h"
  27 #include "nvc0_context.h"
  28 #include "nvc0_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31 #include "nvc0_graph_macros.h"
  32
  33 static boolean
  34 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  35                                 enum pipe_format format,
  36                                 enum pipe_texture_target target,
  37                                 unsigned sample_count,
  38                                 unsigned bindings, unsigned geom_flags)
  39 {
  40    if (sample_count > 1)
  41       return FALSE;
  42
  43    if (!util_format_s3tc_enabled) {
  44       switch (format) {
  45       case PIPE_FORMAT_DXT1_RGB:
  46       case PIPE_FORMAT_DXT1_RGBA:
  47       case PIPE_FORMAT_DXT3_RGBA:
  48       case PIPE_FORMAT_DXT5_RGBA:
  49          return FALSE;
  50       default:
  51          break;
  52       }
  53    }
  54
  55    /* transfers & shared are always supported */
  56    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  57                  PIPE_BIND_TRANSFER_WRITE |
  58                  PIPE_BIND_SHARED);
  59
  60    return (nvc0_format_table[format].usage & bindings) == bindings;
  61 }
  62
  63 static int
  64 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  65 {
  66    switch (param) {
  67    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  68    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  69       return 32;
  70    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  71       return 64;
  72    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  73       return 13;
  74    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  75       return 10;
  76    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  77       return 13;
  78    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  79    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  80    case PIPE_CAP_TEXTURE_SWIZZLE:
  81    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  82    case PIPE_CAP_NPOT_TEXTURES:
  83    case PIPE_CAP_ANISOTROPIC_FILTER:
  84       return 1;
  85    case PIPE_CAP_TWO_SIDED_STENCIL:
  86    case PIPE_CAP_DEPTH_CLAMP:
  87    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  88    case PIPE_CAP_POINT_SPRITE:
  89       return 1;
  90    case PIPE_CAP_GLSL:
  91    case PIPE_CAP_SM3:
  92       return 1;
  93    case PIPE_CAP_MAX_RENDER_TARGETS:
  94       return 8;
  95    case PIPE_CAP_OCCLUSION_QUERY:
  96       return 1;
  97    case PIPE_CAP_TIMER_QUERY:
  98    case PIPE_CAP_STREAM_OUTPUT:
  99       return 0;
 100    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 101    case PIPE_CAP_INDEP_BLEND_ENABLE:
 102    case PIPE_CAP_INDEP_BLEND_FUNC:
 103       return 1;
 104    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 105    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 106       return 1;
 107    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 108    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 109       return 0;
 110    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 111       return 0;
 112    case PIPE_CAP_PRIMITIVE_RESTART:
 113       return 1;
 114    default:
 115       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 116       return 0;
 117    }
 118 }
 119
 120 static int
 121 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 122                              enum pipe_shader_cap param)
 123 {
 124    switch (shader) {
 125    case PIPE_SHADER_VERTEX:
 126       /*
 127    case PIPE_SHADER_TESSELLATION_CONTROL:
 128    case PIPE_SHADER_TESSELLATION_EVALUATION:
 129       */
 130    case PIPE_SHADER_GEOMETRY:
 131    case PIPE_SHADER_FRAGMENT:
 132       break;
 133    default:
 134       return 0;
 135    }
 136
 137    switch (param) {
 138    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 139    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 140    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 141    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 142       return 16384;
 143    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 144       return 4;
 145    case PIPE_SHADER_CAP_MAX_INPUTS:
 146       if (shader == PIPE_SHADER_VERTEX)
 147          return 32;
 148       return 0x300 / 16;
 149    case PIPE_SHADER_CAP_MAX_CONSTS:
 150       return 65536 / 16;
 151    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 152       return 14;
 153    case PIPE_SHADER_CAP_MAX_ADDRS:
 154       return 1;
 155    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 156    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 157       return shader != PIPE_SHADER_FRAGMENT;
 158    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 159    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 160       return 1;
 161    case PIPE_SHADER_CAP_MAX_PREDS:
 162       return 0;
 163    case PIPE_SHADER_CAP_MAX_TEMPS:
 164       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 165    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 166       return 1;
 167    default:
 168       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 169       return 0;
 170    }
 171 }
 172
 173 static float
 174 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 175 {
 176    switch (param) {
 177    case PIPE_CAP_MAX_LINE_WIDTH:
 178    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 179       return 10.0f;
 180    case PIPE_CAP_MAX_POINT_WIDTH:
 181    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 182       return 64.0f;
 183    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 184       return 16.0f;
 185    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 186       return 4.0f;
 187    default:
 188       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 189       return 0.0f;
 190    }
 191 }
 192
 193 static void
 194 nvc0_screen_destroy(struct pipe_screen *pscreen)
 195 {
 196    struct nvc0_screen *screen = nvc0_screen(pscreen);
 197
 198    nouveau_bo_ref(NULL, &screen->text);
 199    nouveau_bo_ref(NULL, &screen->tls);
 200    nouveau_bo_ref(NULL, &screen->txc);
 201    nouveau_bo_ref(NULL, &screen->fence.bo);
 202    nouveau_bo_ref(NULL, &screen->mp_stack_bo);
 203
 204    nouveau_resource_destroy(&screen->text_heap);
 205
 206    if (screen->tic.entries)
 207       FREE(screen->tic.entries);
 208
 209    nouveau_screen_fini(&screen->base);
 210
 211    FREE(screen);
 212 }
 213
 214 static int
 215 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 216                      unsigned size, const uint32_t *data)
 217 {
 218    struct nouveau_channel *chan = screen->base.channel;
 219
 220    size /= 4;
 221
 222    BEGIN_RING(chan, RING_ANY(NVC0_GRAPH_MACRO_ID), 2);
 223    OUT_RING  (chan, (m - 0x3800) / 8);
 224    OUT_RING  (chan, pos);
 225    BEGIN_RING_1I(chan, RING_ANY(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 226    OUT_RING  (chan, pos);
 227    OUT_RINGp (chan, data, size);
 228
 229    return pos + size;
 230 }
 231
 232 static void
 233 nvc0_screen_fence_reference(struct pipe_screen *pscreen,
 234                             struct pipe_fence_handle **ptr,
 235                             struct pipe_fence_handle *fence)
 236 {
 237    nvc0_fence_reference((struct nvc0_fence **)ptr, nvc0_fence(fence));
 238 }
 239
 240 static int
 241 nvc0_screen_fence_signalled(struct pipe_screen *pscreen,
 242                             struct pipe_fence_handle *fence,
 243                             unsigned flags)
 244 {
 245    return !(((struct nvc0_fence *)fence)->state == NVC0_FENCE_STATE_SIGNALLED);
 246 }
 247
 248 static int
 249 nvc0_screen_fence_finish(struct pipe_screen *pscreen,
 250                          struct pipe_fence_handle *fence,
 251                          unsigned flags)
 252 {
 253    return nvc0_fence_wait((struct nvc0_fence *)fence) != TRUE;
 254 }
 255
 256 static void
 257 nvc0_magic_3d_init(struct nouveau_channel *chan)
 258 {
 259    BEGIN_RING(chan, RING_3D_(0x10cc), 1);
 260    OUT_RING  (chan, 0xff);
 261    BEGIN_RING(chan, RING_3D_(0x10e0), 2);
 262    OUT_RING(chan, 0xff);
 263    OUT_RING(chan, 0xff);
 264    BEGIN_RING(chan, RING_3D_(0x10ec), 2);
 265    OUT_RING(chan, 0xff);
 266    OUT_RING(chan, 0xff);
 267    BEGIN_RING(chan, RING_3D_(0x074c), 1);
 268    OUT_RING  (chan, 0x3f);
 269
 270    BEGIN_RING(chan, RING_3D_(0x10f8), 1);
 271    OUT_RING  (chan, 0x0101);
 272
 273    BEGIN_RING(chan, RING_3D_(0x16a8), 1);
 274    OUT_RING  (chan, (3 << 16) | 3);
 275    BEGIN_RING(chan, RING_3D_(0x1794), 1);
 276    OUT_RING  (chan, (2 << 16) | 2);
 277    BEGIN_RING(chan, RING_3D_(0x0de8), 1);
 278    OUT_RING  (chan, 1);
 279    BEGIN_RING(chan, RING_3D_(0x165c), 1);
 280    OUT_RING  (chan, 0);
 281
 282    BEGIN_RING(chan, RING_3D_(0x1528), 1); /* MP poke */
 283    OUT_RING  (chan, 0);
 284
 285    BEGIN_RING(chan, RING_3D_(0x12ac), 1);
 286    OUT_RING  (chan, 0);
 287    BEGIN_RING(chan, RING_3D_(0x0218), 1);
 288    OUT_RING  (chan, 0x10);
 289    BEGIN_RING(chan, RING_3D_(0x10fc), 1);
 290    OUT_RING  (chan, 0x10);
 291    BEGIN_RING(chan, RING_3D_(0x1290), 1);
 292    OUT_RING  (chan, 0x10);
 293    BEGIN_RING(chan, RING_3D_(0x12d8), 2);
 294    OUT_RING  (chan, 0x10);
 295    OUT_RING  (chan, 0x10);
 296    BEGIN_RING(chan, RING_3D_(0x06d4), 1);
 297    OUT_RING  (chan, 8);
 298    BEGIN_RING(chan, RING_3D_(0x1140), 1);
 299    OUT_RING  (chan, 0x10);
 300    BEGIN_RING(chan, RING_3D_(0x1610), 1);
 301    OUT_RING  (chan, 0xe);
 302
 303    BEGIN_RING(chan, RING_3D_(0x164c), 1);
 304    OUT_RING  (chan, 1 << 12);
 305    BEGIN_RING(chan, RING_3D_(0x151c), 1);
 306    OUT_RING  (chan, 1);
 307    BEGIN_RING(chan, RING_3D_(0x020c), 1);
 308    OUT_RING  (chan, 1);
 309    BEGIN_RING(chan, RING_3D_(0x030c), 1);
 310    OUT_RING  (chan, 0);
 311    BEGIN_RING(chan, RING_3D_(0x0300), 1);
 312    OUT_RING  (chan, 3);
 313    BEGIN_RING(chan, RING_3D_(0x1280), 1); /* PGRAPH poke */
 314    OUT_RING  (chan, 0);
 315    BEGIN_RING(chan, RING_3D_(0x02d0), 1);
 316    OUT_RING  (chan, 0x1f40);
 317    BEGIN_RING(chan, RING_3D_(0x00fdc), 1);
 318    OUT_RING  (chan, 1);
 319    BEGIN_RING(chan, RING_3D_(0x19c0), 1);
 320    OUT_RING  (chan, 1);
 321    BEGIN_RING(chan, RING_3D_(0x075c), 1);
 322    OUT_RING  (chan, 3);
 323
 324    BEGIN_RING(chan, RING_3D_(0x0fac), 1);
 325    OUT_RING  (chan, 0);
 326    BEGIN_RING(chan, RING_3D_(0x0f90), 1);
 327    OUT_RING  (chan, 0);
 328 }
 329
 330 struct pipe_screen *
 331 nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 332 {
 333    struct nvc0_screen *screen;
 334    struct nouveau_channel *chan;
 335    struct pipe_screen *pscreen;
 336    int ret;
 337    unsigned i;
 338
 339    screen = CALLOC_STRUCT(nvc0_screen);
 340    if (!screen)
 341       return NULL;
 342    pscreen = &screen->base.base;
 343
 344    ret = nouveau_screen_init(&screen->base, dev);
 345    if (ret) {
 346       nvc0_screen_destroy(pscreen);
 347       return NULL;
 348    }
 349    chan = screen->base.channel;
 350
 351    pscreen->winsys = ws;
 352    pscreen->destroy = nvc0_screen_destroy;
 353    pscreen->context_create = nvc0_create;
 354    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 355    pscreen->get_param = nvc0_screen_get_param;
 356    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 357    pscreen->get_paramf = nvc0_screen_get_paramf;
 358    pscreen->fence_reference = nvc0_screen_fence_reference;
 359    pscreen->fence_signalled = nvc0_screen_fence_signalled;
 360    pscreen->fence_finish = nvc0_screen_fence_finish;
 361
 362    nvc0_screen_init_resource_functions(pscreen);
 363
 364    screen->base.vertex_buffer_flags = NOUVEAU_BO_GART;
 365    screen->base.index_buffer_flags = 0;
 366
 367    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, 4096, &screen->fence.bo);
 368    if (ret)
 369       goto fail;
 370    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 371    screen->fence.map = screen->fence.bo->map;
 372    nouveau_bo_unmap(screen->fence.bo);
 373
 374    for (i = 0; i < NVC0_SCRATCH_NR_BUFFERS; ++i) {
 375       ret = nouveau_bo_new(dev, NOUVEAU_BO_GART, 0, NVC0_SCRATCH_SIZE,
 376                            &screen->scratch.bo[i]);
 377       if (ret)
 378          goto fail;
 379    }
 380
 381    for (i = 0; i < 8; ++i) {
 382       BEGIN_RING(chan, (i << 13) | (0x0000 >> 2), 1);
 383       OUT_RING  (chan, 0x0000);
 384    }
 385
 386    BEGIN_RING(chan, RING_MF_(0x0000), 1);
 387    OUT_RING  (chan, 0x9039);
 388    BEGIN_RING(chan, RING_MF(NOTIFY_ADDRESS_HIGH), 3);
 389    OUT_RELOCh(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 390    OUT_RELOCl(chan, screen->fence.bo, 16, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 391    OUT_RING  (chan, 0);
 392
 393    BEGIN_RING(chan, RING_2D_(0x0000), 1);
 394    OUT_RING  (chan, 0x902d);
 395    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 396    OUT_RING  (chan, NVC0_2D_OPERATION_SRCCOPY);
 397    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 398    OUT_RING  (chan, 0);
 399    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 400    OUT_RING  (chan, 0);
 401    BEGIN_RING(chan, RING_2D_(0x0884), 1);
 402    OUT_RING  (chan, 0x3f);
 403    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 404    OUT_RING  (chan, 1);
 405
 406    BEGIN_RING(chan, RING_3D_(0x0000), 1);
 407    OUT_RING  (chan, 0x9097);
 408    BEGIN_RING(chan, RING_3D(NOTIFY_ADDRESS_HIGH), 3);
 409    OUT_RELOCh(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 410    OUT_RELOCl(chan, screen->fence.bo, 32, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 411    OUT_RING  (chan, 0);
 412
 413    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 414    OUT_RING  (chan, NVC0_3D_COND_MODE_ALWAYS);
 415
 416    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 417    OUT_RING  (chan, 1);
 418
 419    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ZETA_ENABLE), 1);
 420    OUT_RING  (chan, 0);
 421    BEGIN_RING(chan, RING_3D(MULTISAMPLE_COLOR_ENABLE), 1);
 422    OUT_RING  (chan, 0);
 423    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 424    OUT_RING  (chan, NVC0_3D_MULTISAMPLE_MODE_1X);
 425    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 426    OUT_RING  (chan, 0);
 427
 428    nvc0_magic_3d_init(chan);
 429
 430    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, &screen->text);
 431    if (ret)
 432       goto fail;
 433    /* nouveau_bo_pin(dev, screen->text); */
 434
 435    nouveau_resource_init(&screen->text_heap, 0, 1 << 20);
 436
 437    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 5 << 16,
 438                         &screen->uniforms);
 439    if (ret)
 440       goto fail;
 441
 442    screen->tls_size = 4 * 4 * 32 * 128 * 4;
 443    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17,
 444                         screen->tls_size, &screen->tls);
 445    if (ret)
 446       goto fail;
 447
 448    BEGIN_RING(chan, RING_3D(CODE_ADDRESS_HIGH), 2);
 449    OUT_RELOCh(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 450    OUT_RELOCl(chan, screen->text, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 451    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 4);
 452    OUT_RELOCh(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 453    OUT_RELOCl(chan, screen->tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 454    OUT_RING  (chan, screen->tls_size >> 32);
 455    OUT_RING  (chan, screen->tls_size);
 456    BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
 457    OUT_RING  (chan, 0);
 458
 459    for (i = 0; i < 5; ++i) {
 460       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 461       OUT_RING  (chan, 0x54);
 462    }
 463    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 464    OUT_RING  (chan, 0);
 465
 466    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20,
 467                         &screen->mp_stack_bo);
 468    if (ret)
 469       goto fail;
 470    /* nouveau_bo_pin(dev, screen->mp_stack_bo); */
 471
 472    BEGIN_RING(chan, RING_3D_(0x17bc), 3);
 473    OUT_RELOCh(chan, screen->mp_stack_bo, 0, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 474    OUT_RELOCl(chan, screen->mp_stack_bo, 0, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR);
 475    OUT_RING  (chan, 1);
 476
 477    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, &screen->txc);
 478    if (ret)
 479       goto fail;
 480    /* nouveau_bo_pin(dev, screen->txc); */
 481
 482    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 483    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 484    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 485    OUT_RING  (chan, NVC0_TIC_MAX_ENTRIES - 1);
 486
 487    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 488    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 489    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 490    OUT_RING  (chan, NVC0_TSC_MAX_ENTRIES - 1);
 491
 492    BEGIN_RING(chan, RING_3D(Y_ORIGIN_BOTTOM), 1);
 493    OUT_RING  (chan, 0);
 494    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 495    OUT_RING  (chan, 0);
 496    OUT_RING  (chan, 0);
 497    BEGIN_RING(chan, RING_3D_(0x1590), 1); /* deactivate ZCULL */
 498    OUT_RING  (chan, 0x3f);
 499
 500    BEGIN_RING(chan, RING_3D(VIEWPORT_CLIP_RECTS_EN), 1);
 501    OUT_RING  (chan, 0);
 502    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 503    OUT_RING  (chan, 0);
 504
 505    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 506    OUT_RING  (chan, 1);
 507    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 508    OUT_RINGf (chan, 0.0f);
 509    OUT_RINGf (chan, 1.0f);
 510
 511    /* We use scissors instead of exact view volume clipping,
 512     * so they're always enabled.
 513     */
 514    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 515    OUT_RING  (chan, 1);
 516    OUT_RING  (chan, 8192 << 16);
 517    OUT_RING  (chan, 8192 << 16);
 518
 519    BEGIN_RING(chan, RING_3D_(0x0fac), 1);
 520    OUT_RING  (chan, 0);
 521    BEGIN_RING(chan, RING_3D_(0x3484), 1);
 522    OUT_RING  (chan, 0);
 523    BEGIN_RING(chan, RING_3D_(0x0dbc), 1);
 524    OUT_RING  (chan, 0x00010000);
 525    BEGIN_RING(chan, RING_3D_(0x0dd8), 1);
 526    OUT_RING  (chan, 0xff800006);
 527    BEGIN_RING(chan, RING_3D_(0x3488), 1);
 528    OUT_RING  (chan, 0);
 529
 530 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
 531
 532    i = 0;
 533    MK_MACRO(NVC0_3D_BLEND_ENABLES, nvc0_9097_blend_enables);
 534    MK_MACRO(NVC0_3D_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
 535    MK_MACRO(NVC0_3D_TEP_SELECT, nvc0_9097_tep_select);
 536    MK_MACRO(NVC0_3D_GP_SELECT, nvc0_9097_gp_select);
 537    MK_MACRO(NVC0_3D_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
 538    MK_MACRO(NVC0_3D_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
 539    MK_MACRO(NVC0_3D_COLOR_MASK_BROADCAST, nvc0_9097_color_mask_brdc);
 540
 541    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 542    OUT_RING  (chan, 1);
 543    BEGIN_RING(chan, RING_3D(GP_SELECT), 1);
 544    OUT_RING  (chan, 0x40);
 545    BEGIN_RING(chan, RING_3D(GP_BUILTIN_RESULT_EN), 1);
 546    OUT_RING  (chan, 0);
 547    BEGIN_RING(chan, RING_3D(TEP_SELECT), 1);
 548    OUT_RING  (chan, 0x30);
 549    BEGIN_RING(chan, RING_3D(PATCH_VERTICES), 1);
 550    OUT_RING  (chan, 3);
 551    BEGIN_RING(chan, RING_3D(SP_SELECT(2)), 1);
 552    OUT_RING  (chan, 0x20);
 553    BEGIN_RING(chan, RING_3D(SP_SELECT(0)), 1);
 554    OUT_RING  (chan, 0x00);
 555
 556    BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
 557    OUT_RING  (chan, 0);
 558
 559    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 560    OUT_RING  (chan, 0x11111111);
 561    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 562    OUT_RING  (chan, 1);
 563
 564    BEGIN_RING(chan, RING_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 565    OUT_RING  (chan, 0xab);
 566    OUT_RING  (chan, 0x00000000);
 567
 568    FIRE_RING (chan);
 569
 570    screen->tic.entries = CALLOC(4096, sizeof(void *));
 571    screen->tsc.entries = screen->tic.entries + 2048;
 572
 573    screen->mm_GART = nvc0_mm_create(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
 574                                     0x000);
 575    screen->mm_VRAM = nvc0_mm_create(dev, NOUVEAU_BO_VRAM, 0x000);
 576    screen->mm_VRAM_fe0 = nvc0_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 577
 578    nvc0_screen_fence_new(screen, &screen->fence.current, FALSE);
 579
 580    return pscreen;
 581
 582 fail:
 583    nvc0_screen_destroy(pscreen);
 584    return NULL;
 585 }
 586
 587 void
 588 nvc0_screen_make_buffers_resident(struct nvc0_screen *screen)
 589 {
 590    struct nouveau_channel *chan = screen->base.channel;
 591
 592    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 593
 594    nouveau_reloc_emit(chan, NULL, 0, NULL, screen->text, 0, 0, flags, 0, 0);
 595    nouveau_reloc_emit(chan, NULL, 0, NULL, screen->txc, 0, 0, flags, 0, 0);
 596    nouveau_reloc_emit(chan, NULL, 0, NULL, screen->tls, 0, 0, flags, 0, 0);
 597 }
 598
 599 int
 600 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
 601 {
 602    int i = screen->tic.next;
 603
 604    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 605       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 606
 607    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
 608
 609    if (screen->tic.entries[i])
 610       nvc0_tic_entry(screen->tic.entries[i])->id = -1;
 611
 612    screen->tic.entries[i] = entry;
 613    return i;
 614 }
 615
 616 int
 617 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
 618 {
 619    int i = screen->tsc.next;
 620
 621    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 622       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 623
 624    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
 625
 626    if (screen->tsc.entries[i])
 627       nvc0_tsc_entry(screen->tsc.entries[i])->id = -1;
 628
 629    screen->tsc.entries[i] = entry;
 630    return i;
 631 }