gallium: remove PIPE_CAP_GLSL and enable GLSL unconditionally
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_screen.h
1 #ifndef __NVC0_SCREEN_H__
2 #define __NVC0_SCREEN_H__
3
4 #define NOUVEAU_NVC0
5 #include "nouveau/nouveau_screen.h"
6 #include "nouveau/nouveau_mm.h"
7 #include "nouveau/nouveau_fence.h"
8 #undef NOUVEAU_NVC0
9 #include "nvc0_winsys.h"
10 #include "nvc0_stateobj.h"
11
12 #define NVC0_TIC_MAX_ENTRIES 2048
13 #define NVC0_TSC_MAX_ENTRIES 2048
14
15 struct nvc0_context;
16
17 #define NVC0_SCRATCH_SIZE (2 << 20)
18 #define NVC0_SCRATCH_NR_BUFFERS 2
19
20 #define NVC0_SCREEN_RESIDENT_BO_COUNT 5
21
22 struct nvc0_blitctx;
23
24 struct nvc0_screen {
25 struct nouveau_screen base;
26 struct nouveau_winsys *nvws;
27
28 struct nvc0_context *cur_ctx;
29
30 int num_occlusion_queries_active;
31
32 struct nouveau_bo *text;
33 struct nouveau_bo *uniforms;
34 struct nouveau_bo *tls;
35 struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
36 struct nouveau_bo *vfetch_cache;
37
38 uint64_t tls_size;
39
40 struct nouveau_resource *text_heap;
41 struct nouveau_resource *lib_code; /* allocated from text_heap */
42
43 struct nvc0_blitctx *blitctx;
44
45 struct {
46 struct nouveau_bo *bo[NVC0_SCRATCH_NR_BUFFERS];
47 uint8_t *buf;
48 int index;
49 uint32_t offset;
50 } scratch;
51
52 struct {
53 void **entries;
54 int next;
55 uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];
56 } tic;
57
58 struct {
59 void **entries;
60 int next;
61 uint32_t lock[NVC0_TSC_MAX_ENTRIES / 32];
62 } tsc;
63
64 struct {
65 struct nouveau_bo *bo;
66 uint32_t *map;
67 } fence;
68
69 struct nouveau_mman *mm_VRAM_fe0;
70
71 struct nouveau_grobj *fermi;
72 struct nouveau_grobj *eng2d;
73 struct nouveau_grobj *m2mf;
74 };
75
76 static INLINE struct nvc0_screen *
77 nvc0_screen(struct pipe_screen *screen)
78 {
79 return (struct nvc0_screen *)screen;
80 }
81
82 boolean nvc0_blitctx_create(struct nvc0_screen *);
83
84 void nvc0_screen_make_buffers_resident(struct nvc0_screen *);
85
86 int nvc0_screen_tic_alloc(struct nvc0_screen *, void *);
87 int nvc0_screen_tsc_alloc(struct nvc0_screen *, void *);
88
89 static INLINE void
90 nvc0_resource_fence(struct nv04_resource *res, uint32_t flags)
91 {
92 struct nvc0_screen *screen = nvc0_screen(res->base.screen);
93
94 if (res->mm) {
95 nouveau_fence_ref(screen->base.fence.current, &res->fence);
96
97 if (flags & NOUVEAU_BO_WR)
98 nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);
99 }
100 }
101
102 static INLINE void
103 nvc0_resource_validate(struct nv04_resource *res, uint32_t flags)
104 {
105 struct nvc0_screen *screen = nvc0_screen(res->base.screen);
106
107 if (likely(res->bo)) {
108 nouveau_bo_validate(screen->base.channel, res->bo, flags);
109
110 if (flags & NOUVEAU_BO_WR)
111 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
112 if (flags & NOUVEAU_BO_RD)
113 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
114
115 nvc0_resource_fence(res, flags);
116 }
117 }
118
119 struct nvc0_format {
120 uint32_t rt;
121 uint32_t tic;
122 uint32_t vtx;
123 uint32_t usage;
124 };
125
126 extern const struct nvc0_format nvc0_format_table[];
127
128 static INLINE void
129 nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
130 {
131 if (tic->id >= 0)
132 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
133 }
134
135 static INLINE void
136 nvc0_screen_tsc_unlock(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
137 {
138 if (tsc->id >= 0)
139 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
140 }
141
142 static INLINE void
143 nvc0_screen_tic_free(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
144 {
145 if (tic->id >= 0) {
146 screen->tic.entries[tic->id] = NULL;
147 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
148 }
149 }
150
151 static INLINE void
152 nvc0_screen_tsc_free(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
153 {
154 if (tsc->id >= 0) {
155 screen->tsc.entries[tsc->id] = NULL;
156 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
157 }
158 }
159
160 #endif