nouveau: switch to libdrm_nouveau-2.0
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_inlines.h"
25 #include "util/u_transfer.h"
26
27 #include "tgsi/tgsi_parse.h"
28
29 #include "nvc0_stateobj.h"
30 #include "nvc0_context.h"
31
32 #include "nvc0_3d.xml.h"
33 #include "nv50/nv50_texture.xml.h"
34
35 #include "nouveau/nouveau_gldefs.h"
36
37 static INLINE uint32_t
38 nvc0_colormask(unsigned mask)
39 {
40 uint32_t ret = 0;
41
42 if (mask & PIPE_MASK_R)
43 ret |= 0x0001;
44 if (mask & PIPE_MASK_G)
45 ret |= 0x0010;
46 if (mask & PIPE_MASK_B)
47 ret |= 0x0100;
48 if (mask & PIPE_MASK_A)
49 ret |= 0x1000;
50
51 return ret;
52 }
53
54 #define NVC0_BLEND_FACTOR_CASE(a, b) \
55 case PIPE_BLENDFACTOR_##a: return NV50_3D_BLEND_FACTOR_##b
56
57 static INLINE uint32_t
58 nvc0_blend_fac(unsigned factor)
59 {
60 switch (factor) {
61 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
62 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
63 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
64 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
65 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
66 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
67 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
68 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
69 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
70 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
71 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
72 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
73 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
74 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
75 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
76 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
77 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
78 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
80 default:
81 return NV50_3D_BLEND_FACTOR_ZERO;
82 }
83 }
84
85 static void *
86 nvc0_blend_state_create(struct pipe_context *pipe,
87 const struct pipe_blend_state *cso)
88 {
89 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
90 int i;
91 uint32_t ms;
92
93 so->pipe = *cso;
94
95 SB_IMMED_3D(so, BLEND_INDEPENDENT, cso->independent_blend_enable);
96
97 if (!cso->logicop_enable)
98 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
99
100 if (cso->logicop_enable) {
101 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
102 SB_DATA (so, 1);
103 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
104
105 SB_IMMED_3D(so, BLEND_ENABLES, 0);
106 } else
107 if (!cso->independent_blend_enable) {
108 SB_IMMED_3D(so, BLEND_ENABLES, cso->rt[0].blend_enable ? 0xff : 0);
109
110 if (cso->rt[0].blend_enable) {
111 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
112 SB_DATA (so, nvgl_blend_eqn(cso->rt[0].rgb_func));
113 SB_DATA (so, nvc0_blend_fac(cso->rt[0].rgb_src_factor));
114 SB_DATA (so, nvc0_blend_fac(cso->rt[0].rgb_dst_factor));
115 SB_DATA (so, nvgl_blend_eqn(cso->rt[0].alpha_func));
116 SB_DATA (so, nvc0_blend_fac(cso->rt[0].alpha_src_factor));
117 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
118 SB_DATA (so, nvc0_blend_fac(cso->rt[0].alpha_dst_factor));
119 }
120
121 SB_IMMED_3D(so, COLOR_MASK_COMMON, 1);
122 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
123 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
124 } else {
125 uint8_t en = 0;
126
127 for (i = 0; i < 8; ++i) {
128 if (!cso->rt[i].blend_enable)
129 continue;
130 en |= 1 << i;
131
132 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
133 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
134 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
135 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
136 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
137 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
138 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
139 }
140 SB_IMMED_3D(so, BLEND_ENABLES, en);
141
142 SB_IMMED_3D(so, COLOR_MASK_COMMON, 0);
143 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
144 for (i = 0; i < 8; ++i)
145 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
146 }
147
148 ms = 0;
149 if (cso->alpha_to_coverage)
150 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
151 if (cso->alpha_to_one)
152 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
153
154 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
155 SB_DATA (so, ms);
156
157 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
158 return so;
159 }
160
161 static void
162 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
163 {
164 struct nvc0_context *nvc0 = nvc0_context(pipe);
165
166 nvc0->blend = hwcso;
167 nvc0->dirty |= NVC0_NEW_BLEND;
168 }
169
170 static void
171 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
172 {
173 FREE(hwcso);
174 }
175
176 /* NOTE: ignoring line_last_pixel, using FALSE (set on screen init) */
177 static void *
178 nvc0_rasterizer_state_create(struct pipe_context *pipe,
179 const struct pipe_rasterizer_state *cso)
180 {
181 struct nvc0_rasterizer_stateobj *so;
182 uint32_t reg;
183
184 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
185 if (!so)
186 return NULL;
187 so->pipe = *cso;
188
189 /* Scissor enables are handled in scissor state, we will not want to
190 * always emit 16 commands, one for each scissor rectangle, here.
191 */
192
193 SB_BEGIN_3D(so, SHADE_MODEL, 1);
194 SB_DATA (so, cso->flatshade ? NVC0_3D_SHADE_MODEL_FLAT :
195 NVC0_3D_SHADE_MODEL_SMOOTH);
196 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
197 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
198
199 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
200 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
201 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
202
203 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
204
205 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
206 if (cso->line_smooth)
207 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
208 else
209 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
210 SB_DATA (so, fui(cso->line_width));
211
212 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
213 if (cso->line_stipple_enable) {
214 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
215 SB_DATA (so, (cso->line_stipple_pattern << 8) |
216 cso->line_stipple_factor);
217
218 }
219
220 SB_IMMED_3D(so, VP_POINT_SIZE_EN, cso->point_size_per_vertex);
221 if (!cso->point_size_per_vertex) {
222 SB_BEGIN_3D(so, POINT_SIZE, 1);
223 SB_DATA (so, fui(cso->point_size));
224 }
225
226 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
227 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
228 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
229
230 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
231 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
232 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
233 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
234
235 SB_BEGIN_3D(so, POLYGON_MODE_FRONT, 1);
236 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
237 SB_BEGIN_3D(so, POLYGON_MODE_BACK, 1);
238 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
239 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
240
241 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
242 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
243 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
244 NVC0_3D_FRONT_FACE_CW);
245 switch (cso->cull_face) {
246 case PIPE_FACE_FRONT_AND_BACK:
247 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
248 break;
249 case PIPE_FACE_FRONT:
250 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
251 break;
252 case PIPE_FACE_BACK:
253 default:
254 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
255 break;
256 }
257
258 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
259 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
260 SB_DATA (so, cso->offset_point);
261 SB_DATA (so, cso->offset_line);
262 SB_DATA (so, cso->offset_tri);
263
264 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
265 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
266 SB_DATA (so, fui(cso->offset_scale));
267 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
268 SB_DATA (so, fui(cso->offset_units * 2.0f));
269 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
270 SB_DATA (so, fui(cso->offset_clamp));
271 }
272
273 if (cso->depth_clip)
274 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
275 else
276 reg =
277 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
278 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
279 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
280 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
281
282 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
283 SB_DATA (so, reg);
284
285 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
286 return (void *)so;
287 }
288
289 static void
290 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
291 {
292 struct nvc0_context *nvc0 = nvc0_context(pipe);
293
294 nvc0->rast = hwcso;
295 nvc0->dirty |= NVC0_NEW_RASTERIZER;
296 }
297
298 static void
299 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
300 {
301 FREE(hwcso);
302 }
303
304 static void *
305 nvc0_zsa_state_create(struct pipe_context *pipe,
306 const struct pipe_depth_stencil_alpha_state *cso)
307 {
308 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
309
310 so->pipe = *cso;
311
312 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
313 if (cso->depth.enabled) {
314 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
315 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
316 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
317 }
318
319 if (cso->stencil[0].enabled) {
320 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
321 SB_DATA (so, 1);
322 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
323 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
324 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
325 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
326 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
327 SB_DATA (so, cso->stencil[0].valuemask);
328 SB_DATA (so, cso->stencil[0].writemask);
329 } else {
330 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
331 }
332
333 if (cso->stencil[1].enabled) {
334 assert(cso->stencil[0].enabled);
335 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
336 SB_DATA (so, 1);
337 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
338 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
339 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
340 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
341 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
342 SB_DATA (so, cso->stencil[1].writemask);
343 SB_DATA (so, cso->stencil[1].valuemask);
344 } else
345 if (cso->stencil[0].enabled) {
346 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
347 }
348
349 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
350 if (cso->alpha.enabled) {
351 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
352 SB_DATA (so, fui(cso->alpha.ref_value));
353 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
354 }
355
356 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
357 return (void *)so;
358 }
359
360 static void
361 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
362 {
363 struct nvc0_context *nvc0 = nvc0_context(pipe);
364
365 nvc0->zsa = hwcso;
366 nvc0->dirty |= NVC0_NEW_ZSA;
367 }
368
369 static void
370 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
371 {
372 FREE(hwcso);
373 }
374
375 /* ====================== SAMPLERS AND TEXTURES ================================
376 */
377
378 #define NV50_TSC_WRAP_CASE(n) \
379 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
380
381 static INLINE unsigned
382 nv50_tsc_wrap_mode(unsigned wrap)
383 {
384 switch (wrap) {
385 NV50_TSC_WRAP_CASE(REPEAT);
386 NV50_TSC_WRAP_CASE(MIRROR_REPEAT);
387 NV50_TSC_WRAP_CASE(CLAMP_TO_EDGE);
388 NV50_TSC_WRAP_CASE(CLAMP_TO_BORDER);
389 NV50_TSC_WRAP_CASE(CLAMP);
390 NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_EDGE);
391 NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_BORDER);
392 NV50_TSC_WRAP_CASE(MIRROR_CLAMP);
393 default:
394 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
395 return NV50_TSC_WRAP_REPEAT;
396 }
397 }
398
399 static void
400 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
401 {
402 unsigned s, i;
403
404 for (s = 0; s < 5; ++s)
405 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
406 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
407 nvc0_context(pipe)->samplers[s][i] = NULL;
408
409 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
410
411 FREE(hwcso);
412 }
413
414 static INLINE void
415 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
416 unsigned nr, void **hwcso)
417 {
418 unsigned i;
419
420 for (i = 0; i < nr; ++i) {
421 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
422
423 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
424 if (old)
425 nvc0_screen_tsc_unlock(nvc0->screen, old);
426 }
427 for (; i < nvc0->num_samplers[s]; ++i)
428 if (nvc0->samplers[s][i])
429 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
430
431 nvc0->num_samplers[s] = nr;
432
433 nvc0->dirty |= NVC0_NEW_SAMPLERS;
434 }
435
436 static void
437 nvc0_vp_sampler_states_bind(struct pipe_context *pipe, unsigned nr, void **s)
438 {
439 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
440 }
441
442 static void
443 nvc0_fp_sampler_states_bind(struct pipe_context *pipe, unsigned nr, void **s)
444 {
445 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
446 }
447
448 static void
449 nvc0_gp_sampler_states_bind(struct pipe_context *pipe, unsigned nr, void **s)
450 {
451 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
452 }
453
454 /* NOTE: only called when not referenced anywhere, won't be bound */
455 static void
456 nvc0_sampler_view_destroy(struct pipe_context *pipe,
457 struct pipe_sampler_view *view)
458 {
459 pipe_resource_reference(&view->texture, NULL);
460
461 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
462
463 FREE(nv50_tic_entry(view));
464 }
465
466 static INLINE void
467 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
468 unsigned nr,
469 struct pipe_sampler_view **views)
470 {
471 unsigned i;
472
473 for (i = 0; i < nr; ++i) {
474 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
475 if (old)
476 nvc0_screen_tic_unlock(nvc0->screen, old);
477
478 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
479 }
480
481 for (i = nr; i < nvc0->num_textures[s]; ++i) {
482 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
483 if (!old)
484 continue;
485 nvc0_screen_tic_unlock(nvc0->screen, old);
486
487 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
488 }
489
490 nvc0->num_textures[s] = nr;
491
492 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX);
493
494 nvc0->dirty |= NVC0_NEW_TEXTURES;
495 }
496
497 static void
498 nvc0_vp_set_sampler_views(struct pipe_context *pipe,
499 unsigned nr,
500 struct pipe_sampler_view **views)
501 {
502 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
503 }
504
505 static void
506 nvc0_fp_set_sampler_views(struct pipe_context *pipe,
507 unsigned nr,
508 struct pipe_sampler_view **views)
509 {
510 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
511 }
512
513 static void
514 nvc0_gp_set_sampler_views(struct pipe_context *pipe,
515 unsigned nr,
516 struct pipe_sampler_view **views)
517 {
518 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
519 }
520
521 /* ============================= SHADERS =======================================
522 */
523
524 static void *
525 nvc0_sp_state_create(struct pipe_context *pipe,
526 const struct pipe_shader_state *cso, unsigned type)
527 {
528 struct nvc0_program *prog;
529
530 prog = CALLOC_STRUCT(nvc0_program);
531 if (!prog)
532 return NULL;
533
534 prog->type = type;
535
536 if (cso->tokens)
537 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
538
539 if (cso->stream_output.num_outputs)
540 prog->pipe.stream_output = cso->stream_output;
541
542 return (void *)prog;
543 }
544
545 static void
546 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
547 {
548 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
549
550 nvc0_program_destroy(nvc0_context(pipe), prog);
551
552 FREE((void *)prog->pipe.tokens);
553 FREE(prog);
554 }
555
556 static void *
557 nvc0_vp_state_create(struct pipe_context *pipe,
558 const struct pipe_shader_state *cso)
559 {
560 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
561 }
562
563 static void
564 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
565 {
566 struct nvc0_context *nvc0 = nvc0_context(pipe);
567
568 nvc0->vertprog = hwcso;
569 nvc0->dirty |= NVC0_NEW_VERTPROG;
570 }
571
572 static void *
573 nvc0_fp_state_create(struct pipe_context *pipe,
574 const struct pipe_shader_state *cso)
575 {
576 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
577 }
578
579 static void
580 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
581 {
582 struct nvc0_context *nvc0 = nvc0_context(pipe);
583
584 nvc0->fragprog = hwcso;
585 nvc0->dirty |= NVC0_NEW_FRAGPROG;
586 }
587
588 static void *
589 nvc0_gp_state_create(struct pipe_context *pipe,
590 const struct pipe_shader_state *cso)
591 {
592 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
593 }
594
595 static void
596 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
597 {
598 struct nvc0_context *nvc0 = nvc0_context(pipe);
599
600 nvc0->gmtyprog = hwcso;
601 nvc0->dirty |= NVC0_NEW_GMTYPROG;
602 }
603
604 static void
605 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
606 struct pipe_resource *res)
607 {
608 struct nvc0_context *nvc0 = nvc0_context(pipe);
609
610 switch (shader) {
611 case PIPE_SHADER_VERTEX: shader = 0; break;
612 /*
613 case PIPE_SHADER_TESSELLATION_CONTROL: shader = 1; break;
614 case PIPE_SHADER_TESSELLATION_EVALUATION: shader = 2; break;
615 */
616 case PIPE_SHADER_GEOMETRY: shader = 3; break;
617 case PIPE_SHADER_FRAGMENT: shader = 4; break;
618 default:
619 assert(0);
620 break;
621 }
622
623 if (nvc0->constbuf[shader][index])
624 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_CB(shader, index));
625
626 pipe_resource_reference(&nvc0->constbuf[shader][index], res);
627
628 nvc0->constbuf_dirty[shader] |= 1 << index;
629
630 nvc0->dirty |= NVC0_NEW_CONSTBUF;
631 }
632
633 /* =============================================================================
634 */
635
636 static void
637 nvc0_set_blend_color(struct pipe_context *pipe,
638 const struct pipe_blend_color *bcol)
639 {
640 struct nvc0_context *nvc0 = nvc0_context(pipe);
641
642 nvc0->blend_colour = *bcol;
643 nvc0->dirty |= NVC0_NEW_BLEND_COLOUR;
644 }
645
646 static void
647 nvc0_set_stencil_ref(struct pipe_context *pipe,
648 const struct pipe_stencil_ref *sr)
649 {
650 struct nvc0_context *nvc0 = nvc0_context(pipe);
651
652 nvc0->stencil_ref = *sr;
653 nvc0->dirty |= NVC0_NEW_STENCIL_REF;
654 }
655
656 static void
657 nvc0_set_clip_state(struct pipe_context *pipe,
658 const struct pipe_clip_state *clip)
659 {
660 struct nvc0_context *nvc0 = nvc0_context(pipe);
661
662 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
663
664 nvc0->dirty |= NVC0_NEW_CLIP;
665 }
666
667 static void
668 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
669 {
670 struct nvc0_context *nvc0 = nvc0_context(pipe);
671
672 nvc0->sample_mask = sample_mask;
673 nvc0->dirty |= NVC0_NEW_SAMPLE_MASK;
674 }
675
676
677 static void
678 nvc0_set_framebuffer_state(struct pipe_context *pipe,
679 const struct pipe_framebuffer_state *fb)
680 {
681 struct nvc0_context *nvc0 = nvc0_context(pipe);
682
683 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
684
685 nvc0->framebuffer = *fb;
686 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
687 }
688
689 static void
690 nvc0_set_polygon_stipple(struct pipe_context *pipe,
691 const struct pipe_poly_stipple *stipple)
692 {
693 struct nvc0_context *nvc0 = nvc0_context(pipe);
694
695 nvc0->stipple = *stipple;
696 nvc0->dirty |= NVC0_NEW_STIPPLE;
697 }
698
699 static void
700 nvc0_set_scissor_state(struct pipe_context *pipe,
701 const struct pipe_scissor_state *scissor)
702 {
703 struct nvc0_context *nvc0 = nvc0_context(pipe);
704
705 nvc0->scissor = *scissor;
706 nvc0->dirty |= NVC0_NEW_SCISSOR;
707 }
708
709 static void
710 nvc0_set_viewport_state(struct pipe_context *pipe,
711 const struct pipe_viewport_state *vpt)
712 {
713 struct nvc0_context *nvc0 = nvc0_context(pipe);
714
715 nvc0->viewport = *vpt;
716 nvc0->dirty |= NVC0_NEW_VIEWPORT;
717 }
718
719 static void
720 nvc0_set_vertex_buffers(struct pipe_context *pipe,
721 unsigned count,
722 const struct pipe_vertex_buffer *vb)
723 {
724 struct nvc0_context *nvc0 = nvc0_context(pipe);
725 unsigned i;
726
727 for (i = 0; i < count; ++i)
728 pipe_resource_reference(&nvc0->vtxbuf[i].buffer, vb[i].buffer);
729 for (; i < nvc0->num_vtxbufs; ++i)
730 pipe_resource_reference(&nvc0->vtxbuf[i].buffer, NULL);
731
732 memcpy(nvc0->vtxbuf, vb, sizeof(*vb) * count);
733 nvc0->num_vtxbufs = count;
734
735 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
736
737 nvc0->dirty |= NVC0_NEW_ARRAYS;
738 }
739
740 static void
741 nvc0_set_index_buffer(struct pipe_context *pipe,
742 const struct pipe_index_buffer *ib)
743 {
744 struct nvc0_context *nvc0 = nvc0_context(pipe);
745
746 if (nvc0->idxbuf.buffer)
747 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_IDX);
748
749 if (ib && ib->buffer) {
750 nvc0->dirty |= NVC0_NEW_IDXBUF;
751 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
752 nvc0->idxbuf.offset = ib->offset;
753 nvc0->idxbuf.index_size = ib->index_size;
754 } else {
755 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
756 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
757 }
758 }
759
760 static void
761 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
762 {
763 struct nvc0_context *nvc0 = nvc0_context(pipe);
764
765 nvc0->vertex = hwcso;
766 nvc0->dirty |= NVC0_NEW_VERTEX;
767 }
768
769 static struct pipe_stream_output_target *
770 nvc0_so_target_create(struct pipe_context *pipe,
771 struct pipe_resource *res,
772 unsigned offset, unsigned size)
773 {
774 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
775 if (!targ)
776 return NULL;
777
778 targ->pq = pipe->create_query(pipe, NVC0_QUERY_TFB_BUFFER_OFFSET);
779 if (!targ->pq) {
780 FREE(targ);
781 return NULL;
782 }
783 targ->clean = TRUE;
784
785 targ->pipe.buffer_size = size;
786 targ->pipe.buffer_offset = offset;
787 targ->pipe.context = pipe;
788 targ->pipe.buffer = NULL;
789 pipe_resource_reference(&targ->pipe.buffer, res);
790 pipe_reference_init(&targ->pipe.reference, 1);
791
792 return &targ->pipe;
793 }
794
795 static void
796 nvc0_so_target_destroy(struct pipe_context *pipe,
797 struct pipe_stream_output_target *ptarg)
798 {
799 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
800 pipe->destroy_query(pipe, targ->pq);
801 FREE(targ);
802 }
803
804 static void
805 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
806 unsigned num_targets,
807 struct pipe_stream_output_target **targets,
808 unsigned append_mask)
809 {
810 struct nvc0_context *nvc0 = nvc0_context(pipe);
811 unsigned i;
812 boolean serialize = TRUE;
813
814 assert(num_targets <= 4);
815
816 for (i = 0; i < num_targets; ++i) {
817 if (nvc0->tfbbuf[i] == targets[i] && (append_mask & (1 << i)))
818 continue;
819 nvc0->tfbbuf_dirty |= 1 << i;
820
821 if (nvc0->tfbbuf[i] && nvc0->tfbbuf[i] != targets[i])
822 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
823
824 if (targets[i] && !(append_mask & (1 << i)))
825 nvc0_so_target(targets[i])->clean = TRUE;
826
827 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
828 }
829 for (; i < nvc0->num_tfbbufs; ++i) {
830 nvc0->tfbbuf_dirty |= 1 << i;
831 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
832 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
833 }
834 nvc0->num_tfbbufs = num_targets;
835
836 if (nvc0->tfbbuf_dirty)
837 nvc0->dirty |= NVC0_NEW_TFB_TARGETS;
838 }
839
840 void
841 nvc0_init_state_functions(struct nvc0_context *nvc0)
842 {
843 struct pipe_context *pipe = &nvc0->base.pipe;
844
845 pipe->create_blend_state = nvc0_blend_state_create;
846 pipe->bind_blend_state = nvc0_blend_state_bind;
847 pipe->delete_blend_state = nvc0_blend_state_delete;
848
849 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
850 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
851 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
852
853 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
854 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
855 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
856
857 pipe->create_sampler_state = nv50_sampler_state_create;
858 pipe->delete_sampler_state = nvc0_sampler_state_delete;
859 pipe->bind_vertex_sampler_states = nvc0_vp_sampler_states_bind;
860 pipe->bind_fragment_sampler_states = nvc0_fp_sampler_states_bind;
861 pipe->bind_geometry_sampler_states = nvc0_gp_sampler_states_bind;
862
863 pipe->create_sampler_view = nvc0_create_sampler_view;
864 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
865 pipe->set_vertex_sampler_views = nvc0_vp_set_sampler_views;
866 pipe->set_fragment_sampler_views = nvc0_fp_set_sampler_views;
867 pipe->set_geometry_sampler_views = nvc0_gp_set_sampler_views;
868
869 pipe->create_vs_state = nvc0_vp_state_create;
870 pipe->create_fs_state = nvc0_fp_state_create;
871 pipe->create_gs_state = nvc0_gp_state_create;
872 pipe->bind_vs_state = nvc0_vp_state_bind;
873 pipe->bind_fs_state = nvc0_fp_state_bind;
874 pipe->bind_gs_state = nvc0_gp_state_bind;
875 pipe->delete_vs_state = nvc0_sp_state_delete;
876 pipe->delete_fs_state = nvc0_sp_state_delete;
877 pipe->delete_gs_state = nvc0_sp_state_delete;
878
879 pipe->set_blend_color = nvc0_set_blend_color;
880 pipe->set_stencil_ref = nvc0_set_stencil_ref;
881 pipe->set_clip_state = nvc0_set_clip_state;
882 pipe->set_sample_mask = nvc0_set_sample_mask;
883 pipe->set_constant_buffer = nvc0_set_constant_buffer;
884 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
885 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
886 pipe->set_scissor_state = nvc0_set_scissor_state;
887 pipe->set_viewport_state = nvc0_set_viewport_state;
888
889 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
890 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
891 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
892
893 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
894 pipe->set_index_buffer = nvc0_set_index_buffer;
895
896 pipe->create_stream_output_target = nvc0_so_target_create;
897 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
898 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
899
900 pipe->redefine_user_buffer = u_default_redefine_user_buffer;
901 }
902