2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_defines.h"
24 #include "util/u_helpers.h"
25 #include "util/u_inlines.h"
26 #include "util/u_transfer.h"
28 #include "tgsi/tgsi_parse.h"
30 #include "nvc0_stateobj.h"
31 #include "nvc0_context.h"
33 #include "nvc0_3d.xml.h"
34 #include "nv50/nv50_texture.xml.h"
36 #include "nouveau/nouveau_gldefs.h"
38 static INLINE
uint32_t
39 nvc0_colormask(unsigned mask
)
43 if (mask
& PIPE_MASK_R
)
45 if (mask
& PIPE_MASK_G
)
47 if (mask
& PIPE_MASK_B
)
49 if (mask
& PIPE_MASK_A
)
55 #define NVC0_BLEND_FACTOR_CASE(a, b) \
56 case PIPE_BLENDFACTOR_##a: return NV50_3D_BLEND_FACTOR_##b
58 static INLINE
uint32_t
59 nvc0_blend_fac(unsigned factor
)
62 NVC0_BLEND_FACTOR_CASE(ONE
, ONE
);
63 NVC0_BLEND_FACTOR_CASE(SRC_COLOR
, SRC_COLOR
);
64 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA
, SRC_ALPHA
);
65 NVC0_BLEND_FACTOR_CASE(DST_ALPHA
, DST_ALPHA
);
66 NVC0_BLEND_FACTOR_CASE(DST_COLOR
, DST_COLOR
);
67 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE
, SRC_ALPHA_SATURATE
);
68 NVC0_BLEND_FACTOR_CASE(CONST_COLOR
, CONSTANT_COLOR
);
69 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA
, CONSTANT_ALPHA
);
70 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR
, SRC1_COLOR
);
71 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA
, SRC1_ALPHA
);
72 NVC0_BLEND_FACTOR_CASE(ZERO
, ZERO
);
73 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR
, ONE_MINUS_SRC_COLOR
);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA
, ONE_MINUS_SRC_ALPHA
);
75 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA
, ONE_MINUS_DST_ALPHA
);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR
, ONE_MINUS_DST_COLOR
);
77 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR
, ONE_MINUS_CONSTANT_COLOR
);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA
, ONE_MINUS_CONSTANT_ALPHA
);
79 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR
, ONE_MINUS_SRC1_COLOR
);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA
, ONE_MINUS_SRC1_ALPHA
);
82 return NV50_3D_BLEND_FACTOR_ZERO
;
87 nvc0_blend_state_create(struct pipe_context
*pipe
,
88 const struct pipe_blend_state
*cso
)
90 struct nvc0_blend_stateobj
*so
= CALLOC_STRUCT(nvc0_blend_stateobj
);
92 int r
; /* reference */
95 boolean indep_masks
= FALSE
;
96 boolean indep_funcs
= FALSE
;
100 /* check which states actually have differing values */
101 if (cso
->independent_blend_enable
) {
102 for (r
= 0; r
< 8 && !cso
->rt
[r
].blend_enable
; ++r
);
104 for (i
= r
+ 1; i
< 8; ++i
) {
105 if (!cso
->rt
[i
].blend_enable
)
108 if (cso
->rt
[i
].rgb_func
!= cso
->rt
[r
].rgb_func
||
109 cso
->rt
[i
].rgb_src_factor
!= cso
->rt
[r
].rgb_src_factor
||
110 cso
->rt
[i
].rgb_dst_factor
!= cso
->rt
[r
].rgb_dst_factor
||
111 cso
->rt
[i
].alpha_func
!= cso
->rt
[r
].alpha_func
||
112 cso
->rt
[i
].alpha_src_factor
!= cso
->rt
[r
].alpha_src_factor
||
113 cso
->rt
[i
].alpha_dst_factor
!= cso
->rt
[r
].alpha_dst_factor
) {
119 blend_en
|= (cso
->rt
[i
].blend_enable
? 1 : 0) << i
;
121 for (i
= 1; i
< 8; ++i
) {
122 if (cso
->rt
[i
].colormask
!= cso
->rt
[0].colormask
) {
129 if (cso
->rt
[0].blend_enable
)
133 if (cso
->logicop_enable
) {
134 SB_BEGIN_3D(so
, LOGIC_OP_ENABLE
, 2);
136 SB_DATA (so
, nvgl_logicop_func(cso
->logicop_func
));
138 SB_IMMED_3D(so
, MACRO_BLEND_ENABLES
, 0);
140 SB_IMMED_3D(so
, LOGIC_OP_ENABLE
, 0);
142 SB_IMMED_3D(so
, BLEND_INDEPENDENT
, indep_funcs
);
143 SB_IMMED_3D(so
, MACRO_BLEND_ENABLES
, blend_en
);
145 for (i
= 0; i
< 8; ++i
) {
146 if (cso
->rt
[i
].blend_enable
) {
147 SB_BEGIN_3D(so
, IBLEND_EQUATION_RGB(i
), 6);
148 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[i
].rgb_func
));
149 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].rgb_src_factor
));
150 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].rgb_dst_factor
));
151 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[i
].alpha_func
));
152 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].alpha_src_factor
));
153 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[i
].alpha_dst_factor
));
158 SB_BEGIN_3D(so
, BLEND_EQUATION_RGB
, 5);
159 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[r
].rgb_func
));
160 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].rgb_src_factor
));
161 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].rgb_dst_factor
));
162 SB_DATA (so
, nvgl_blend_eqn(cso
->rt
[r
].alpha_func
));
163 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].alpha_src_factor
));
164 SB_BEGIN_3D(so
, BLEND_FUNC_DST_ALPHA
, 1);
165 SB_DATA (so
, nvc0_blend_fac(cso
->rt
[r
].alpha_dst_factor
));
168 SB_IMMED_3D(so
, COLOR_MASK_COMMON
, !indep_masks
);
170 SB_BEGIN_3D(so
, COLOR_MASK(0), 8);
171 for (i
= 0; i
< 8; ++i
)
172 SB_DATA(so
, nvc0_colormask(cso
->rt
[i
].colormask
));
174 SB_BEGIN_3D(so
, COLOR_MASK(0), 1);
175 SB_DATA (so
, nvc0_colormask(cso
->rt
[0].colormask
));
180 if (cso
->alpha_to_coverage
)
181 ms
|= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE
;
182 if (cso
->alpha_to_one
)
183 ms
|= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE
;
185 SB_BEGIN_3D(so
, MULTISAMPLE_CTRL
, 1);
188 assert(so
->size
<= (sizeof(so
->state
) / sizeof(so
->state
[0])));
193 nvc0_blend_state_bind(struct pipe_context
*pipe
, void *hwcso
)
195 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
198 nvc0
->dirty
|= NVC0_NEW_BLEND
;
202 nvc0_blend_state_delete(struct pipe_context
*pipe
, void *hwcso
)
207 /* NOTE: ignoring line_last_pixel, using FALSE (set on screen init) */
209 nvc0_rasterizer_state_create(struct pipe_context
*pipe
,
210 const struct pipe_rasterizer_state
*cso
)
212 struct nvc0_rasterizer_stateobj
*so
;
215 so
= CALLOC_STRUCT(nvc0_rasterizer_stateobj
);
220 /* Scissor enables are handled in scissor state, we will not want to
221 * always emit 16 commands, one for each scissor rectangle, here.
224 SB_BEGIN_3D(so
, SHADE_MODEL
, 1);
225 SB_DATA (so
, cso
->flatshade
? NVC0_3D_SHADE_MODEL_FLAT
:
226 NVC0_3D_SHADE_MODEL_SMOOTH
);
227 SB_IMMED_3D(so
, PROVOKING_VERTEX_LAST
, !cso
->flatshade_first
);
228 SB_IMMED_3D(so
, VERTEX_TWO_SIDE_ENABLE
, cso
->light_twoside
);
230 SB_IMMED_3D(so
, VERT_COLOR_CLAMP_EN
, cso
->clamp_vertex_color
);
231 SB_BEGIN_3D(so
, FRAG_COLOR_CLAMP_EN
, 1);
232 SB_DATA (so
, cso
->clamp_fragment_color
? 0x11111111 : 0x00000000);
234 SB_IMMED_3D(so
, MULTISAMPLE_ENABLE
, cso
->multisample
);
236 SB_IMMED_3D(so
, LINE_SMOOTH_ENABLE
, cso
->line_smooth
);
237 if (cso
->line_smooth
)
238 SB_BEGIN_3D(so
, LINE_WIDTH_SMOOTH
, 1);
240 SB_BEGIN_3D(so
, LINE_WIDTH_ALIASED
, 1);
241 SB_DATA (so
, fui(cso
->line_width
));
243 SB_IMMED_3D(so
, LINE_STIPPLE_ENABLE
, cso
->line_stipple_enable
);
244 if (cso
->line_stipple_enable
) {
245 SB_BEGIN_3D(so
, LINE_STIPPLE_PATTERN
, 1);
246 SB_DATA (so
, (cso
->line_stipple_pattern
<< 8) |
247 cso
->line_stipple_factor
);
251 SB_IMMED_3D(so
, VP_POINT_SIZE_EN
, cso
->point_size_per_vertex
);
252 if (!cso
->point_size_per_vertex
) {
253 SB_BEGIN_3D(so
, POINT_SIZE
, 1);
254 SB_DATA (so
, fui(cso
->point_size
));
257 reg
= (cso
->sprite_coord_mode
== PIPE_SPRITE_COORD_UPPER_LEFT
) ?
258 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT
:
259 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT
;
261 SB_BEGIN_3D(so
, POINT_COORD_REPLACE
, 1);
262 SB_DATA (so
, ((cso
->sprite_coord_enable
& 0xff) << 3) | reg
);
263 SB_IMMED_3D(so
, POINT_SPRITE_ENABLE
, cso
->point_quad_rasterization
);
264 SB_IMMED_3D(so
, POINT_SMOOTH_ENABLE
, cso
->point_smooth
);
266 SB_BEGIN_3D(so
, MACRO_POLYGON_MODE_FRONT
, 1);
267 SB_DATA (so
, nvgl_polygon_mode(cso
->fill_front
));
268 SB_BEGIN_3D(so
, MACRO_POLYGON_MODE_BACK
, 1);
269 SB_DATA (so
, nvgl_polygon_mode(cso
->fill_back
));
270 SB_IMMED_3D(so
, POLYGON_SMOOTH_ENABLE
, cso
->poly_smooth
);
272 SB_BEGIN_3D(so
, CULL_FACE_ENABLE
, 3);
273 SB_DATA (so
, cso
->cull_face
!= PIPE_FACE_NONE
);
274 SB_DATA (so
, cso
->front_ccw
? NVC0_3D_FRONT_FACE_CCW
:
275 NVC0_3D_FRONT_FACE_CW
);
276 switch (cso
->cull_face
) {
277 case PIPE_FACE_FRONT_AND_BACK
:
278 SB_DATA(so
, NVC0_3D_CULL_FACE_FRONT_AND_BACK
);
280 case PIPE_FACE_FRONT
:
281 SB_DATA(so
, NVC0_3D_CULL_FACE_FRONT
);
285 SB_DATA(so
, NVC0_3D_CULL_FACE_BACK
);
289 SB_IMMED_3D(so
, POLYGON_STIPPLE_ENABLE
, cso
->poly_stipple_enable
);
290 SB_BEGIN_3D(so
, POLYGON_OFFSET_POINT_ENABLE
, 3);
291 SB_DATA (so
, cso
->offset_point
);
292 SB_DATA (so
, cso
->offset_line
);
293 SB_DATA (so
, cso
->offset_tri
);
295 if (cso
->offset_point
|| cso
->offset_line
|| cso
->offset_tri
) {
296 SB_BEGIN_3D(so
, POLYGON_OFFSET_FACTOR
, 1);
297 SB_DATA (so
, fui(cso
->offset_scale
));
298 SB_BEGIN_3D(so
, POLYGON_OFFSET_UNITS
, 1);
299 SB_DATA (so
, fui(cso
->offset_units
* 2.0f
));
300 SB_BEGIN_3D(so
, POLYGON_OFFSET_CLAMP
, 1);
301 SB_DATA (so
, fui(cso
->offset_clamp
));
305 reg
= NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
;
308 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1
|
309 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR
|
310 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR
|
311 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2
;
313 SB_BEGIN_3D(so
, VIEW_VOLUME_CLIP_CTRL
, 1);
316 assert(so
->size
<= (sizeof(so
->state
) / sizeof(so
->state
[0])));
321 nvc0_rasterizer_state_bind(struct pipe_context
*pipe
, void *hwcso
)
323 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
326 nvc0
->dirty
|= NVC0_NEW_RASTERIZER
;
330 nvc0_rasterizer_state_delete(struct pipe_context
*pipe
, void *hwcso
)
336 nvc0_zsa_state_create(struct pipe_context
*pipe
,
337 const struct pipe_depth_stencil_alpha_state
*cso
)
339 struct nvc0_zsa_stateobj
*so
= CALLOC_STRUCT(nvc0_zsa_stateobj
);
343 SB_IMMED_3D(so
, DEPTH_TEST_ENABLE
, cso
->depth
.enabled
);
344 if (cso
->depth
.enabled
) {
345 SB_IMMED_3D(so
, DEPTH_WRITE_ENABLE
, cso
->depth
.writemask
);
346 SB_BEGIN_3D(so
, DEPTH_TEST_FUNC
, 1);
347 SB_DATA (so
, nvgl_comparison_op(cso
->depth
.func
));
350 if (cso
->stencil
[0].enabled
) {
351 SB_BEGIN_3D(so
, STENCIL_ENABLE
, 5);
353 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[0].fail_op
));
354 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[0].zfail_op
));
355 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[0].zpass_op
));
356 SB_DATA (so
, nvgl_comparison_op(cso
->stencil
[0].func
));
357 SB_BEGIN_3D(so
, STENCIL_FRONT_FUNC_MASK
, 2);
358 SB_DATA (so
, cso
->stencil
[0].valuemask
);
359 SB_DATA (so
, cso
->stencil
[0].writemask
);
361 SB_IMMED_3D(so
, STENCIL_ENABLE
, 0);
364 if (cso
->stencil
[1].enabled
) {
365 assert(cso
->stencil
[0].enabled
);
366 SB_BEGIN_3D(so
, STENCIL_TWO_SIDE_ENABLE
, 5);
368 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[1].fail_op
));
369 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[1].zfail_op
));
370 SB_DATA (so
, nvgl_stencil_op(cso
->stencil
[1].zpass_op
));
371 SB_DATA (so
, nvgl_comparison_op(cso
->stencil
[1].func
));
372 SB_BEGIN_3D(so
, STENCIL_BACK_MASK
, 2);
373 SB_DATA (so
, cso
->stencil
[1].writemask
);
374 SB_DATA (so
, cso
->stencil
[1].valuemask
);
376 if (cso
->stencil
[0].enabled
) {
377 SB_IMMED_3D(so
, STENCIL_TWO_SIDE_ENABLE
, 0);
380 SB_IMMED_3D(so
, ALPHA_TEST_ENABLE
, cso
->alpha
.enabled
);
381 if (cso
->alpha
.enabled
) {
382 SB_BEGIN_3D(so
, ALPHA_TEST_REF
, 2);
383 SB_DATA (so
, fui(cso
->alpha
.ref_value
));
384 SB_DATA (so
, nvgl_comparison_op(cso
->alpha
.func
));
387 assert(so
->size
<= (sizeof(so
->state
) / sizeof(so
->state
[0])));
392 nvc0_zsa_state_bind(struct pipe_context
*pipe
, void *hwcso
)
394 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
397 nvc0
->dirty
|= NVC0_NEW_ZSA
;
401 nvc0_zsa_state_delete(struct pipe_context
*pipe
, void *hwcso
)
406 /* ====================== SAMPLERS AND TEXTURES ================================
409 #define NV50_TSC_WRAP_CASE(n) \
410 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
412 static INLINE
unsigned
413 nv50_tsc_wrap_mode(unsigned wrap
)
416 NV50_TSC_WRAP_CASE(REPEAT
);
417 NV50_TSC_WRAP_CASE(MIRROR_REPEAT
);
418 NV50_TSC_WRAP_CASE(CLAMP_TO_EDGE
);
419 NV50_TSC_WRAP_CASE(CLAMP_TO_BORDER
);
420 NV50_TSC_WRAP_CASE(CLAMP
);
421 NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_EDGE
);
422 NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_BORDER
);
423 NV50_TSC_WRAP_CASE(MIRROR_CLAMP
);
425 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap
);
426 return NV50_TSC_WRAP_REPEAT
;
431 nvc0_sampler_state_delete(struct pipe_context
*pipe
, void *hwcso
)
435 for (s
= 0; s
< 5; ++s
)
436 for (i
= 0; i
< nvc0_context(pipe
)->num_samplers
[s
]; ++i
)
437 if (nvc0_context(pipe
)->samplers
[s
][i
] == hwcso
)
438 nvc0_context(pipe
)->samplers
[s
][i
] = NULL
;
440 nvc0_screen_tsc_free(nvc0_context(pipe
)->screen
, nv50_tsc_entry(hwcso
));
446 nvc0_stage_sampler_states_bind(struct nvc0_context
*nvc0
, int s
,
447 unsigned nr
, void **hwcso
)
451 for (i
= 0; i
< nr
; ++i
) {
452 struct nv50_tsc_entry
*old
= nvc0
->samplers
[s
][i
];
456 nvc0
->samplers_dirty
[s
] |= 1 << i
;
458 nvc0
->samplers
[s
][i
] = nv50_tsc_entry(hwcso
[i
]);
460 nvc0_screen_tsc_unlock(nvc0
->screen
, old
);
462 for (; i
< nvc0
->num_samplers
[s
]; ++i
) {
463 if (nvc0
->samplers
[s
][i
]) {
464 nvc0_screen_tsc_unlock(nvc0
->screen
, nvc0
->samplers
[s
][i
]);
465 nvc0
->samplers
[s
][i
] = NULL
;
469 nvc0
->num_samplers
[s
] = nr
;
471 nvc0
->dirty
|= NVC0_NEW_SAMPLERS
;
475 nvc0_vp_sampler_states_bind(struct pipe_context
*pipe
, unsigned nr
, void **s
)
477 nvc0_stage_sampler_states_bind(nvc0_context(pipe
), 0, nr
, s
);
481 nvc0_fp_sampler_states_bind(struct pipe_context
*pipe
, unsigned nr
, void **s
)
483 nvc0_stage_sampler_states_bind(nvc0_context(pipe
), 4, nr
, s
);
487 nvc0_gp_sampler_states_bind(struct pipe_context
*pipe
, unsigned nr
, void **s
)
489 nvc0_stage_sampler_states_bind(nvc0_context(pipe
), 3, nr
, s
);
493 nvc0_stage_sampler_states_bind_range(struct nvc0_context
*nvc0
,
495 unsigned start
, unsigned nr
, void **cso
)
497 const unsigned end
= start
+ nr
;
502 for (i
= start
; i
< end
; ++i
) {
503 const unsigned p
= i
- start
;
506 if (cso
[p
] == nvc0
->samplers
[s
][i
])
508 nvc0
->samplers_dirty
[s
] |= 1 << i
;
510 if (nvc0
->samplers
[s
][i
])
511 nvc0_screen_tsc_unlock(nvc0
->screen
, nvc0
->samplers
[s
][i
]);
512 nvc0
->samplers
[s
][i
] = cso
[p
];
515 for (i
= start
; i
< end
; ++i
) {
516 if (nvc0
->samplers
[s
][i
]) {
517 nvc0_screen_tsc_unlock(nvc0
->screen
, nvc0
->samplers
[s
][i
]);
518 nvc0
->samplers
[s
][i
] = NULL
;
519 nvc0
->samplers_dirty
[s
] |= 1 << i
;
524 if (nvc0
->num_samplers
[s
] <= end
) {
525 if (last_valid
< 0) {
526 for (i
= start
; i
&& !nvc0
->samplers
[s
][i
- 1]; --i
);
527 nvc0
->num_samplers
[s
] = i
;
529 nvc0
->num_samplers
[s
] = last_valid
+ 1;
535 nvc0_cp_sampler_states_bind(struct pipe_context
*pipe
,
536 unsigned start
, unsigned nr
, void **cso
)
538 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe
), 5, start
, nr
, cso
);
540 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_SAMPLERS
;
543 /* NOTE: only called when not referenced anywhere, won't be bound */
545 nvc0_sampler_view_destroy(struct pipe_context
*pipe
,
546 struct pipe_sampler_view
*view
)
548 pipe_resource_reference(&view
->texture
, NULL
);
550 nvc0_screen_tic_free(nvc0_context(pipe
)->screen
, nv50_tic_entry(view
));
552 FREE(nv50_tic_entry(view
));
556 nvc0_stage_set_sampler_views(struct nvc0_context
*nvc0
, int s
,
558 struct pipe_sampler_view
**views
)
562 for (i
= 0; i
< nr
; ++i
) {
563 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
565 if (views
[i
] == nvc0
->textures
[s
][i
])
567 nvc0
->textures_dirty
[s
] |= 1 << i
;
570 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_TEX(s
, i
));
571 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
574 pipe_sampler_view_reference(&nvc0
->textures
[s
][i
], views
[i
]);
577 for (i
= nr
; i
< nvc0
->num_textures
[s
]; ++i
) {
578 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
580 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_TEX(s
, i
));
581 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
582 pipe_sampler_view_reference(&nvc0
->textures
[s
][i
], NULL
);
586 nvc0
->num_textures
[s
] = nr
;
588 nvc0
->dirty
|= NVC0_NEW_TEXTURES
;
592 nvc0_vp_set_sampler_views(struct pipe_context
*pipe
,
594 struct pipe_sampler_view
**views
)
596 nvc0_stage_set_sampler_views(nvc0_context(pipe
), 0, nr
, views
);
600 nvc0_fp_set_sampler_views(struct pipe_context
*pipe
,
602 struct pipe_sampler_view
**views
)
604 nvc0_stage_set_sampler_views(nvc0_context(pipe
), 4, nr
, views
);
608 nvc0_gp_set_sampler_views(struct pipe_context
*pipe
,
610 struct pipe_sampler_view
**views
)
612 nvc0_stage_set_sampler_views(nvc0_context(pipe
), 3, nr
, views
);
616 nvc0_stage_set_sampler_views_range(struct nvc0_context
*nvc0
, const unsigned s
,
617 unsigned start
, unsigned nr
,
618 struct pipe_sampler_view
**views
)
620 struct nouveau_bufctx
*bctx
= (s
== 5) ? nvc0
->bufctx_cp
: nvc0
->bufctx_3d
;
621 const unsigned end
= start
+ nr
;
622 const unsigned bin
= (s
== 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_TEX(s
, 0);
627 for (i
= start
; i
< end
; ++i
) {
628 const unsigned p
= i
- start
;
631 if (views
[p
] == nvc0
->textures
[s
][i
])
633 nvc0
->textures_dirty
[s
] |= 1 << i
;
635 if (nvc0
->textures
[s
][i
]) {
636 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
637 nouveau_bufctx_reset(bctx
, bin
+ i
);
638 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
640 pipe_sampler_view_reference(&nvc0
->textures
[s
][i
], views
[p
]);
643 for (i
= start
; i
< end
; ++i
) {
644 struct nv50_tic_entry
*old
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
647 nvc0
->textures_dirty
[s
] |= 1 << i
;
649 nvc0_screen_tic_unlock(nvc0
->screen
, old
);
650 pipe_sampler_view_reference(&nvc0
->textures
[s
][i
], NULL
);
651 nouveau_bufctx_reset(bctx
, bin
+ i
);
655 if (nvc0
->num_textures
[s
] <= end
) {
656 if (last_valid
< 0) {
657 for (i
= start
; i
&& !nvc0
->textures
[s
][i
- 1]; --i
);
658 nvc0
->num_textures
[s
] = i
;
660 nvc0
->num_textures
[s
] = last_valid
+ 1;
666 nvc0_cp_set_sampler_views(struct pipe_context
*pipe
,
667 unsigned start
, unsigned nr
,
668 struct pipe_sampler_view
**views
)
670 nvc0_stage_set_sampler_views_range(nvc0_context(pipe
), 5, start
, nr
, views
);
672 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_TEXTURES
;
676 /* ============================= SHADERS =======================================
680 nvc0_sp_state_create(struct pipe_context
*pipe
,
681 const struct pipe_shader_state
*cso
, unsigned type
)
683 struct nvc0_program
*prog
;
685 prog
= CALLOC_STRUCT(nvc0_program
);
692 prog
->pipe
.tokens
= tgsi_dup_tokens(cso
->tokens
);
694 if (cso
->stream_output
.num_outputs
)
695 prog
->pipe
.stream_output
= cso
->stream_output
;
701 nvc0_sp_state_delete(struct pipe_context
*pipe
, void *hwcso
)
703 struct nvc0_program
*prog
= (struct nvc0_program
*)hwcso
;
705 nvc0_program_destroy(nvc0_context(pipe
), prog
);
707 FREE((void *)prog
->pipe
.tokens
);
712 nvc0_vp_state_create(struct pipe_context
*pipe
,
713 const struct pipe_shader_state
*cso
)
715 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_VERTEX
);
719 nvc0_vp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
721 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
723 nvc0
->vertprog
= hwcso
;
724 nvc0
->dirty
|= NVC0_NEW_VERTPROG
;
728 nvc0_fp_state_create(struct pipe_context
*pipe
,
729 const struct pipe_shader_state
*cso
)
731 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_FRAGMENT
);
735 nvc0_fp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
737 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
739 nvc0
->fragprog
= hwcso
;
740 nvc0
->dirty
|= NVC0_NEW_FRAGPROG
;
744 nvc0_gp_state_create(struct pipe_context
*pipe
,
745 const struct pipe_shader_state
*cso
)
747 return nvc0_sp_state_create(pipe
, cso
, PIPE_SHADER_GEOMETRY
);
751 nvc0_gp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
753 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
755 nvc0
->gmtyprog
= hwcso
;
756 nvc0
->dirty
|= NVC0_NEW_GMTYPROG
;
760 nvc0_cp_state_create(struct pipe_context
*pipe
,
761 const struct pipe_compute_state
*cso
)
763 struct nvc0_program
*prog
;
765 prog
= CALLOC_STRUCT(nvc0_program
);
768 prog
->type
= PIPE_SHADER_COMPUTE
;
770 prog
->cp
.smem_size
= cso
->req_local_mem
;
771 prog
->cp
.lmem_size
= cso
->req_private_mem
;
772 prog
->parm_size
= cso
->req_input_mem
;
774 prog
->pipe
.tokens
= tgsi_dup_tokens((const struct tgsi_token
*)cso
->prog
);
780 nvc0_cp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
782 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
784 nvc0
->compprog
= hwcso
;
785 nvc0
->dirty_cp
|= NVC0_NEW_CP_PROGRAM
;
789 nvc0_set_constant_buffer(struct pipe_context
*pipe
, uint shader
, uint index
,
790 struct pipe_constant_buffer
*cb
)
792 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
793 struct pipe_resource
*res
= cb
? cb
->buffer
: NULL
;
794 const unsigned s
= nvc0_shader_stage(shader
);
795 const unsigned i
= index
;
797 if (unlikely(shader
== PIPE_SHADER_COMPUTE
)) {
798 assert(!cb
|| !cb
->user_buffer
);
799 if (nvc0
->constbuf
[s
][i
].u
.buf
)
800 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_CB(i
));
802 nvc0
->dirty_cp
|= NVC0_NEW_CP_CONSTBUF
;
804 if (nvc0
->constbuf
[s
][i
].user
)
805 nvc0
->constbuf
[s
][i
].u
.buf
= NULL
;
807 if (nvc0
->constbuf
[s
][i
].u
.buf
)
808 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_CB(s
, i
));
810 nvc0
->dirty
|= NVC0_NEW_CONSTBUF
;
812 nvc0
->constbuf_dirty
[s
] |= 1 << i
;
814 pipe_resource_reference(&nvc0
->constbuf
[s
][i
].u
.buf
, res
);
816 nvc0
->constbuf
[s
][i
].user
= (cb
&& cb
->user_buffer
) ? TRUE
: FALSE
;
817 if (nvc0
->constbuf
[s
][i
].user
) {
818 nvc0
->constbuf
[s
][i
].u
.data
= cb
->user_buffer
;
819 nvc0
->constbuf
[s
][i
].size
= cb
->buffer_size
;
822 nvc0
->constbuf
[s
][i
].offset
= cb
->buffer_offset
;
823 nvc0
->constbuf
[s
][i
].size
= align(cb
->buffer_size
, 0x100);
827 /* =============================================================================
831 nvc0_set_blend_color(struct pipe_context
*pipe
,
832 const struct pipe_blend_color
*bcol
)
834 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
836 nvc0
->blend_colour
= *bcol
;
837 nvc0
->dirty
|= NVC0_NEW_BLEND_COLOUR
;
841 nvc0_set_stencil_ref(struct pipe_context
*pipe
,
842 const struct pipe_stencil_ref
*sr
)
844 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
846 nvc0
->stencil_ref
= *sr
;
847 nvc0
->dirty
|= NVC0_NEW_STENCIL_REF
;
851 nvc0_set_clip_state(struct pipe_context
*pipe
,
852 const struct pipe_clip_state
*clip
)
854 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
856 memcpy(nvc0
->clip
.ucp
, clip
->ucp
, sizeof(clip
->ucp
));
858 nvc0
->dirty
|= NVC0_NEW_CLIP
;
862 nvc0_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
864 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
866 nvc0
->sample_mask
= sample_mask
;
867 nvc0
->dirty
|= NVC0_NEW_SAMPLE_MASK
;
872 nvc0_set_framebuffer_state(struct pipe_context
*pipe
,
873 const struct pipe_framebuffer_state
*fb
)
875 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
878 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_FB
);
880 for (i
= 0; i
< fb
->nr_cbufs
; ++i
)
881 pipe_surface_reference(&nvc0
->framebuffer
.cbufs
[i
], fb
->cbufs
[i
]);
882 for (; i
< nvc0
->framebuffer
.nr_cbufs
; ++i
)
883 pipe_surface_reference(&nvc0
->framebuffer
.cbufs
[i
], NULL
);
885 nvc0
->framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
887 nvc0
->framebuffer
.width
= fb
->width
;
888 nvc0
->framebuffer
.height
= fb
->height
;
890 pipe_surface_reference(&nvc0
->framebuffer
.zsbuf
, fb
->zsbuf
);
892 nvc0
->dirty
|= NVC0_NEW_FRAMEBUFFER
;
896 nvc0_set_polygon_stipple(struct pipe_context
*pipe
,
897 const struct pipe_poly_stipple
*stipple
)
899 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
901 nvc0
->stipple
= *stipple
;
902 nvc0
->dirty
|= NVC0_NEW_STIPPLE
;
906 nvc0_set_scissor_state(struct pipe_context
*pipe
,
907 const struct pipe_scissor_state
*scissor
)
909 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
911 nvc0
->scissor
= *scissor
;
912 nvc0
->dirty
|= NVC0_NEW_SCISSOR
;
916 nvc0_set_viewport_state(struct pipe_context
*pipe
,
917 const struct pipe_viewport_state
*vpt
)
919 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
921 nvc0
->viewport
= *vpt
;
922 nvc0
->dirty
|= NVC0_NEW_VIEWPORT
;
926 nvc0_set_vertex_buffers(struct pipe_context
*pipe
,
927 unsigned start_slot
, unsigned count
,
928 const struct pipe_vertex_buffer
*vb
)
930 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
933 util_set_vertex_buffers_count(nvc0
->vtxbuf
, &nvc0
->num_vtxbufs
, vb
,
937 nvc0
->vbo_user
&= ~(((1ull << count
) - 1) << start_slot
);
938 nvc0
->constant_vbos
&= ~(((1ull << count
) - 1) << start_slot
);
942 for (i
= 0; i
< count
; ++i
) {
943 unsigned dst_index
= start_slot
+ i
;
945 if (vb
[i
].user_buffer
) {
946 nvc0
->vbo_user
|= 1 << dst_index
;
948 nvc0
->constant_vbos
|= 1 << dst_index
;
950 nvc0
->constant_vbos
&= ~(1 << dst_index
);
952 nvc0
->vbo_user
&= ~(1 << dst_index
);
953 nvc0
->constant_vbos
&= ~(1 << dst_index
);
957 nvc0
->dirty
|= NVC0_NEW_ARRAYS
;
958 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_VTX
);
962 nvc0_set_index_buffer(struct pipe_context
*pipe
,
963 const struct pipe_index_buffer
*ib
)
965 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
967 if (nvc0
->idxbuf
.buffer
)
968 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_IDX
);
971 pipe_resource_reference(&nvc0
->idxbuf
.buffer
, ib
->buffer
);
972 nvc0
->idxbuf
.index_size
= ib
->index_size
;
974 nvc0
->idxbuf
.offset
= ib
->offset
;
975 nvc0
->dirty
|= NVC0_NEW_IDXBUF
;
977 nvc0
->idxbuf
.user_buffer
= ib
->user_buffer
;
978 nvc0
->dirty
&= ~NVC0_NEW_IDXBUF
;
981 nvc0
->dirty
&= ~NVC0_NEW_IDXBUF
;
982 pipe_resource_reference(&nvc0
->idxbuf
.buffer
, NULL
);
987 nvc0_vertex_state_bind(struct pipe_context
*pipe
, void *hwcso
)
989 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
991 nvc0
->vertex
= hwcso
;
992 nvc0
->dirty
|= NVC0_NEW_VERTEX
;
995 static struct pipe_stream_output_target
*
996 nvc0_so_target_create(struct pipe_context
*pipe
,
997 struct pipe_resource
*res
,
998 unsigned offset
, unsigned size
)
1000 struct nvc0_so_target
*targ
= MALLOC_STRUCT(nvc0_so_target
);
1004 targ
->pq
= pipe
->create_query(pipe
, NVC0_QUERY_TFB_BUFFER_OFFSET
);
1011 targ
->pipe
.buffer_size
= size
;
1012 targ
->pipe
.buffer_offset
= offset
;
1013 targ
->pipe
.context
= pipe
;
1014 targ
->pipe
.buffer
= NULL
;
1015 pipe_resource_reference(&targ
->pipe
.buffer
, res
);
1016 pipe_reference_init(&targ
->pipe
.reference
, 1);
1022 nvc0_so_target_destroy(struct pipe_context
*pipe
,
1023 struct pipe_stream_output_target
*ptarg
)
1025 struct nvc0_so_target
*targ
= nvc0_so_target(ptarg
);
1026 pipe
->destroy_query(pipe
, targ
->pq
);
1027 pipe_resource_reference(&targ
->pipe
.buffer
, NULL
);
1032 nvc0_set_transform_feedback_targets(struct pipe_context
*pipe
,
1033 unsigned num_targets
,
1034 struct pipe_stream_output_target
**targets
,
1035 unsigned append_mask
)
1037 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
1039 boolean serialize
= TRUE
;
1041 assert(num_targets
<= 4);
1043 for (i
= 0; i
< num_targets
; ++i
) {
1044 if (nvc0
->tfbbuf
[i
] == targets
[i
] && (append_mask
& (1 << i
)))
1046 nvc0
->tfbbuf_dirty
|= 1 << i
;
1048 if (nvc0
->tfbbuf
[i
] && nvc0
->tfbbuf
[i
] != targets
[i
])
1049 nvc0_so_target_save_offset(pipe
, nvc0
->tfbbuf
[i
], i
, &serialize
);
1051 if (targets
[i
] && !(append_mask
& (1 << i
)))
1052 nvc0_so_target(targets
[i
])->clean
= TRUE
;
1054 pipe_so_target_reference(&nvc0
->tfbbuf
[i
], targets
[i
]);
1056 for (; i
< nvc0
->num_tfbbufs
; ++i
) {
1057 nvc0
->tfbbuf_dirty
|= 1 << i
;
1058 nvc0_so_target_save_offset(pipe
, nvc0
->tfbbuf
[i
], i
, &serialize
);
1059 pipe_so_target_reference(&nvc0
->tfbbuf
[i
], NULL
);
1061 nvc0
->num_tfbbufs
= num_targets
;
1063 if (nvc0
->tfbbuf_dirty
)
1064 nvc0
->dirty
|= NVC0_NEW_TFB_TARGETS
;
1068 nvc0_bind_surfaces_range(struct nvc0_context
*nvc0
, const unsigned t
,
1069 unsigned start
, unsigned nr
,
1070 struct pipe_surface
**psurfaces
)
1072 const unsigned end
= start
+ nr
;
1073 const unsigned mask
= ((1 << nr
) - 1) << start
;
1077 for (i
= start
; i
< end
; ++i
) {
1078 const unsigned p
= i
- start
;
1080 nvc0
->surfaces_valid
[t
] |= (1 << i
);
1082 nvc0
->surfaces_valid
[t
] &= ~(1 << i
);
1083 pipe_surface_reference(&nvc0
->surfaces
[t
][i
], psurfaces
[p
]);
1086 for (i
= start
; i
< end
; ++i
)
1087 pipe_surface_reference(&nvc0
->surfaces
[t
][i
], NULL
);
1088 nvc0
->surfaces_valid
[t
] &= ~mask
;
1090 nvc0
->surfaces_dirty
[t
] |= mask
;
1093 nouveau_bufctx_reset(nvc0
->bufctx_3d
, NVC0_BIND_SUF
);
1095 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_SUF
);
1099 nvc0_set_compute_resources(struct pipe_context
*pipe
,
1100 unsigned start
, unsigned nr
,
1101 struct pipe_surface
**resources
)
1103 nvc0_bind_surfaces_range(nvc0_context(pipe
), 1, start
, nr
, resources
);
1105 nvc0_context(pipe
)->dirty_cp
|= NVC0_NEW_CP_SURFACES
;
1109 nvc0_set_shader_resources(struct pipe_context
*pipe
,
1110 unsigned start
, unsigned nr
,
1111 struct pipe_surface
**resources
)
1113 nvc0_bind_surfaces_range(nvc0_context(pipe
), 0, start
, nr
, resources
);
1115 nvc0_context(pipe
)->dirty
|= NVC0_NEW_SURFACES
;
1119 nvc0_set_global_handle(uint32_t *phandle
, struct pipe_resource
*res
)
1121 struct nv04_resource
*buf
= nv04_resource(res
);
1123 uint64_t limit
= (buf
->address
+ buf
->base
.width0
) - 1;
1124 if (limit
< (1ULL << 32)) {
1125 *phandle
= (uint32_t)buf
->address
;
1127 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1128 "resource not contained within 32-bit address space !\n");
1137 nvc0_set_global_bindings(struct pipe_context
*pipe
,
1138 unsigned start
, unsigned nr
,
1139 struct pipe_resource
**resources
,
1142 struct nvc0_context
*nvc0
= nvc0_context(pipe
);
1143 struct pipe_resource
**ptr
;
1145 const unsigned end
= start
+ nr
;
1147 if (nvc0
->global_residents
.size
<= (end
* sizeof(struct pipe_resource
*))) {
1148 const unsigned old_size
= nvc0
->global_residents
.size
;
1149 const unsigned req_size
= end
* sizeof(struct pipe_resource
*);
1150 util_dynarray_resize(&nvc0
->global_residents
, req_size
);
1151 memset((uint8_t *)nvc0
->global_residents
.data
+ old_size
, 0,
1152 req_size
- old_size
);
1156 ptr
= util_dynarray_element(
1157 &nvc0
->global_residents
, struct pipe_resource
*, start
);
1158 for (i
= 0; i
< nr
; ++i
) {
1159 pipe_resource_reference(&ptr
[i
], resources
[i
]);
1160 nvc0_set_global_handle(handles
[i
], resources
[i
]);
1163 ptr
= util_dynarray_element(
1164 &nvc0
->global_residents
, struct pipe_resource
*, start
);
1165 for (i
= 0; i
< nr
; ++i
)
1166 pipe_resource_reference(&ptr
[i
], NULL
);
1169 nouveau_bufctx_reset(nvc0
->bufctx_cp
, NVC0_BIND_CP_GLOBAL
);
1171 nvc0
->dirty_cp
= NVC0_NEW_CP_GLOBALS
;
1175 nvc0_init_state_functions(struct nvc0_context
*nvc0
)
1177 struct pipe_context
*pipe
= &nvc0
->base
.pipe
;
1179 pipe
->create_blend_state
= nvc0_blend_state_create
;
1180 pipe
->bind_blend_state
= nvc0_blend_state_bind
;
1181 pipe
->delete_blend_state
= nvc0_blend_state_delete
;
1183 pipe
->create_rasterizer_state
= nvc0_rasterizer_state_create
;
1184 pipe
->bind_rasterizer_state
= nvc0_rasterizer_state_bind
;
1185 pipe
->delete_rasterizer_state
= nvc0_rasterizer_state_delete
;
1187 pipe
->create_depth_stencil_alpha_state
= nvc0_zsa_state_create
;
1188 pipe
->bind_depth_stencil_alpha_state
= nvc0_zsa_state_bind
;
1189 pipe
->delete_depth_stencil_alpha_state
= nvc0_zsa_state_delete
;
1191 pipe
->create_sampler_state
= nv50_sampler_state_create
;
1192 pipe
->delete_sampler_state
= nvc0_sampler_state_delete
;
1193 pipe
->bind_vertex_sampler_states
= nvc0_vp_sampler_states_bind
;
1194 pipe
->bind_fragment_sampler_states
= nvc0_fp_sampler_states_bind
;
1195 pipe
->bind_geometry_sampler_states
= nvc0_gp_sampler_states_bind
;
1196 pipe
->bind_compute_sampler_states
= nvc0_cp_sampler_states_bind
;
1198 pipe
->create_sampler_view
= nvc0_create_sampler_view
;
1199 pipe
->sampler_view_destroy
= nvc0_sampler_view_destroy
;
1200 pipe
->set_vertex_sampler_views
= nvc0_vp_set_sampler_views
;
1201 pipe
->set_fragment_sampler_views
= nvc0_fp_set_sampler_views
;
1202 pipe
->set_geometry_sampler_views
= nvc0_gp_set_sampler_views
;
1203 pipe
->set_compute_sampler_views
= nvc0_cp_set_sampler_views
;
1205 pipe
->create_vs_state
= nvc0_vp_state_create
;
1206 pipe
->create_fs_state
= nvc0_fp_state_create
;
1207 pipe
->create_gs_state
= nvc0_gp_state_create
;
1208 pipe
->bind_vs_state
= nvc0_vp_state_bind
;
1209 pipe
->bind_fs_state
= nvc0_fp_state_bind
;
1210 pipe
->bind_gs_state
= nvc0_gp_state_bind
;
1211 pipe
->delete_vs_state
= nvc0_sp_state_delete
;
1212 pipe
->delete_fs_state
= nvc0_sp_state_delete
;
1213 pipe
->delete_gs_state
= nvc0_sp_state_delete
;
1215 pipe
->create_compute_state
= nvc0_cp_state_create
;
1216 pipe
->bind_compute_state
= nvc0_cp_state_bind
;
1217 pipe
->delete_compute_state
= nvc0_sp_state_delete
;
1219 pipe
->set_blend_color
= nvc0_set_blend_color
;
1220 pipe
->set_stencil_ref
= nvc0_set_stencil_ref
;
1221 pipe
->set_clip_state
= nvc0_set_clip_state
;
1222 pipe
->set_sample_mask
= nvc0_set_sample_mask
;
1223 pipe
->set_constant_buffer
= nvc0_set_constant_buffer
;
1224 pipe
->set_framebuffer_state
= nvc0_set_framebuffer_state
;
1225 pipe
->set_polygon_stipple
= nvc0_set_polygon_stipple
;
1226 pipe
->set_scissor_state
= nvc0_set_scissor_state
;
1227 pipe
->set_viewport_state
= nvc0_set_viewport_state
;
1229 pipe
->create_vertex_elements_state
= nvc0_vertex_state_create
;
1230 pipe
->delete_vertex_elements_state
= nvc0_vertex_state_delete
;
1231 pipe
->bind_vertex_elements_state
= nvc0_vertex_state_bind
;
1233 pipe
->set_vertex_buffers
= nvc0_set_vertex_buffers
;
1234 pipe
->set_index_buffer
= nvc0_set_index_buffer
;
1236 pipe
->create_stream_output_target
= nvc0_so_target_create
;
1237 pipe
->stream_output_target_destroy
= nvc0_so_target_destroy
;
1238 pipe
->set_stream_output_targets
= nvc0_set_transform_feedback_targets
;
1240 pipe
->set_global_binding
= nvc0_set_global_bindings
;
1241 pipe
->set_compute_resources
= nvc0_set_compute_resources
;
1242 pipe
->set_shader_resources
= nvc0_set_shader_resources
;