src/gallium/drivers/nvc0/nvc0_state_validate.c

   1
   2 #include "util/u_math.h"
   3
   4 #include "nvc0_context.h"
   5
   6 static void
   7 nvc0_validate_zcull(struct nvc0_context *nvc0)
   8 {
   9     struct nouveau_channel *chan = nvc0->screen->base.channel;
  10     struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
  11     struct nv50_surface *sf = nv50_surface(fb->zsbuf);
  12     struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
  13     struct nouveau_bo *bo = mt->base.bo;
  14     uint32_t size;
  15     uint32_t offset = align(mt->total_size, 1 << 17);
  16     unsigned width, height;
  17
  18     assert(mt->base.base.depth0 == 1 && mt->base.base.array_size < 2);
  19
  20     size = mt->total_size * 2;
  21
  22     height = align(fb->height, 32);
  23     width = fb->width % 224;
  24     if (width)
  25        width = fb->width + (224 - width);
  26     else
  27        width = fb->width;
  28
  29     MARK_RING (chan, 23, 4);
  30     BEGIN_RING(chan, RING_3D_(0x1590), 1); /* ZCULL_REGION_INDEX (bits 0x3f) */
  31     OUT_RING  (chan, 0);
  32     BEGIN_RING(chan, RING_3D_(0x07e8), 2); /* ZCULL_ADDRESS_A_HIGH */
  33     OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  34     OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  35     offset += 1 << 17;
  36     BEGIN_RING(chan, RING_3D_(0x07f0), 2); /* ZCULL_ADDRESS_B_HIGH */
  37     OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  38     OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  39     BEGIN_RING(chan, RING_3D_(0x07e0), 2);
  40     OUT_RING  (chan, size);
  41     OUT_RING  (chan, size >> 16);
  42     BEGIN_RING(chan, RING_3D_(0x15c8), 1); /* bits 0x3 */
  43     OUT_RING  (chan, 2);
  44     BEGIN_RING(chan, RING_3D_(0x07c0), 4); /* ZCULL dimensions */
  45     OUT_RING  (chan, width);
  46     OUT_RING  (chan, height);
  47     OUT_RING  (chan, 1);
  48     OUT_RING  (chan, 0);
  49     BEGIN_RING(chan, RING_3D_(0x15fc), 2);
  50     OUT_RING  (chan, 0); /* bits 0xffff */
  51     OUT_RING  (chan, 0); /* bits 0xffff */
  52     BEGIN_RING(chan, RING_3D_(0x1958), 1);
  53     OUT_RING  (chan, 0); /* bits ~0 */
  54 }
  55
  56 static void
  57 nvc0_validate_fb(struct nvc0_context *nvc0)
  58 {
  59     struct nouveau_channel *chan = nvc0->screen->base.channel;
  60     struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
  61     unsigned i;
  62     unsigned ms_mode = NVC0_3D_MULTISAMPLE_MODE_MS1;
  63     boolean serialize = FALSE;
  64
  65     nvc0_bufctx_reset(nvc0, NVC0_BUFCTX_FRAME);
  66
  67     BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
  68     OUT_RING  (chan, (076543210 << 4) | fb->nr_cbufs);
  69     BEGIN_RING(chan, RING_3D(SCREEN_SCISSOR_HORIZ), 2);
  70     OUT_RING  (chan, fb->width << 16);
  71     OUT_RING  (chan, fb->height << 16);
  72
  73     MARK_RING(chan, 9 * fb->nr_cbufs, 2 * fb->nr_cbufs);
  74
  75     for (i = 0; i < fb->nr_cbufs; ++i) {
  76         struct nv50_miptree *mt = nv50_miptree(fb->cbufs[i]->texture);
  77         struct nv50_surface *sf = nv50_surface(fb->cbufs[i]);
  78         struct nouveau_bo *bo = mt->base.bo;
  79         uint32_t offset = sf->offset;
  80
  81         BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(i)), 9);
  82         OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  83         OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  84         OUT_RING  (chan, sf->width);
  85         OUT_RING  (chan, sf->height);
  86         OUT_RING  (chan, nvc0_format_table[sf->base.format].rt);
  87         OUT_RING  (chan, (mt->layout_3d << 16) |
  88                    mt->level[sf->base.u.tex.level].tile_mode);
  89         OUT_RING  (chan, sf->base.u.tex.first_layer + sf->depth);
  90         OUT_RING  (chan, mt->layer_stride >> 2);
  91         OUT_RING  (chan, sf->base.u.tex.first_layer);
  92
  93         ms_mode = mt->ms_mode;
  94
  95         if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
  96            serialize = TRUE;
  97         mt->base.status |=  NOUVEAU_BUFFER_STATUS_GPU_WRITING;
  98         mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
  99
 100         /* only register for writing, otherwise we'd always serialize here */
 101         nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, &mt->base,
 102                                  NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 103     }
 104
 105     if (fb->zsbuf) {
 106         struct nv50_miptree *mt = nv50_miptree(fb->zsbuf->texture);
 107         struct nv50_surface *sf = nv50_surface(fb->zsbuf);
 108         struct nouveau_bo *bo = mt->base.bo;
 109         int unk = mt->base.base.target == PIPE_TEXTURE_2D;
 110         uint32_t offset = sf->offset;
 111
 112         MARK_RING (chan, 12, 2);
 113         BEGIN_RING(chan, RING_3D(ZETA_ADDRESS_HIGH), 5);
 114         OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 115         OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 116         OUT_RING  (chan, nvc0_format_table[fb->zsbuf->format].rt);
 117         OUT_RING  (chan, mt->level[sf->base.u.tex.level].tile_mode);
 118         OUT_RING  (chan, mt->layer_stride >> 2);
 119         BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
 120         OUT_RING  (chan, 1);
 121         BEGIN_RING(chan, RING_3D(ZETA_HORIZ), 3);
 122         OUT_RING  (chan, sf->width);
 123         OUT_RING  (chan, sf->height);
 124         OUT_RING  (chan, (unk << 16) |
 125                    (sf->base.u.tex.first_layer + sf->depth));
 126         BEGIN_RING(chan, RING_3D(ZETA_BASE_LAYER), 1);
 127         OUT_RING  (chan, sf->base.u.tex.first_layer);
 128
 129         ms_mode = mt->ms_mode;
 130
 131         if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
 132            serialize = TRUE;
 133         mt->base.status |=  NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 134         mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
 135
 136         nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, &mt->base,
 137                                  NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 138     } else {
 139         BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
 140         OUT_RING  (chan, 0);
 141     }
 142
 143     IMMED_RING(chan, RING_3D(MULTISAMPLE_MODE), ms_mode);
 144
 145     if (serialize) {
 146        BEGIN_RING(chan, RING_3D(SERIALIZE), 1);
 147        OUT_RING  (chan, 0);
 148     }
 149 }
 150
 151 static void
 152 nvc0_validate_blend_colour(struct nvc0_context *nvc0)
 153 {
 154     struct nouveau_channel *chan = nvc0->screen->base.channel;
 155
 156     BEGIN_RING(chan, RING_3D(BLEND_COLOR(0)), 4);
 157     OUT_RINGf (chan, nvc0->blend_colour.color[0]);
 158     OUT_RINGf (chan, nvc0->blend_colour.color[1]);
 159     OUT_RINGf (chan, nvc0->blend_colour.color[2]);
 160     OUT_RINGf (chan, nvc0->blend_colour.color[3]);
 161 }
 162
 163 static void
 164 nvc0_validate_stencil_ref(struct nvc0_context *nvc0)
 165 {
 166     struct nouveau_channel *chan = nvc0->screen->base.channel;
 167     const ubyte *ref = &nvc0->stencil_ref.ref_value[0];
 168
 169     IMMED_RING(chan, RING_3D(STENCIL_FRONT_FUNC_REF), ref[0]);
 170     IMMED_RING(chan, RING_3D(STENCIL_BACK_FUNC_REF), ref[1]);
 171 }
 172
 173 static void
 174 nvc0_validate_stipple(struct nvc0_context *nvc0)
 175 {
 176     struct nouveau_channel *chan = nvc0->screen->base.channel;
 177     unsigned i;
 178
 179     BEGIN_RING(chan, RING_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
 180     for (i = 0; i < 32; ++i)
 181         OUT_RING(chan, util_bswap32(nvc0->stipple.stipple[i]));
 182 }
 183
 184 static void
 185 nvc0_validate_scissor(struct nvc0_context *nvc0)
 186 {
 187     struct nouveau_channel *chan = nvc0->screen->base.channel;
 188     struct pipe_scissor_state *s = &nvc0->scissor;
 189
 190     if (!(nvc0->dirty & NVC0_NEW_SCISSOR) &&
 191         nvc0->rast->pipe.scissor == nvc0->state.scissor)
 192        return;
 193     nvc0->state.scissor = nvc0->rast->pipe.scissor;
 194
 195     BEGIN_RING(chan, RING_3D(SCISSOR_HORIZ(0)), 2);
 196     if (nvc0->rast->pipe.scissor) {
 197        OUT_RING(chan, (s->maxx << 16) | s->minx);
 198        OUT_RING(chan, (s->maxy << 16) | s->miny);
 199     } else {
 200        OUT_RING(chan, (0xffff << 16) | 0);
 201        OUT_RING(chan, (0xffff << 16) | 0);
 202     }
 203 }
 204
 205 static void
 206 nvc0_validate_viewport(struct nvc0_context *nvc0)
 207 {
 208     struct nouveau_channel *chan = nvc0->screen->base.channel;
 209     struct pipe_viewport_state *vp = &nvc0->viewport;
 210     int x, y, w, h;
 211     float zmin, zmax;
 212
 213     BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSLATE_X(0)), 3);
 214     OUT_RINGf (chan, vp->translate[0]);
 215     OUT_RINGf (chan, vp->translate[1]);
 216     OUT_RINGf (chan, vp->translate[2]);
 217     BEGIN_RING(chan, RING_3D(VIEWPORT_SCALE_X(0)), 3);
 218     OUT_RINGf (chan, vp->scale[0]);
 219     OUT_RINGf (chan, vp->scale[1]);
 220     OUT_RINGf (chan, vp->scale[2]);
 221
 222     /* now set the viewport rectangle to viewport dimensions for clipping */
 223
 224     x = util_iround(MAX2(0.0f, vp->translate[0] - fabsf(vp->scale[0])));
 225     y = util_iround(MAX2(0.0f, vp->translate[1] - fabsf(vp->scale[1])));
 226     w = util_iround(vp->translate[0] + fabsf(vp->scale[0])) - x;
 227     h = util_iround(vp->translate[1] + fabsf(vp->scale[1])) - y;
 228
 229     zmin = vp->translate[2] - fabsf(vp->scale[2]);
 230     zmax = vp->translate[2] + fabsf(vp->scale[2]);
 231
 232     BEGIN_RING(chan, RING_3D(VIEWPORT_HORIZ(0)), 2);
 233     OUT_RING  (chan, (w << 16) | x);
 234     OUT_RING  (chan, (h << 16) | y);
 235     BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 236     OUT_RINGf (chan, zmin);
 237     OUT_RINGf (chan, zmax);
 238 }
 239
 240 static void
 241 nvc0_validate_clip(struct nvc0_context *nvc0)
 242 {
 243    struct nouveau_channel *chan = nvc0->screen->base.channel;
 244    uint32_t clip;
 245
 246    if (nvc0->clip.depth_clamp) {
 247       clip =
 248          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
 249          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
 250          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
 251          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
 252    } else {
 253       clip = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
 254    }
 255
 256    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 257    OUT_RING  (chan, clip);
 258
 259    if (nvc0->clip.nr) {
 260       struct nouveau_bo *bo = nvc0->screen->uniforms;
 261
 262       MARK_RING (chan, 6 + nvc0->clip.nr * 4, 2);
 263       BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 264       OUT_RING  (chan, 256);
 265       OUT_RELOCh(chan, bo, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 266       OUT_RELOCl(chan, bo, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 267       BEGIN_RING_1I(chan, RING_3D(CB_POS), nvc0->clip.nr * 4 + 1);
 268       OUT_RING  (chan, 0);
 269       OUT_RINGp (chan, &nvc0->clip.ucp[0][0], nvc0->clip.nr * 4);
 270
 271       BEGIN_RING(chan, RING_3D(VP_CLIP_DISTANCE_ENABLE), 1);
 272       OUT_RING  (chan, (1 << nvc0->clip.nr) - 1);
 273    } else {
 274       IMMED_RING(chan, RING_3D(VP_CLIP_DISTANCE_ENABLE), 0);
 275    }
 276 }
 277
 278 static void
 279 nvc0_validate_blend(struct nvc0_context *nvc0)
 280 {
 281    struct nouveau_channel *chan = nvc0->screen->base.channel;
 282
 283    WAIT_RING(chan, nvc0->blend->size);
 284    OUT_RINGp(chan, nvc0->blend->state, nvc0->blend->size);
 285 }
 286
 287 static void
 288 nvc0_validate_zsa(struct nvc0_context *nvc0)
 289 {
 290    struct nouveau_channel *chan = nvc0->screen->base.channel;
 291
 292    WAIT_RING(chan, nvc0->zsa->size);
 293    OUT_RINGp(chan, nvc0->zsa->state, nvc0->zsa->size);
 294 }
 295
 296 static void
 297 nvc0_validate_rasterizer(struct nvc0_context *nvc0)
 298 {
 299    struct nouveau_channel *chan = nvc0->screen->base.channel;
 300
 301    WAIT_RING(chan, nvc0->rast->size);
 302    OUT_RINGp(chan, nvc0->rast->state, nvc0->rast->size);
 303 }
 304
 305 static void
 306 nvc0_constbufs_validate(struct nvc0_context *nvc0)
 307 {
 308    struct nouveau_channel *chan = nvc0->screen->base.channel;
 309    struct nouveau_bo *bo;
 310    unsigned s;
 311
 312    for (s = 0; s < 5; ++s) {
 313       struct nv04_resource *res;
 314       int i;
 315
 316       while (nvc0->constbuf_dirty[s]) {
 317          unsigned base = 0;
 318          unsigned offset = 0, words = 0;
 319          boolean rebind = TRUE;
 320
 321          i = ffs(nvc0->constbuf_dirty[s]) - 1;
 322          nvc0->constbuf_dirty[s] &= ~(1 << i);
 323
 324          res = nv04_resource(nvc0->constbuf[s][i]);
 325          if (!res) {
 326             BEGIN_RING(chan, RING_3D(CB_BIND(s)), 1);
 327             OUT_RING  (chan, (i << 4) | 0);
 328             if (i == 0)
 329                nvc0->state.uniform_buffer_bound[s] = 0;
 330             continue;
 331          }
 332
 333          if (!nouveau_resource_mapped_by_gpu(&res->base)) {
 334             if (i == 0) {
 335                base = s << 16;
 336                bo = nvc0->screen->uniforms;
 337
 338                if (nvc0->state.uniform_buffer_bound[s] >= res->base.width0)
 339                   rebind = FALSE;
 340                else
 341                   nvc0->state.uniform_buffer_bound[s] =
 342                      align(res->base.width0, 0x100);
 343             } else {
 344                bo = res->bo;
 345             }
 346 #if 0
 347             nvc0_m2mf_push_linear(nvc0, bo, NOUVEAU_BO_VRAM,
 348                                   base, res->base.width0, res->data);
 349             BEGIN_RING(chan, RING_3D_(0x021c), 1);
 350             OUT_RING  (chan, 0x1111);
 351 #else
 352             words = res->base.width0 / 4;
 353 #endif
 354          } else {
 355             bo = res->bo;
 356             if (i == 0)
 357                nvc0->state.uniform_buffer_bound[s] = 0;
 358          }
 359
 360          if (bo != nvc0->screen->uniforms)
 361             nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_CONSTANT, res,
 362                                      NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 363
 364          if (rebind) {
 365             MARK_RING (chan, 4, 2);
 366             BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 367             OUT_RING  (chan, align(res->base.width0, 0x100));
 368             OUT_RELOCh(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 369             OUT_RELOCl(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 370             BEGIN_RING(chan, RING_3D(CB_BIND(s)), 1);
 371             OUT_RING  (chan, (i << 4) | 1);
 372          }
 373
 374          while (words) {
 375             unsigned nr = AVAIL_RING(chan);
 376
 377             if (nr < 16) {
 378                FIRE_RING(chan);
 379                continue;
 380             }
 381             nr = MIN2(MIN2(nr - 6, words), NV04_PFIFO_MAX_PACKET_LEN - 1);
 382
 383             MARK_RING (chan, nr + 5, 2);
 384             BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 385             OUT_RING  (chan, align(res->base.width0, 0x100));
 386             OUT_RELOCh(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 387             OUT_RELOCl(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 388             BEGIN_RING_1I(chan, RING_3D(CB_POS), nr + 1);
 389             OUT_RING  (chan, offset);
 390             OUT_RINGp (chan, &res->data[offset], nr);
 391
 392             offset += nr * 4;
 393             words -= nr;
 394          }
 395       }
 396    }
 397 }
 398
 399 static void
 400 nvc0_validate_sample_mask(struct nvc0_context *nvc0)
 401 {
 402    struct nouveau_channel *chan = nvc0->screen->base.channel;
 403
 404    unsigned mask[4] =
 405    {
 406       nvc0->sample_mask & 0xffff,
 407       nvc0->sample_mask & 0xffff,
 408       nvc0->sample_mask & 0xffff,
 409       nvc0->sample_mask & 0xffff
 410    };
 411
 412    BEGIN_RING(chan, RING_3D(MSAA_MASK(0)), 4);
 413    OUT_RING  (chan, mask[0]);
 414    OUT_RING  (chan, mask[1]);
 415    OUT_RING  (chan, mask[2]);
 416    OUT_RING  (chan, mask[3]);
 417    BEGIN_RING(chan, RING_3D(SAMPLE_SHADING), 1);
 418    OUT_RING  (chan, 0x01);
 419 }
 420
 421 static void
 422 nvc0_validate_derived_1(struct nvc0_context *nvc0)
 423 {
 424    struct nouveau_channel *chan = nvc0->screen->base.channel;
 425    boolean early_z;
 426
 427    early_z = nvc0->fragprog->fp.early_z && !nvc0->zsa->pipe.alpha.enabled;
 428
 429    if (early_z != nvc0->state.early_z) {
 430       nvc0->state.early_z = early_z;
 431       IMMED_RING(chan, RING_3D(EARLY_FRAGMENT_TESTS), early_z);
 432    }
 433 }
 434
 435 static void
 436 nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
 437 {
 438    struct nvc0_context *ctx_from = ctx_to->screen->cur_ctx;
 439
 440    if (ctx_from)
 441       ctx_to->state = ctx_from->state;
 442
 443    ctx_to->dirty = ~0;
 444
 445    if (!ctx_to->vertex)
 446       ctx_to->dirty &= ~(NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS);
 447
 448    if (!ctx_to->vertprog)
 449       ctx_to->dirty &= ~NVC0_NEW_VERTPROG;
 450    if (!ctx_to->fragprog)
 451       ctx_to->dirty &= ~NVC0_NEW_FRAGPROG;
 452
 453    if (!ctx_to->blend)
 454       ctx_to->dirty &= ~NVC0_NEW_BLEND;
 455    if (!ctx_to->rast)
 456       ctx_to->dirty &= ~(NVC0_NEW_RASTERIZER | NVC0_NEW_SCISSOR);
 457    if (!ctx_to->zsa)
 458       ctx_to->dirty &= ~NVC0_NEW_ZSA;
 459
 460    ctx_to->screen->cur_ctx = ctx_to;
 461 }
 462
 463 static struct state_validate {
 464     void (*func)(struct nvc0_context *);
 465     uint32_t states;
 466 } validate_list[] = {
 467     { nvc0_validate_fb,            NVC0_NEW_FRAMEBUFFER },
 468     { nvc0_validate_blend,         NVC0_NEW_BLEND },
 469     { nvc0_validate_zsa,           NVC0_NEW_ZSA },
 470     { nvc0_validate_sample_mask,   NVC0_NEW_SAMPLE_MASK },
 471     { nvc0_validate_rasterizer,    NVC0_NEW_RASTERIZER },
 472     { nvc0_validate_blend_colour,  NVC0_NEW_BLEND_COLOUR },
 473     { nvc0_validate_stencil_ref,   NVC0_NEW_STENCIL_REF },
 474     { nvc0_validate_stipple,       NVC0_NEW_STIPPLE },
 475     { nvc0_validate_scissor,       NVC0_NEW_SCISSOR | NVC0_NEW_RASTERIZER },
 476     { nvc0_validate_viewport,      NVC0_NEW_VIEWPORT },
 477     { nvc0_validate_clip,          NVC0_NEW_CLIP },
 478     { nvc0_vertprog_validate,      NVC0_NEW_VERTPROG },
 479     { nvc0_tctlprog_validate,      NVC0_NEW_TCTLPROG },
 480     { nvc0_tevlprog_validate,      NVC0_NEW_TEVLPROG },
 481     { nvc0_gmtyprog_validate,      NVC0_NEW_GMTYPROG },
 482     { nvc0_fragprog_validate,      NVC0_NEW_FRAGPROG },
 483     { nvc0_validate_derived_1,     NVC0_NEW_FRAGPROG | NVC0_NEW_ZSA },
 484     { nvc0_constbufs_validate,     NVC0_NEW_CONSTBUF },
 485     { nvc0_validate_textures,      NVC0_NEW_TEXTURES },
 486     { nvc0_validate_samplers,      NVC0_NEW_SAMPLERS },
 487     { nvc0_vertex_arrays_validate, NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS },
 488     { nvc0_tfb_validate,           NVC0_NEW_TFB | NVC0_NEW_TFB_BUFFERS }
 489 };
 490 #define validate_list_len (sizeof(validate_list) / sizeof(validate_list[0]))
 491
 492 boolean
 493 nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask, unsigned words)
 494 {
 495    uint32_t state_mask;
 496    unsigned i;
 497
 498    if (nvc0->screen->cur_ctx != nvc0)
 499       nvc0_switch_pipe_context(nvc0);
 500
 501    state_mask = nvc0->dirty & mask;
 502
 503    if (state_mask) {
 504       for (i = 0; i < validate_list_len; ++i) {
 505          struct state_validate *validate = &validate_list[i];
 506
 507          if (state_mask & validate->states)
 508             validate->func(nvc0);
 509       }
 510       nvc0->dirty &= ~state_mask;
 511    }
 512
 513    MARK_RING(nvc0->screen->base.channel, words, 0);
 514
 515    nvc0_bufctx_emit_relocs(nvc0);
 516
 517    return TRUE;
 518 }