src/gallium/drivers/nvc0/nvc0_state_validate.c

   1
   2 #include "nvc0_context.h"
   3 #include "os/os_time.h"
   4
   5 static void
   6 nvc0_validate_zcull(struct nvc0_context *nvc0)
   7 {
   8     struct nouveau_channel *chan = nvc0->screen->base.channel;
   9     struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
  10     struct nvc0_surface *sf = nvc0_surface(fb->zsbuf);
  11     struct nvc0_miptree *mt = nvc0_miptree(sf->base.texture);
  12     struct nouveau_bo *bo = mt->base.bo;
  13     uint32_t size;
  14     uint32_t offset = align(mt->total_size, 1 << 17);
  15     unsigned width, height;
  16
  17     assert(mt->base.base.depth0 == 1 && mt->base.base.array_size < 2);
  18
  19     size = mt->total_size * 2;
  20
  21     height = align(fb->height, 32);
  22     width = fb->width % 224;
  23     if (width)
  24        width = fb->width + (224 - width);
  25     else
  26        width = fb->width;
  27
  28     MARK_RING (chan, 23, 4);
  29     BEGIN_RING(chan, RING_3D_(0x1590), 1); /* ZCULL_REGION_INDEX (bits 0x3f) */
  30     OUT_RING  (chan, 0);
  31     BEGIN_RING(chan, RING_3D_(0x07e8), 2); /* ZCULL_ADDRESS_A_HIGH */
  32     OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  33     OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  34     offset += 1 << 17;
  35     BEGIN_RING(chan, RING_3D_(0x07f0), 2); /* ZCULL_ADDRESS_B_HIGH */
  36     OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  37     OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  38     BEGIN_RING(chan, RING_3D_(0x07e0), 2);
  39     OUT_RING  (chan, size);
  40     OUT_RING  (chan, size >> 16);
  41     BEGIN_RING(chan, RING_3D_(0x15c8), 1); /* bits 0x3 */
  42     OUT_RING  (chan, 2);
  43     BEGIN_RING(chan, RING_3D_(0x07c0), 4); /* ZCULL dimensions */
  44     OUT_RING  (chan, width);
  45     OUT_RING  (chan, height);
  46     OUT_RING  (chan, 1);
  47     OUT_RING  (chan, 0);
  48     BEGIN_RING(chan, RING_3D_(0x15fc), 2);
  49     OUT_RING  (chan, 0); /* bits 0xffff */
  50     OUT_RING  (chan, 0); /* bits 0xffff */
  51     BEGIN_RING(chan, RING_3D_(0x1958), 1);
  52     OUT_RING  (chan, 0); /* bits ~0 */
  53 }
  54
  55 static void
  56 nvc0_validate_fb(struct nvc0_context *nvc0)
  57 {
  58     struct nouveau_channel *chan = nvc0->screen->base.channel;
  59     struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
  60     unsigned i;
  61     boolean serialize = FALSE;
  62
  63     nvc0_bufctx_reset(nvc0, NVC0_BUFCTX_FRAME);
  64
  65     BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
  66     OUT_RING  (chan, (076543210 << 4) | fb->nr_cbufs);
  67     BEGIN_RING(chan, RING_3D(SCREEN_SCISSOR_HORIZ), 2);
  68     OUT_RING  (chan, fb->width << 16);
  69     OUT_RING  (chan, fb->height << 16);
  70
  71     MARK_RING(chan, 9 * fb->nr_cbufs, 2 * fb->nr_cbufs);
  72
  73     for (i = 0; i < fb->nr_cbufs; ++i) {
  74         struct nvc0_miptree *mt = nvc0_miptree(fb->cbufs[i]->texture);
  75         struct nvc0_surface *sf = nvc0_surface(fb->cbufs[i]);
  76         struct nouveau_bo *bo = mt->base.bo;
  77         uint32_t offset = sf->offset;
  78
  79         BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(i)), 9);
  80         OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  81         OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  82         OUT_RING  (chan, sf->width);
  83         OUT_RING  (chan, sf->height);
  84         OUT_RING  (chan, nvc0_format_table[sf->base.format].rt);
  85         OUT_RING  (chan, (mt->layout_3d << 16) |
  86                    mt->level[sf->base.u.tex.level].tile_mode);
  87         OUT_RING  (chan, sf->base.u.tex.first_layer + sf->depth);
  88         OUT_RING  (chan, mt->layer_stride >> 2);
  89         OUT_RING  (chan, sf->base.u.tex.first_layer);
  90
  91         if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
  92            serialize = TRUE;
  93         mt->base.status |=  NOUVEAU_BUFFER_STATUS_GPU_WRITING;
  94         mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
  95
  96         nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, &mt->base,
  97                                  NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
  98     }
  99
 100     if (fb->zsbuf) {
 101         struct nvc0_miptree *mt = nvc0_miptree(fb->zsbuf->texture);
 102         struct nvc0_surface *sf = nvc0_surface(fb->zsbuf);
 103         struct nouveau_bo *bo = mt->base.bo;
 104         int unk = mt->base.base.target == PIPE_TEXTURE_2D;
 105         uint32_t offset = sf->offset;
 106
 107         MARK_RING (chan, 12, 2);
 108         BEGIN_RING(chan, RING_3D(ZETA_ADDRESS_HIGH), 5);
 109         OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 110         OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 111         OUT_RING  (chan, nvc0_format_table[fb->zsbuf->format].rt);
 112         OUT_RING  (chan, mt->level[sf->base.u.tex.level].tile_mode);
 113         OUT_RING  (chan, mt->layer_stride >> 2);
 114         BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
 115         OUT_RING  (chan, 1);
 116         BEGIN_RING(chan, RING_3D(ZETA_HORIZ), 3);
 117         OUT_RING  (chan, sf->width);
 118         OUT_RING  (chan, sf->height);
 119         OUT_RING  (chan, (unk << 16) |
 120                    (sf->base.u.tex.first_layer + sf->depth));
 121         BEGIN_RING(chan, RING_3D(ZETA_BASE_LAYER), 1);
 122         OUT_RING  (chan, sf->base.u.tex.first_layer);
 123
 124         if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
 125            serialize = TRUE;
 126         mt->base.status |=  NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 127         mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
 128
 129         nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, &mt->base,
 130                                  NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 131     } else {
 132         BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
 133         OUT_RING  (chan, 0);
 134     }
 135
 136     if (serialize) {
 137        BEGIN_RING(chan, RING_3D(SERIALIZE), 1);
 138        OUT_RING  (chan, 0);
 139     }
 140 }
 141
 142 static void
 143 nvc0_validate_blend_colour(struct nvc0_context *nvc0)
 144 {
 145     struct nouveau_channel *chan = nvc0->screen->base.channel;
 146
 147     BEGIN_RING(chan, RING_3D(BLEND_COLOR(0)), 4);
 148     OUT_RINGf (chan, nvc0->blend_colour.color[0]);
 149     OUT_RINGf (chan, nvc0->blend_colour.color[1]);
 150     OUT_RINGf (chan, nvc0->blend_colour.color[2]);
 151     OUT_RINGf (chan, nvc0->blend_colour.color[3]);
 152 }
 153
 154 static void
 155 nvc0_validate_stencil_ref(struct nvc0_context *nvc0)
 156 {
 157     struct nouveau_channel *chan = nvc0->screen->base.channel;
 158
 159     BEGIN_RING(chan, RING_3D(STENCIL_FRONT_FUNC_REF), 1);
 160     OUT_RING  (chan, nvc0->stencil_ref.ref_value[0]);
 161     BEGIN_RING(chan, RING_3D(STENCIL_BACK_FUNC_REF), 1);
 162     OUT_RING  (chan, nvc0->stencil_ref.ref_value[1]);
 163 }
 164
 165 static void
 166 nvc0_validate_stipple(struct nvc0_context *nvc0)
 167 {
 168     struct nouveau_channel *chan = nvc0->screen->base.channel;
 169     unsigned i;
 170
 171     BEGIN_RING(chan, RING_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
 172     for (i = 0; i < 32; ++i)
 173         OUT_RING(chan, util_bswap32(nvc0->stipple.stipple[i]));
 174 }
 175
 176 static void
 177 nvc0_validate_scissor(struct nvc0_context *nvc0)
 178 {
 179     struct nouveau_channel *chan = nvc0->screen->base.channel;
 180     struct pipe_scissor_state *s = &nvc0->scissor;
 181
 182     if (!(nvc0->dirty & NVC0_NEW_SCISSOR) &&
 183         nvc0->rast->pipe.scissor == nvc0->state.scissor)
 184        return;
 185     nvc0->state.scissor = nvc0->rast->pipe.scissor;
 186
 187     BEGIN_RING(chan, RING_3D(SCISSOR_HORIZ(0)), 2);
 188     if (nvc0->rast->pipe.scissor) {
 189        OUT_RING(chan, (s->maxx << 16) | s->minx);
 190        OUT_RING(chan, (s->maxy << 16) | s->miny);
 191     } else {
 192        OUT_RING(chan, (0xffff << 16) | 0);
 193        OUT_RING(chan, (0xffff << 16) | 0);
 194     }
 195 }
 196
 197 static void
 198 nvc0_validate_viewport(struct nvc0_context *nvc0)
 199 {
 200     struct nouveau_channel *chan = nvc0->screen->base.channel;
 201     struct pipe_viewport_state *vp = &nvc0->viewport;
 202     int x, y, w, h;
 203     float zmin, zmax;
 204
 205     BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSLATE_X(0)), 3);
 206     OUT_RINGf (chan, vp->translate[0]);
 207     OUT_RINGf (chan, vp->translate[1]);
 208     OUT_RINGf (chan, vp->translate[2]);
 209     BEGIN_RING(chan, RING_3D(VIEWPORT_SCALE_X(0)), 3);
 210     OUT_RINGf (chan, vp->scale[0]);
 211     OUT_RINGf (chan, vp->scale[1]);
 212     OUT_RINGf (chan, vp->scale[2]);
 213
 214     /* now set the viewport rectangle to viewport dimensions for clipping */
 215
 216     x = (int)(vp->translate[0] - fabsf(vp->scale[0]));
 217     y = (int)(vp->translate[1] - fabsf(vp->scale[1]));
 218     w = (int)fabsf(2.0f * vp->scale[0]);
 219     h = (int)fabsf(2.0f * vp->scale[1]);
 220     zmin = vp->translate[2] - fabsf(vp->scale[2]);
 221     zmax = vp->translate[2] + fabsf(vp->scale[2]);
 222
 223     BEGIN_RING(chan, RING_3D(VIEWPORT_HORIZ(0)), 2);
 224     OUT_RING  (chan, (w << 16) | x);
 225     OUT_RING  (chan, (h << 16) | y);
 226     BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 227     OUT_RINGf (chan, zmin);
 228     OUT_RINGf (chan, zmax);
 229 }
 230
 231 static void
 232 nvc0_validate_clip(struct nvc0_context *nvc0)
 233 {
 234    struct nouveau_channel *chan = nvc0->screen->base.channel;
 235    uint32_t clip;
 236
 237    if (nvc0->clip.depth_clamp) {
 238       clip =
 239          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
 240          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
 241          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
 242          NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
 243    } else {
 244       clip = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
 245    }
 246
 247    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 248    OUT_RING  (chan, clip);
 249
 250    if (nvc0->clip.nr) {
 251       struct nouveau_bo *bo = nvc0->screen->uniforms;
 252
 253       MARK_RING (chan, 6 + nvc0->clip.nr * 4, 2);
 254       BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 255       OUT_RING  (chan, 256);
 256       OUT_RELOCh(chan, bo, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 257       OUT_RELOCl(chan, bo, 5 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 258       BEGIN_RING_1I(chan, RING_3D(CB_POS), nvc0->clip.nr * 4 + 1);
 259       OUT_RING  (chan, 0);
 260       OUT_RINGp (chan, &nvc0->clip.ucp[0][0], nvc0->clip.nr * 4);
 261
 262       BEGIN_RING(chan, RING_3D(VP_CLIP_DISTANCE_ENABLE), 1);
 263       OUT_RING  (chan, (1 << nvc0->clip.nr) - 1);
 264    } else {
 265       IMMED_RING(chan, RING_3D(VP_CLIP_DISTANCE_ENABLE), 0);
 266    }
 267 }
 268
 269 static void
 270 nvc0_validate_blend(struct nvc0_context *nvc0)
 271 {
 272    struct nouveau_channel *chan = nvc0->screen->base.channel;
 273
 274    WAIT_RING(chan, nvc0->blend->size);
 275    OUT_RINGp(chan, nvc0->blend->state, nvc0->blend->size);
 276 }
 277
 278 static void
 279 nvc0_validate_zsa(struct nvc0_context *nvc0)
 280 {
 281    struct nouveau_channel *chan = nvc0->screen->base.channel;
 282
 283    WAIT_RING(chan, nvc0->zsa->size);
 284    OUT_RINGp(chan, nvc0->zsa->state, nvc0->zsa->size);
 285 }
 286
 287 static void
 288 nvc0_validate_rasterizer(struct nvc0_context *nvc0)
 289 {
 290    struct nouveau_channel *chan = nvc0->screen->base.channel;
 291
 292    WAIT_RING(chan, nvc0->rast->size);
 293    OUT_RINGp(chan, nvc0->rast->state, nvc0->rast->size);
 294 }
 295
 296 static void
 297 nvc0_validate_sprite_coords(struct nvc0_context *nvc0)
 298 {
 299    struct nouveau_channel *chan = nvc0->screen->base.channel;
 300    uint32_t reg;
 301
 302    if (nvc0->rast->pipe.sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT)
 303       reg = NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT;
 304    else
 305       reg = NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
 306
 307    if (nvc0->rast->pipe.point_quad_rasterization) {
 308       uint32_t en = nvc0->rast->pipe.sprite_coord_enable;
 309
 310       while (en) {
 311          int i = ffs(en) - 1;
 312          en &= ~(1 << i);
 313          if (i >= 0 && i < 8)
 314             reg |= 8 << i;
 315       }
 316    }
 317
 318    BEGIN_RING(chan, RING_3D(POINT_COORD_REPLACE), 1);
 319    OUT_RING  (chan, reg);
 320 }
 321
 322 static void
 323 nvc0_constbufs_validate(struct nvc0_context *nvc0)
 324 {
 325    struct nouveau_channel *chan = nvc0->screen->base.channel;
 326    struct nouveau_bo *bo;
 327    unsigned s;
 328
 329    for (s = 0; s < 5; ++s) {
 330       struct nv04_resource *res;
 331       int i;
 332
 333       while (nvc0->constbuf_dirty[s]) {
 334          unsigned base = 0;
 335          unsigned offset = 0, words = 0;
 336          boolean rebind = TRUE;
 337
 338          i = ffs(nvc0->constbuf_dirty[s]) - 1;
 339          nvc0->constbuf_dirty[s] &= ~(1 << i);
 340
 341          res = nv04_resource(nvc0->constbuf[s][i]);
 342          if (!res) {
 343             BEGIN_RING(chan, RING_3D(CB_BIND(s)), 1);
 344             OUT_RING  (chan, (i << 4) | 0);
 345             if (i == 0)
 346                nvc0->state.uniform_buffer_bound[s] = 0;
 347             continue;
 348          }
 349
 350          if (!nouveau_resource_mapped_by_gpu(&res->base)) {
 351             if (i == 0) {
 352                base = s << 16;
 353                bo = nvc0->screen->uniforms;
 354
 355                if (nvc0->state.uniform_buffer_bound[s] >= res->base.width0)
 356                   rebind = FALSE;
 357                else
 358                   nvc0->state.uniform_buffer_bound[s] =
 359                      align(res->base.width0, 0x100);
 360             } else {
 361                bo = res->bo;
 362             }
 363 #if 0
 364             nvc0_m2mf_push_linear(nvc0, bo, NOUVEAU_BO_VRAM,
 365                                   base, res->base.width0, res->data);
 366             BEGIN_RING(chan, RING_3D_(0x021c), 1);
 367             OUT_RING  (chan, 0x1111);
 368 #else
 369             words = res->base.width0 / 4;
 370 #endif
 371          } else {
 372             bo = res->bo;
 373             if (i == 0)
 374                nvc0->state.uniform_buffer_bound[s] = 0;
 375          }
 376
 377          if (bo != nvc0->screen->uniforms)
 378             nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_CONSTANT, res,
 379                                      NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 380
 381          if (rebind) {
 382             MARK_RING (chan, 4, 2);
 383             BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 384             OUT_RING  (chan, align(res->base.width0, 0x100));
 385             OUT_RELOCh(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 386             OUT_RELOCl(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 387             BEGIN_RING(chan, RING_3D(CB_BIND(s)), 1);
 388             OUT_RING  (chan, (i << 4) | 1);
 389          }
 390
 391          while (words) {
 392             unsigned nr = AVAIL_RING(chan);
 393
 394             if (nr < 16) {
 395                FIRE_RING(chan);
 396                continue;
 397             }
 398             nr = MIN2(MIN2(nr - 6, words), NV04_PFIFO_MAX_PACKET_LEN - 1);
 399
 400             MARK_RING (chan, nr + 5, 2);
 401             BEGIN_RING(chan, RING_3D(CB_SIZE), 3);
 402             OUT_RING  (chan, align(res->base.width0, 0x100));
 403             OUT_RELOCh(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 404             OUT_RELOCl(chan, bo, base, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 405             BEGIN_RING_1I(chan, RING_3D(CB_POS), nr + 1);
 406             OUT_RING  (chan, offset);
 407             OUT_RINGp (chan, &res->data[offset], nr);
 408
 409             offset += nr * 4;
 410             words -= nr;
 411          }
 412       }
 413    }
 414 }
 415
 416 static struct state_validate {
 417     void (*func)(struct nvc0_context *);
 418     uint32_t states;
 419 } validate_list[] = {
 420     { nvc0_validate_fb,            NVC0_NEW_FRAMEBUFFER },
 421     { nvc0_validate_blend,         NVC0_NEW_BLEND },
 422     { nvc0_validate_zsa,           NVC0_NEW_ZSA },
 423     { nvc0_validate_rasterizer,    NVC0_NEW_RASTERIZER },
 424     { nvc0_validate_blend_colour,  NVC0_NEW_BLEND_COLOUR },
 425     { nvc0_validate_stencil_ref,   NVC0_NEW_STENCIL_REF },
 426     { nvc0_validate_stipple,       NVC0_NEW_STIPPLE },
 427     { nvc0_validate_scissor,       NVC0_NEW_SCISSOR | NVC0_NEW_RASTERIZER },
 428     { nvc0_validate_viewport,      NVC0_NEW_VIEWPORT },
 429     { nvc0_validate_clip,          NVC0_NEW_CLIP },
 430     { nvc0_vertprog_validate,      NVC0_NEW_VERTPROG },
 431     { nvc0_tctlprog_validate,      NVC0_NEW_TCTLPROG },
 432     { nvc0_tevlprog_validate,      NVC0_NEW_TEVLPROG },
 433     { nvc0_gmtyprog_validate,      NVC0_NEW_GMTYPROG },
 434     { nvc0_fragprog_validate,      NVC0_NEW_FRAGPROG },
 435     { nvc0_validate_sprite_coords, NVC0_NEW_RASTERIZER | NVC0_NEW_FRAGPROG },
 436     { nvc0_constbufs_validate,     NVC0_NEW_CONSTBUF },
 437     { nvc0_validate_textures,      NVC0_NEW_TEXTURES },
 438     { nvc0_validate_samplers,      NVC0_NEW_SAMPLERS },
 439     { nvc0_vertex_arrays_validate, NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS },
 440     { nvc0_tfb_validate,           NVC0_NEW_TFB | NVC0_NEW_TFB_BUFFERS }
 441 };
 442 #define validate_list_len (sizeof(validate_list) / sizeof(validate_list[0]))
 443
 444 boolean
 445 nvc0_state_validate(struct nvc0_context *nvc0)
 446 {
 447    unsigned i;
 448 #if 0
 449    if (nvc0->screen->cur_ctx != nvc0) /* FIXME: not everything is valid */
 450       nvc0->dirty = 0xffffffff;
 451 #endif
 452    nvc0->screen->cur_ctx = nvc0;
 453
 454    if (nvc0->dirty) {
 455       for (i = 0; i < validate_list_len; ++i) {
 456          struct state_validate *validate = &validate_list[i];
 457
 458          if (nvc0->dirty & validate->states)
 459             validate->func(nvc0);
 460       }
 461       nvc0->dirty = 0;
 462    }
 463
 464    nvc0_bufctx_emit_relocs(nvc0);
 465
 466    return TRUE;
 467 }