projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
nouveau: switch to libdrm_nouveau-2.0
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_state_validate.c
1
2 #include "util/u_math.h"
3
4 #include "nvc0_context.h"
5
6 static void
7 nvc0_validate_zcull(struct nvc0_context *nvc0)
8 {
9 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
10 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
11 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
12 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
13 struct nouveau_bo *bo = mt->base.bo;
14 uint32_t size;
15 uint32_t offset = align(mt->total_size, 1 << 17);
16 unsigned width, height;
17
18 assert(mt->base.base.depth0 == 1 && mt->base.base.array_size < 2);
19
20 size = mt->total_size * 2;
21
22 height = align(fb->height, 32);
23 width = fb->width % 224;
24 if (width)
25 width = fb->width + (224 - width);
26 else
27 width = fb->width;
28
29 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1);
30 PUSH_DATA (push, 0);
31 BEGIN_NVC0(push, NVC0_3D(ZCULL_ADDRESS_HIGH), 2);
32 PUSH_DATAh(push, bo->offset + offset);
33 PUSH_DATA (push, bo->offset + offset);
34 offset += 1 << 17;
35 BEGIN_NVC0(push, NVC0_3D(ZCULL_LIMIT_HIGH), 2);
36 PUSH_DATAh(push, bo->offset + offset);
37 PUSH_DATA (push, bo->offset + offset);
38 BEGIN_NVC0(push, SUBC_3D(0x07e0), 2);
39 PUSH_DATA (push, size);
40 PUSH_DATA (push, size >> 16);
41 BEGIN_NVC0(push, SUBC_3D(0x15c8), 1); /* bits 0x3 */
42 PUSH_DATA (push, 2);
43 BEGIN_NVC0(push, NVC0_3D(ZCULL_WIDTH), 4);
44 PUSH_DATA (push, width);
45 PUSH_DATA (push, height);
46 PUSH_DATA (push, 1);
47 PUSH_DATA (push, 0);
48 BEGIN_NVC0(push, NVC0_3D(ZCULL_WINDOW_OFFSET_X), 2);
49 PUSH_DATA (push, 0);
50 PUSH_DATA (push, 0);
51 BEGIN_NVC0(push, NVC0_3D(ZCULL_INVALIDATE), 1);
52 PUSH_DATA (push, 0);
53 }
54
55 static void
56 nvc0_validate_fb(struct nvc0_context *nvc0)
57 {
58 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
59 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
60 unsigned i;
61 unsigned ms_mode = NVC0_3D_MULTISAMPLE_MODE_MS1;
62 boolean serialize = FALSE;
63
64 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
65
66 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
67 PUSH_DATA (push, (076543210 << 4) | fb->nr_cbufs);
68 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
69 PUSH_DATA (push, fb->width << 16);
70 PUSH_DATA (push, fb->height << 16);
71
72 for (i = 0; i < fb->nr_cbufs; ++i) {
73 struct nv50_surface *sf = nv50_surface(fb->cbufs[i]);
74 struct nv04_resource *res = nv04_resource(sf->base.texture);
75 struct nouveau_bo *bo = res->bo;
76
77 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
78 PUSH_DATAh(push, res->address + sf->offset);
79 PUSH_DATA (push, res->address + sf->offset);
80 if (likely(nouveau_bo_memtype(bo))) {
81 struct nv50_miptree *mt = nv50_miptree(sf->base.texture);
82
83 assert(sf->base.texture->target != PIPE_BUFFER);
84
85 PUSH_DATA(push, sf->width);
86 PUSH_DATA(push, sf->height);
87 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
88 PUSH_DATA(push, (mt->layout_3d << 16) |
89 mt->level[sf->base.u.tex.level].tile_mode);
90 PUSH_DATA(push, sf->base.u.tex.first_layer + sf->depth);
91 PUSH_DATA(push, mt->layer_stride >> 2);
92 PUSH_DATA(push, sf->base.u.tex.first_layer);
93
94 ms_mode = mt->ms_mode;
95 } else {
96 if (res->base.target == PIPE_BUFFER) {
97 PUSH_DATA(push, 262144);
98 PUSH_DATA(push, 1);
99 } else {
100 PUSH_DATA(push, nv50_miptree(sf->base.texture)->level[0].pitch);
101 PUSH_DATA(push, sf->height);
102 }
103 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
104 PUSH_DATA(push, 1 << 12);
105 PUSH_DATA(push, 1);
106 PUSH_DATA(push, 0);
107 PUSH_DATA(push, 0);
108
109 nvc0_resource_fence(res, NOUVEAU_BO_WR);
110
111 assert(!fb->zsbuf);
112 }
113
114 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_READING)
115 serialize = TRUE;
116 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
117 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
118
119 /* only register for writing, otherwise we'd always serialize here */
120 BCTX_REFN(nvc0->bufctx_3d, FB, res, WR);
121 }
122
123 if (fb->zsbuf) {
124 struct nv50_miptree *mt = nv50_miptree(fb->zsbuf->texture);
125 struct nv50_surface *sf = nv50_surface(fb->zsbuf);
126 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
127
128 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
129 PUSH_DATAh(push, mt->base.address + sf->offset);
130 PUSH_DATA (push, mt->base.address + sf->offset);
131 PUSH_DATA (push, nvc0_format_table[fb->zsbuf->format].rt);
132 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
133 PUSH_DATA (push, mt->layer_stride >> 2);
134 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
135 PUSH_DATA (push, 1);
136 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
137 PUSH_DATA (push, sf->width);
138 PUSH_DATA (push, sf->height);
139 PUSH_DATA (push, (unk << 16) |
140 (sf->base.u.tex.first_layer + sf->depth));
141 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
142 PUSH_DATA (push, sf->base.u.tex.first_layer);
143
144 ms_mode = mt->ms_mode;
145
146 if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
147 serialize = TRUE;
148 mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
149 mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
150
151 BCTX_REFN(nvc0->bufctx_3d, FB, &mt->base, WR);
152 } else {
153 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
154 PUSH_DATA (push, 0);
155 }
156
157 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), ms_mode);
158
159 if (serialize)
160 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
161 }
162
163 static void
164 nvc0_validate_blend_colour(struct nvc0_context *nvc0)
165 {
166 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
167
168 BEGIN_NVC0(push, NVC0_3D(BLEND_COLOR(0)), 4);
169 PUSH_DATAf(push, nvc0->blend_colour.color[0]);
170 PUSH_DATAf(push, nvc0->blend_colour.color[1]);
171 PUSH_DATAf(push, nvc0->blend_colour.color[2]);
172 PUSH_DATAf(push, nvc0->blend_colour.color[3]);
173 }
174
175 static void
176 nvc0_validate_stencil_ref(struct nvc0_context *nvc0)
177 {
178 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
179 const ubyte *ref = &nvc0->stencil_ref.ref_value[0];
180
181 IMMED_NVC0(push, NVC0_3D(STENCIL_FRONT_FUNC_REF), ref[0]);
182 IMMED_NVC0(push, NVC0_3D(STENCIL_BACK_FUNC_REF), ref[1]);
183 }
184
185 static void
186 nvc0_validate_stipple(struct nvc0_context *nvc0)
187 {
188 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
189 unsigned i;
190
191 BEGIN_NVC0(push, NVC0_3D(POLYGON_STIPPLE_PATTERN(0)), 32);
192 for (i = 0; i < 32; ++i)
193 PUSH_DATA(push, util_bswap32(nvc0->stipple.stipple[i]));
194 }
195
196 static void
197 nvc0_validate_scissor(struct nvc0_context *nvc0)
198 {
199 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
200 struct pipe_scissor_state *s = &nvc0->scissor;
201
202 if (!(nvc0->dirty & NVC0_NEW_SCISSOR) &&
203 nvc0->rast->pipe.scissor == nvc0->state.scissor)
204 return;
205 nvc0->state.scissor = nvc0->rast->pipe.scissor;
206
207 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
208 if (nvc0->rast->pipe.scissor) {
209 PUSH_DATA(push, (s->maxx << 16) | s->minx);
210 PUSH_DATA(push, (s->maxy << 16) | s->miny);
211 } else {
212 PUSH_DATA(push, (0xffff << 16) | 0);
213 PUSH_DATA(push, (0xffff << 16) | 0);
214 }
215 }
216
217 static void
218 nvc0_validate_viewport(struct nvc0_context *nvc0)
219 {
220 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
221 struct pipe_viewport_state *vp = &nvc0->viewport;
222 int x, y, w, h;
223 float zmin, zmax;
224
225 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSLATE_X(0)), 3);
226 PUSH_DATAf(push, vp->translate[0]);
227 PUSH_DATAf(push, vp->translate[1]);
228 PUSH_DATAf(push, vp->translate[2]);
229 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_SCALE_X(0)), 3);
230 PUSH_DATAf(push, vp->scale[0]);
231 PUSH_DATAf(push, vp->scale[1]);
232 PUSH_DATAf(push, vp->scale[2]);
233
234 /* now set the viewport rectangle to viewport dimensions for clipping */
235
236 x = util_iround(MAX2(0.0f, vp->translate[0] - fabsf(vp->scale[0])));
237 y = util_iround(MAX2(0.0f, vp->translate[1] - fabsf(vp->scale[1])));
238 w = util_iround(vp->translate[0] + fabsf(vp->scale[0])) - x;
239 h = util_iround(vp->translate[1] + fabsf(vp->scale[1])) - y;
240
241 zmin = vp->translate[2] - fabsf(vp->scale[2]);
242 zmax = vp->translate[2] + fabsf(vp->scale[2]);
243
244 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
245 PUSH_DATA (push, (w << 16) | x);
246 PUSH_DATA (push, (h << 16) | y);
247 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
248 PUSH_DATAf(push, zmin);
249 PUSH_DATAf(push, zmax);
250 }
251
252 static INLINE void
253 nvc0_upload_uclip_planes(struct nvc0_context *nvc0)
254 {
255 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
256 struct nouveau_bo *bo = nvc0->screen->uniforms;
257
258 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
259 PUSH_DATA (push, 256);
260 PUSH_DATAh(push, bo->offset + (5 << 16));
261 PUSH_DATA (push, bo->offset + (5 << 16));
262 BEGIN_1IC0(push, NVC0_3D(CB_POS), PIPE_MAX_CLIP_PLANES * 4 + 1);
263 PUSH_DATA (push, 0);
264 PUSH_DATAp(push, &nvc0->clip.ucp[0][0], PIPE_MAX_CLIP_PLANES * 4);
265 }
266
267 static INLINE void
268 nvc0_check_program_ucps(struct nvc0_context *nvc0,
269 struct nvc0_program *vp, uint8_t mask)
270 {
271 const unsigned n = util_logbase2(mask) + 1;
272
273 if (vp->vp.num_ucps >= n)
274 return;
275 nvc0_program_destroy(nvc0, vp);
276
277 vp->vp.num_ucps = n;
278 if (likely(vp == nvc0->vertprog))
279 nvc0_vertprog_validate(nvc0);
280 else
281 if (likely(vp == nvc0->gmtyprog))
282 nvc0_vertprog_validate(nvc0);
283 else
284 nvc0_tevlprog_validate(nvc0);
285 }
286
287 static void
288 nvc0_validate_clip(struct nvc0_context *nvc0)
289 {
290 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
291 struct nvc0_program *vp;
292 uint8_t clip_enable = nvc0->rast->pipe.clip_plane_enable;
293
294 if (nvc0->dirty & NVC0_NEW_CLIP)
295 nvc0_upload_uclip_planes(nvc0);
296
297 vp = nvc0->gmtyprog;
298 if (!vp) {
299 vp = nvc0->tevlprog;
300 if (!vp)
301 vp = nvc0->vertprog;
302 }
303
304 if (clip_enable && vp->vp.num_ucps < PIPE_MAX_CLIP_PLANES)
305 nvc0_check_program_ucps(nvc0, vp, clip_enable);
306
307 clip_enable &= vp->vp.clip_enable;
308
309 if (nvc0->state.clip_enable != clip_enable) {
310 nvc0->state.clip_enable = clip_enable;
311 IMMED_NVC0(push, NVC0_3D(CLIP_DISTANCE_ENABLE), clip_enable);
312 }
313 if (nvc0->state.clip_mode != vp->vp.clip_mode) {
314 nvc0->state.clip_mode = vp->vp.clip_mode;
315 BEGIN_NVC0(push, NVC0_3D(CLIP_DISTANCE_MODE), 1);
316 PUSH_DATA (push, vp->vp.clip_mode);
317 }
318 }
319
320 static void
321 nvc0_validate_blend(struct nvc0_context *nvc0)
322 {
323 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
324
325 PUSH_SPACE(push, nvc0->blend->size);
326 PUSH_DATAp(push, nvc0->blend->state, nvc0->blend->size);
327 }
328
329 static void
330 nvc0_validate_zsa(struct nvc0_context *nvc0)
331 {
332 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
333
334 PUSH_SPACE(push, nvc0->zsa->size);
335 PUSH_DATAp(push, nvc0->zsa->state, nvc0->zsa->size);
336 }
337
338 static void
339 nvc0_validate_rasterizer(struct nvc0_context *nvc0)
340 {
341 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
342
343 PUSH_SPACE(push, nvc0->rast->size);
344 PUSH_DATAp(push, nvc0->rast->state, nvc0->rast->size);
345 }
346
347 static void
348 nvc0_constbufs_validate(struct nvc0_context *nvc0)
349 {
350 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
351 struct nouveau_bo *bo;
352 unsigned s;
353
354 for (s = 0; s < 5; ++s) {
355 struct nv04_resource *res;
356 int i;
357
358 while (nvc0->constbuf_dirty[s]) {
359 unsigned base = 0;
360 unsigned words = 0;
361 boolean rebind = TRUE;
362
363 i = ffs(nvc0->constbuf_dirty[s]) - 1;
364 nvc0->constbuf_dirty[s] &= ~(1 << i);
365
366 res = nv04_resource(nvc0->constbuf[s][i]);
367 if (!res) {
368 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
369 PUSH_DATA (push, (i << 4) | 0);
370 if (i == 0)
371 nvc0->state.uniform_buffer_bound[s] = 0;
372 continue;
373 }
374
375 if (!nouveau_resource_mapped_by_gpu(&res->base)) {
376 if (i == 0 && (res->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY)) {
377 base = s << 16;
378 bo = nvc0->screen->uniforms;
379
380 if (nvc0->state.uniform_buffer_bound[s] >= res->base.width0)
381 rebind = FALSE;
382 else
383 nvc0->state.uniform_buffer_bound[s] =
384 align(res->base.width0, 0x100);
385
386 words = res->base.width0 / 4;
387 } else {
388 nouveau_buffer_migrate(&nvc0->base, res, NOUVEAU_BO_VRAM);
389 bo = res->bo;
390 base = res->offset;
391 }
392 } else {
393 bo = res->bo;
394 base = res->offset;
395 if (i == 0)
396 nvc0->state.uniform_buffer_bound[s] = 0;
397 }
398
399 if (bo != nvc0->screen->uniforms)
400 BCTX_REFN(nvc0->bufctx_3d, CB(s, i), res, RD);
401
402 if (rebind) {
403 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
404 PUSH_DATA (push, align(res->base.width0, 0x100));
405 PUSH_DATAh(push, bo->offset + base);
406 PUSH_DATA (push, bo->offset + base);
407 BEGIN_NVC0(push, NVC0_3D(CB_BIND(s)), 1);
408 PUSH_DATA (push, (i << 4) | 1);
409 }
410
411 if (words)
412 nvc0_cb_push(&nvc0->base,
413 bo, NOUVEAU_BO_VRAM, base, res->base.width0,
414 0, words, (const uint32_t *)res->data);
415 }
416 }
417 }
418
419 static void
420 nvc0_validate_sample_mask(struct nvc0_context *nvc0)
421 {
422 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
423
424 unsigned mask[4] =
425 {
426 nvc0->sample_mask & 0xffff,
427 nvc0->sample_mask & 0xffff,
428 nvc0->sample_mask & 0xffff,
429 nvc0->sample_mask & 0xffff
430 };
431
432 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
433 PUSH_DATA (push, mask[0]);
434 PUSH_DATA (push, mask[1]);
435 PUSH_DATA (push, mask[2]);
436 PUSH_DATA (push, mask[3]);
437 BEGIN_NVC0(push, NVC0_3D(SAMPLE_SHADING), 1);
438 PUSH_DATA (push, 0x01);
439 }
440
441 static void
442 nvc0_validate_derived_1(struct nvc0_context *nvc0)
443 {
444 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
445 boolean early_z;
446 boolean rasterizer_discard;
447
448 early_z = nvc0->fragprog->fp.early_z && !nvc0->zsa->pipe.alpha.enabled;
449
450 if (early_z != nvc0->state.early_z) {
451 nvc0->state.early_z = early_z;
452 IMMED_NVC0(push, NVC0_3D(EARLY_FRAGMENT_TESTS), early_z);
453 }
454
455 rasterizer_discard = (!nvc0->fragprog || !nvc0->fragprog->hdr[18]) &&
456 !nvc0->zsa->pipe.depth.enabled && !nvc0->zsa->pipe.stencil[0].enabled;
457 rasterizer_discard = rasterizer_discard ||
458 nvc0->rast->pipe.rasterizer_discard;
459
460 if (rasterizer_discard != nvc0->state.rasterizer_discard) {
461 nvc0->state.rasterizer_discard = rasterizer_discard;
462 IMMED_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), !rasterizer_discard);
463 }
464 }
465
466 static void
467 nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
468 {
469 struct nvc0_context *ctx_from = ctx_to->screen->cur_ctx;
470
471 if (ctx_from)
472 ctx_to->state = ctx_from->state;
473
474 ctx_to->dirty = ~0;
475
476 if (!ctx_to->vertex)
477 ctx_to->dirty &= ~(NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS);
478
479 if (!ctx_to->vertprog)
480 ctx_to->dirty &= ~NVC0_NEW_VERTPROG;
481 if (!ctx_to->fragprog)
482 ctx_to->dirty &= ~NVC0_NEW_FRAGPROG;
483
484 if (!ctx_to->blend)
485 ctx_to->dirty &= ~NVC0_NEW_BLEND;
486 if (!ctx_to->rast)
487 ctx_to->dirty &= ~(NVC0_NEW_RASTERIZER | NVC0_NEW_SCISSOR);
488 if (!ctx_to->zsa)
489 ctx_to->dirty &= ~NVC0_NEW_ZSA;
490
491 ctx_to->screen->cur_ctx = ctx_to;
492 }
493
494 static struct state_validate {
495 void (*func)(struct nvc0_context *);
496 uint32_t states;
497 } validate_list[] = {
498 { nvc0_validate_fb, NVC0_NEW_FRAMEBUFFER },
499 { nvc0_validate_blend, NVC0_NEW_BLEND },
500 { nvc0_validate_zsa, NVC0_NEW_ZSA },
501 { nvc0_validate_sample_mask, NVC0_NEW_SAMPLE_MASK },
502 { nvc0_validate_rasterizer, NVC0_NEW_RASTERIZER },
503 { nvc0_validate_blend_colour, NVC0_NEW_BLEND_COLOUR },
504 { nvc0_validate_stencil_ref, NVC0_NEW_STENCIL_REF },
505 { nvc0_validate_stipple, NVC0_NEW_STIPPLE },
506 { nvc0_validate_scissor, NVC0_NEW_SCISSOR | NVC0_NEW_RASTERIZER },
507 { nvc0_validate_viewport, NVC0_NEW_VIEWPORT },
508 { nvc0_vertprog_validate, NVC0_NEW_VERTPROG },
509 { nvc0_tctlprog_validate, NVC0_NEW_TCTLPROG },
510 { nvc0_tevlprog_validate, NVC0_NEW_TEVLPROG },
511 { nvc0_gmtyprog_validate, NVC0_NEW_GMTYPROG },
512 { nvc0_fragprog_validate, NVC0_NEW_FRAGPROG },
513 { nvc0_validate_derived_1, NVC0_NEW_FRAGPROG | NVC0_NEW_ZSA |
514 NVC0_NEW_RASTERIZER },
515 { nvc0_validate_clip, NVC0_NEW_CLIP | NVC0_NEW_RASTERIZER |
516 NVC0_NEW_VERTPROG |
517 NVC0_NEW_TEVLPROG |
518 NVC0_NEW_GMTYPROG },
519 { nvc0_constbufs_validate, NVC0_NEW_CONSTBUF },
520 { nvc0_validate_textures, NVC0_NEW_TEXTURES },
521 { nvc0_validate_samplers, NVC0_NEW_SAMPLERS },
522 { nvc0_vertex_arrays_validate, NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS },
523 { nvc0_idxbuf_validate, NVC0_NEW_IDXBUF },
524 { nvc0_tfb_validate, NVC0_NEW_TFB_TARGETS | NVC0_NEW_GMTYPROG }
525 };
526 #define validate_list_len (sizeof(validate_list) / sizeof(validate_list[0]))
527
528 boolean
529 nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask, unsigned words)
530 {
531 uint32_t state_mask;
532 int ret;
533 unsigned i;
534
535 if (nvc0->screen->cur_ctx != nvc0)
536 nvc0_switch_pipe_context(nvc0);
537
538 state_mask = nvc0->dirty & mask;
539
540 if (state_mask) {
541 for (i = 0; i < validate_list_len; ++i) {
542 struct state_validate *validate = &validate_list[i];
543
544 if (state_mask & validate->states)
545 validate->func(nvc0);
546 }
547 nvc0->dirty &= ~state_mask;
548
549 nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, FALSE);
550 }
551
552 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_3d);
553 ret = nouveau_pushbuf_validate(nvc0->base.pushbuf);
554 if (unlikely(ret))
555 return FALSE;
556
557 if (unlikely(nvc0->state.flushed))
558 nvc0_bufctx_fence(nvc0, nvc0->bufctx_3d, TRUE);
559
560 return TRUE;
561 }