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nv50,nvc0: fix 3d blits, restore viewport after blit
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "os/os_thread.h"
33
34 #include "nvc0_context.h"
35 #include "nvc0_resource.h"
36
37 #include "nv50/nv50_defs.xml.h"
38 #include "nv50/nv50_texture.xml.h"
39 #include "nv50/nv50_blit.h"
40
41 #define NVC0_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
42
43 /* return TRUE for formats that can be converted among each other by NVC0_2D */
44 static INLINE boolean
45 nvc0_2d_format_faithful(enum pipe_format format)
46 {
47 uint8_t id = nvc0_format_table[format].rt;
48
49 return (id >= 0xc0) && (NVC0_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0)));
50 }
51
52 static INLINE uint8_t
53 nvc0_2d_format(enum pipe_format format)
54 {
55 uint8_t id = nvc0_format_table[format].rt;
56
57 /* Hardware values for color formats range from 0xc0 to 0xff,
58 * but the 2D engine doesn't support all of them.
59 */
60 if (nvc0_2d_format_faithful(format))
61 return id;
62
63 switch (util_format_get_blocksize(format)) {
64 case 1:
65 return NV50_SURFACE_FORMAT_R8_UNORM;
66 case 2:
67 return NV50_SURFACE_FORMAT_R16_UNORM;
68 case 4:
69 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
70 case 8:
71 return NV50_SURFACE_FORMAT_RGBA16_UNORM;
72 case 16:
73 return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
74 default:
75 return 0;
76 }
77 }
78
79 static int
80 nvc0_2d_texture_set(struct nouveau_pushbuf *push, boolean dst,
81 struct nv50_miptree *mt, unsigned level, unsigned layer,
82 enum pipe_format pformat)
83 {
84 struct nouveau_bo *bo = mt->base.bo;
85 uint32_t width, height, depth;
86 uint32_t format;
87 uint32_t mthd = dst ? NVC0_2D_DST_FORMAT : NVC0_2D_SRC_FORMAT;
88 uint32_t offset = mt->level[level].offset;
89
90 format = nvc0_2d_format(pformat);
91 if (!format) {
92 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
93 util_format_name(pformat));
94 return 1;
95 }
96
97 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
98 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
99 depth = u_minify(mt->base.base.depth0, level);
100
101 /* layer has to be < depth, and depth > tile depth / 2 */
102
103 if (!mt->layout_3d) {
104 offset += mt->layer_stride * layer;
105 layer = 0;
106 depth = 1;
107 } else
108 if (!dst) {
109 offset += nvc0_mt_zslice_offset(mt, level, layer);
110 layer = 0;
111 }
112
113 if (!nouveau_bo_memtype(bo)) {
114 BEGIN_NVC0(push, SUBC_2D(mthd), 2);
115 PUSH_DATA (push, format);
116 PUSH_DATA (push, 1);
117 BEGIN_NVC0(push, SUBC_2D(mthd + 0x14), 5);
118 PUSH_DATA (push, mt->level[level].pitch);
119 PUSH_DATA (push, width);
120 PUSH_DATA (push, height);
121 PUSH_DATAh(push, bo->offset + offset);
122 PUSH_DATA (push, bo->offset + offset);
123 } else {
124 BEGIN_NVC0(push, SUBC_2D(mthd), 5);
125 PUSH_DATA (push, format);
126 PUSH_DATA (push, 0);
127 PUSH_DATA (push, mt->level[level].tile_mode);
128 PUSH_DATA (push, depth);
129 PUSH_DATA (push, layer);
130 BEGIN_NVC0(push, SUBC_2D(mthd + 0x18), 4);
131 PUSH_DATA (push, width);
132 PUSH_DATA (push, height);
133 PUSH_DATAh(push, bo->offset + offset);
134 PUSH_DATA (push, bo->offset + offset);
135 }
136
137 #if 0
138 if (dst) {
139 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_CLIP_X), 4);
140 PUSH_DATA (push, 0);
141 PUSH_DATA (push, 0);
142 PUSH_DATA (push, width);
143 PUSH_DATA (push, height);
144 }
145 #endif
146 return 0;
147 }
148
149 static int
150 nvc0_2d_texture_do_copy(struct nouveau_pushbuf *push,
151 struct nv50_miptree *dst, unsigned dst_level,
152 unsigned dx, unsigned dy, unsigned dz,
153 struct nv50_miptree *src, unsigned src_level,
154 unsigned sx, unsigned sy, unsigned sz,
155 unsigned w, unsigned h)
156 {
157 const enum pipe_format dfmt = dst->base.base.format;
158 const enum pipe_format sfmt = src->base.base.format;
159 int ret;
160
161 if (!PUSH_SPACE(push, 2 * 16 + 32))
162 return PIPE_ERROR;
163
164 ret = nvc0_2d_texture_set(push, TRUE, dst, dst_level, dz, dfmt);
165 if (ret)
166 return ret;
167
168 ret = nvc0_2d_texture_set(push, FALSE, src, src_level, sz, sfmt);
169 if (ret)
170 return ret;
171
172 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), 0x00);
173 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
174 PUSH_DATA (push, dx << dst->ms_x);
175 PUSH_DATA (push, dy << dst->ms_y);
176 PUSH_DATA (push, w << dst->ms_x);
177 PUSH_DATA (push, h << dst->ms_y);
178 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
179 PUSH_DATA (push, 0);
180 PUSH_DATA (push, 1);
181 PUSH_DATA (push, 0);
182 PUSH_DATA (push, 1);
183 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
184 PUSH_DATA (push, 0);
185 PUSH_DATA (push, sx << src->ms_x);
186 PUSH_DATA (push, 0);
187 PUSH_DATA (push, sy << src->ms_x);
188
189 return 0;
190 }
191
192 static void
193 nvc0_resource_copy_region(struct pipe_context *pipe,
194 struct pipe_resource *dst, unsigned dst_level,
195 unsigned dstx, unsigned dsty, unsigned dstz,
196 struct pipe_resource *src, unsigned src_level,
197 const struct pipe_box *src_box)
198 {
199 struct nvc0_context *nvc0 = nvc0_context(pipe);
200 int ret;
201 boolean m2mf;
202 unsigned dst_layer = dstz, src_layer = src_box->z;
203
204 /* Fallback for buffers. */
205 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
206 util_resource_copy_region(pipe, dst, dst_level, dstx, dsty, dstz,
207 src, src_level, src_box);
208 return;
209 }
210
211 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
212 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
213
214 m2mf = (src->format == dst->format) ||
215 (util_format_get_blocksizebits(src->format) ==
216 util_format_get_blocksizebits(dst->format));
217
218 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
219
220 if (m2mf) {
221 struct nv50_m2mf_rect drect, srect;
222 unsigned i;
223 unsigned nx = util_format_get_nblocksx(src->format, src_box->width);
224 unsigned ny = util_format_get_nblocksy(src->format, src_box->height);
225
226 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
227 nv50_m2mf_rect_setup(&srect, src, src_level,
228 src_box->x, src_box->y, src_box->z);
229
230 for (i = 0; i < src_box->depth; ++i) {
231 nvc0->m2mf_copy_rect(nvc0, &drect, &srect, nx, ny);
232
233 if (nv50_miptree(dst)->layout_3d)
234 drect.z++;
235 else
236 drect.base += nv50_miptree(dst)->layer_stride;
237
238 if (nv50_miptree(src)->layout_3d)
239 srect.z++;
240 else
241 srect.base += nv50_miptree(src)->layer_stride;
242 }
243 return;
244 }
245
246 assert(nvc0_2d_format_faithful(src->format));
247 assert(nvc0_2d_format_faithful(dst->format));
248
249 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(src), RD);
250 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(dst), WR);
251 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
252 nouveau_pushbuf_validate(nvc0->base.pushbuf);
253
254 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
255 ret = nvc0_2d_texture_do_copy(nvc0->base.pushbuf,
256 nv50_miptree(dst), dst_level,
257 dstx, dsty, dst_layer,
258 nv50_miptree(src), src_level,
259 src_box->x, src_box->y, src_layer,
260 src_box->width, src_box->height);
261 if (ret)
262 break;
263 }
264 nouveau_bufctx_reset(nvc0->bufctx, 0);
265 }
266
267 static void
268 nvc0_clear_render_target(struct pipe_context *pipe,
269 struct pipe_surface *dst,
270 const union pipe_color_union *color,
271 unsigned dstx, unsigned dsty,
272 unsigned width, unsigned height)
273 {
274 struct nvc0_context *nvc0 = nvc0_context(pipe);
275 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
276 struct nv50_surface *sf = nv50_surface(dst);
277 struct nv04_resource *res = nv04_resource(sf->base.texture);
278 unsigned z;
279
280 if (!PUSH_SPACE(push, 32 + sf->depth))
281 return;
282
283 PUSH_REFN (push, res->bo, res->domain | NOUVEAU_BO_WR);
284
285 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
286 PUSH_DATAf(push, color->f[0]);
287 PUSH_DATAf(push, color->f[1]);
288 PUSH_DATAf(push, color->f[2]);
289 PUSH_DATAf(push, color->f[3]);
290
291 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
292 PUSH_DATA (push, ( width << 16) | dstx);
293 PUSH_DATA (push, (height << 16) | dsty);
294
295 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
296 PUSH_DATA (push, 1);
297 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
298 PUSH_DATAh(push, res->address + sf->offset);
299 PUSH_DATA (push, res->address + sf->offset);
300 if (likely(nouveau_bo_memtype(res->bo))) {
301 struct nv50_miptree *mt = nv50_miptree(dst->texture);
302
303 PUSH_DATA(push, sf->width);
304 PUSH_DATA(push, sf->height);
305 PUSH_DATA(push, nvc0_format_table[dst->format].rt);
306 PUSH_DATA(push, (mt->layout_3d << 16) |
307 mt->level[sf->base.u.tex.level].tile_mode);
308 PUSH_DATA(push, dst->u.tex.first_layer + sf->depth);
309 PUSH_DATA(push, mt->layer_stride >> 2);
310 PUSH_DATA(push, dst->u.tex.first_layer);
311 } else {
312 if (res->base.target == PIPE_BUFFER) {
313 PUSH_DATA(push, 262144);
314 PUSH_DATA(push, 1);
315 } else {
316 PUSH_DATA(push, nv50_miptree(&res->base)->level[0].pitch);
317 PUSH_DATA(push, sf->height);
318 }
319 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
320 PUSH_DATA(push, 1 << 12);
321 PUSH_DATA(push, 1);
322 PUSH_DATA(push, 0);
323 PUSH_DATA(push, 0);
324
325 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
326
327 /* tiled textures don't have to be fenced, they're not mapped directly */
328 nvc0_resource_fence(res, NOUVEAU_BO_WR);
329 }
330
331 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
332 for (z = 0; z < sf->depth; ++z) {
333 PUSH_DATA (push, 0x3c |
334 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
335 }
336
337 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
338 }
339
340 static void
341 nvc0_clear_depth_stencil(struct pipe_context *pipe,
342 struct pipe_surface *dst,
343 unsigned clear_flags,
344 double depth,
345 unsigned stencil,
346 unsigned dstx, unsigned dsty,
347 unsigned width, unsigned height)
348 {
349 struct nvc0_context *nvc0 = nvc0_context(pipe);
350 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
351 struct nv50_miptree *mt = nv50_miptree(dst->texture);
352 struct nv50_surface *sf = nv50_surface(dst);
353 uint32_t mode = 0;
354 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
355 unsigned z;
356
357 if (!PUSH_SPACE(push, 32 + sf->depth))
358 return;
359
360 PUSH_REFN (push, mt->base.bo, mt->base.domain | NOUVEAU_BO_WR);
361
362 if (clear_flags & PIPE_CLEAR_DEPTH) {
363 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
364 PUSH_DATAf(push, depth);
365 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
366 }
367
368 if (clear_flags & PIPE_CLEAR_STENCIL) {
369 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
370 PUSH_DATA (push, stencil & 0xff);
371 mode |= NVC0_3D_CLEAR_BUFFERS_S;
372 }
373
374 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
375 PUSH_DATA (push, ( width << 16) | dstx);
376 PUSH_DATA (push, (height << 16) | dsty);
377
378 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
379 PUSH_DATAh(push, mt->base.address + sf->offset);
380 PUSH_DATA (push, mt->base.address + sf->offset);
381 PUSH_DATA (push, nvc0_format_table[dst->format].rt);
382 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
383 PUSH_DATA (push, mt->layer_stride >> 2);
384 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
385 PUSH_DATA (push, 1);
386 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
387 PUSH_DATA (push, sf->width);
388 PUSH_DATA (push, sf->height);
389 PUSH_DATA (push, (unk << 16) | (dst->u.tex.first_layer + sf->depth));
390 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
391 PUSH_DATA (push, dst->u.tex.first_layer);
392
393 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
394 for (z = 0; z < sf->depth; ++z) {
395 PUSH_DATA (push, mode |
396 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
397 }
398
399 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
400 }
401
402 void
403 nvc0_clear(struct pipe_context *pipe, unsigned buffers,
404 const union pipe_color_union *color,
405 double depth, unsigned stencil)
406 {
407 struct nvc0_context *nvc0 = nvc0_context(pipe);
408 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
409 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
410 unsigned i;
411 uint32_t mode = 0;
412
413 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
414 if (!nvc0_state_validate(nvc0, NVC0_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
415 return;
416
417 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
418 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
419 PUSH_DATAf(push, color->f[0]);
420 PUSH_DATAf(push, color->f[1]);
421 PUSH_DATAf(push, color->f[2]);
422 PUSH_DATAf(push, color->f[3]);
423 mode =
424 NVC0_3D_CLEAR_BUFFERS_R | NVC0_3D_CLEAR_BUFFERS_G |
425 NVC0_3D_CLEAR_BUFFERS_B | NVC0_3D_CLEAR_BUFFERS_A;
426 }
427
428 if (buffers & PIPE_CLEAR_DEPTH) {
429 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
430 PUSH_DATA (push, fui(depth));
431 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
432 }
433
434 if (buffers & PIPE_CLEAR_STENCIL) {
435 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
436 PUSH_DATA (push, stencil & 0xff);
437 mode |= NVC0_3D_CLEAR_BUFFERS_S;
438 }
439
440 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
441 PUSH_DATA (push, mode);
442
443 for (i = 1; i < fb->nr_cbufs; i++) {
444 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
445 PUSH_DATA (push, (i << 6) | 0x3c);
446 }
447 }
448
449
450 /* =============================== BLIT CODE ===================================
451 */
452
453 struct nvc0_blitter
454 {
455 struct nvc0_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
456 struct nvc0_program vp;
457
458 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
459
460 pipe_mutex mutex;
461
462 struct nvc0_screen *screen;
463 };
464
465 struct nvc0_blitctx
466 {
467 struct nvc0_context *nvc0;
468 struct nvc0_program *fp;
469 uint8_t mode;
470 uint16_t color_mask;
471 uint8_t filter;
472 enum pipe_texture_target target;
473 struct {
474 struct pipe_framebuffer_state fb;
475 struct nvc0_rasterizer_stateobj *rast;
476 struct nvc0_program *vp;
477 struct nvc0_program *tcp;
478 struct nvc0_program *tep;
479 struct nvc0_program *gp;
480 struct nvc0_program *fp;
481 unsigned num_textures[5];
482 unsigned num_samplers[5];
483 struct pipe_sampler_view *texture[2];
484 struct nv50_tsc_entry *sampler[2];
485 uint32_t dirty;
486 } saved;
487 struct nvc0_rasterizer_stateobj rast;
488 };
489
490 static void
491 nvc0_blitter_make_vp(struct nvc0_blitter *blit)
492 {
493 static const uint32_t code_nvc0[] =
494 {
495 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
496 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
497 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
498 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
499 0x00001de7, 0x80000000, /* exit */
500 };
501 static const uint32_t code_nve4[] =
502 {
503 0x00000007, 0x20000000, /* sched */
504 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
505 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
506 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
507 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
508 0x00001de7, 0x80000000, /* exit */
509 };
510
511 blit->vp.type = PIPE_SHADER_VERTEX;
512 blit->vp.translated = TRUE;
513 if (blit->screen->base.class_3d >= NVE4_3D_CLASS) {
514 blit->vp.code = (uint32_t *)code_nve4; /* const_cast */
515 blit->vp.code_size = sizeof(code_nve4);
516 } else {
517 blit->vp.code = (uint32_t *)code_nvc0; /* const_cast */
518 blit->vp.code_size = sizeof(code_nvc0);
519 }
520 blit->vp.num_gprs = 6;
521 blit->vp.vp.edgeflag = PIPE_MAX_ATTRIBS;
522
523 blit->vp.hdr[0] = 0x00020461; /* vertprog magic */
524 blit->vp.hdr[4] = 0x000ff000; /* no outputs read */
525 blit->vp.hdr[6] = 0x00000073; /* a[0x80].xy, a[0x90].xyz */
526 blit->vp.hdr[13] = 0x00073000; /* o[0x70].xy, o[0x80].xyz */
527 }
528
529 static void
530 nvc0_blitter_make_sampler(struct nvc0_blitter *blit)
531 {
532 /* clamp to edge, min/max lod = 0, nearest filtering */
533
534 blit->sampler[0].id = -1;
535
536 blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
537 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
538 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
539 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
540 blit->sampler[0].tsc[1] =
541 NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
542
543 /* clamp to edge, min/max lod = 0, bilinear filtering */
544
545 blit->sampler[1].id = -1;
546
547 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
548 blit->sampler[1].tsc[1] =
549 NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
550 }
551
552 static void
553 nvc0_blit_select_fp(struct nvc0_blitctx *ctx, const struct pipe_blit_info *info)
554 {
555 struct nvc0_blitter *blitter = ctx->nvc0->screen->blitter;
556
557 const enum pipe_texture_target ptarg =
558 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
559
560 const unsigned targ = nv50_blit_texture_type(ptarg);
561 const unsigned mode = ctx->mode;
562
563 if (!blitter->fp[targ][mode]) {
564 pipe_mutex_lock(blitter->mutex);
565 if (!blitter->fp[targ][mode])
566 blitter->fp[targ][mode] =
567 nv50_blitter_make_fp(&ctx->nvc0->base.pipe, mode, ptarg);
568 pipe_mutex_unlock(blitter->mutex);
569 }
570 ctx->fp = blitter->fp[targ][mode];
571 }
572
573 static void
574 nvc0_blit_set_dst(struct nvc0_blitctx *ctx,
575 struct pipe_resource *res, unsigned level, unsigned layer,
576 enum pipe_format format)
577 {
578 struct nvc0_context *nvc0 = ctx->nvc0;
579 struct pipe_context *pipe = &nvc0->base.pipe;
580 struct pipe_surface templ;
581
582 if (util_format_is_depth_or_stencil(format))
583 templ.format = nv50_blit_zeta_to_colour_format(format);
584 else
585 templ.format = format;
586
587 templ.u.tex.level = level;
588 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
589
590 if (layer == -1) {
591 templ.u.tex.first_layer = 0;
592 templ.u.tex.last_layer =
593 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
594 }
595
596 nvc0->framebuffer.cbufs[0] = nvc0_miptree_surface_new(pipe, res, &templ);
597 nvc0->framebuffer.nr_cbufs = 1;
598 nvc0->framebuffer.zsbuf = NULL;
599 nvc0->framebuffer.width = nvc0->framebuffer.cbufs[0]->width;
600 nvc0->framebuffer.height = nvc0->framebuffer.cbufs[0]->height;
601 }
602
603 static void
604 nvc0_blit_set_src(struct nvc0_blitctx *ctx,
605 struct pipe_resource *res, unsigned level, unsigned layer,
606 enum pipe_format format, const uint8_t filter)
607 {
608 struct nvc0_context *nvc0 = ctx->nvc0;
609 struct pipe_context *pipe = &nvc0->base.pipe;
610 struct pipe_sampler_view templ;
611 uint32_t flags;
612 unsigned s;
613 enum pipe_texture_target target;
614
615 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
616
617 templ.format = format;
618 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
619 templ.u.tex.first_level = templ.u.tex.last_level = level;
620 templ.swizzle_r = PIPE_SWIZZLE_RED;
621 templ.swizzle_g = PIPE_SWIZZLE_GREEN;
622 templ.swizzle_b = PIPE_SWIZZLE_BLUE;
623 templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
624
625 if (layer == -1) {
626 templ.u.tex.first_layer = 0;
627 templ.u.tex.last_layer =
628 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
629 }
630
631 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
632 if (filter && res->nr_samples == 8)
633 flags |= NV50_TEXVIEW_FILTER_MSAA8;
634
635 nvc0->textures[4][0] = nvc0_create_texture_view(
636 pipe, res, &templ, flags, target);
637 nvc0->textures[4][1] = NULL;
638
639 for (s = 0; s <= 3; ++s)
640 nvc0->num_textures[s] = 0;
641 nvc0->num_textures[4] = 1;
642
643 templ.format = nv50_zs_to_s_format(format);
644 if (templ.format != format) {
645 nvc0->textures[4][1] = nvc0_create_texture_view(
646 pipe, res, &templ, flags, target);
647 nvc0->num_textures[4] = 2;
648 }
649 }
650
651 static void
652 nvc0_blitctx_prepare_state(struct nvc0_blitctx *blit)
653 {
654 struct nouveau_pushbuf *push = blit->nvc0->base.pushbuf;
655
656 /* TODO: maybe make this a MACRO (if we need more logic) ? */
657
658 if (blit->nvc0->cond_query)
659 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
660
661 /* blend state */
662 BEGIN_NVC0(push, NVC0_3D(COLOR_MASK(0)), 1);
663 PUSH_DATA (push, blit->color_mask);
664 IMMED_NVC0(push, NVC0_3D(BLEND_ENABLE(0)), 0);
665 IMMED_NVC0(push, NVC0_3D(LOGIC_OP_ENABLE), 0);
666
667 /* rasterizer state */
668 IMMED_NVC0(push, NVC0_3D(FRAG_COLOR_CLAMP_EN), 0);
669 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 0);
670 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
671 PUSH_DATA (push, 0xffff);
672 PUSH_DATA (push, 0xffff);
673 PUSH_DATA (push, 0xffff);
674 PUSH_DATA (push, 0xffff);
675 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_FRONT), 1);
676 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_FRONT_FILL);
677 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_BACK), 1);
678 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_BACK_FILL);
679 IMMED_NVC0(push, NVC0_3D(POLYGON_SMOOTH_ENABLE), 0);
680 IMMED_NVC0(push, NVC0_3D(POLYGON_OFFSET_FILL_ENABLE), 0);
681 IMMED_NVC0(push, NVC0_3D(POLYGON_STIPPLE_ENABLE), 0);
682 IMMED_NVC0(push, NVC0_3D(CULL_FACE_ENABLE), 0);
683
684 /* zsa state */
685 IMMED_NVC0(push, NVC0_3D(DEPTH_TEST_ENABLE), 0);
686 IMMED_NVC0(push, NVC0_3D(STENCIL_ENABLE), 0);
687 IMMED_NVC0(push, NVC0_3D(ALPHA_TEST_ENABLE), 0);
688
689 /* disable transform feedback */
690 IMMED_NVC0(push, NVC0_3D(TFB_ENABLE), 0);
691 }
692
693 static void
694 nvc0_blitctx_pre_blit(struct nvc0_blitctx *ctx)
695 {
696 struct nvc0_context *nvc0 = ctx->nvc0;
697 struct nvc0_blitter *blitter = nvc0->screen->blitter;
698 int s;
699
700 ctx->saved.fb.width = nvc0->framebuffer.width;
701 ctx->saved.fb.height = nvc0->framebuffer.height;
702 ctx->saved.fb.nr_cbufs = nvc0->framebuffer.nr_cbufs;
703 ctx->saved.fb.cbufs[0] = nvc0->framebuffer.cbufs[0];
704 ctx->saved.fb.zsbuf = nvc0->framebuffer.zsbuf;
705
706 ctx->saved.rast = nvc0->rast;
707
708 ctx->saved.vp = nvc0->vertprog;
709 ctx->saved.tcp = nvc0->tctlprog;
710 ctx->saved.tep = nvc0->tevlprog;
711 ctx->saved.gp = nvc0->gmtyprog;
712 ctx->saved.fp = nvc0->fragprog;
713
714 nvc0->rast = &ctx->rast;
715
716 nvc0->vertprog = &blitter->vp;
717 nvc0->tctlprog = NULL;
718 nvc0->tevlprog = NULL;
719 nvc0->gmtyprog = NULL;
720 nvc0->fragprog = ctx->fp;
721
722 for (s = 0; s <= 4; ++s) {
723 ctx->saved.num_textures[s] = nvc0->num_textures[s];
724 ctx->saved.num_samplers[s] = nvc0->num_samplers[s];
725 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
726 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
727 }
728 ctx->saved.texture[0] = nvc0->textures[4][0];
729 ctx->saved.texture[1] = nvc0->textures[4][1];
730 ctx->saved.sampler[0] = nvc0->samplers[4][0];
731 ctx->saved.sampler[1] = nvc0->samplers[4][1];
732
733 nvc0->samplers[4][0] = &blitter->sampler[ctx->filter];
734 nvc0->samplers[4][1] = &blitter->sampler[ctx->filter];
735
736 for (s = 0; s <= 3; ++s)
737 nvc0->num_samplers[s] = 0;
738 nvc0->num_samplers[4] = 2;
739
740 ctx->saved.dirty = nvc0->dirty;
741
742 nvc0->textures_dirty[4] |= 3;
743 nvc0->samplers_dirty[4] |= 3;
744
745 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
746 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 0));
747 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 1));
748
749 nvc0->dirty = NVC0_NEW_FRAMEBUFFER |
750 NVC0_NEW_VERTPROG | NVC0_NEW_FRAGPROG |
751 NVC0_NEW_TCTLPROG | NVC0_NEW_TEVLPROG | NVC0_NEW_GMTYPROG |
752 NVC0_NEW_TEXTURES | NVC0_NEW_SAMPLERS;
753 }
754
755 static void
756 nvc0_blitctx_post_blit(struct nvc0_blitctx *blit)
757 {
758 struct nvc0_context *nvc0 = blit->nvc0;
759 int s;
760
761 pipe_surface_reference(&nvc0->framebuffer.cbufs[0], NULL);
762
763 nvc0->framebuffer.width = blit->saved.fb.width;
764 nvc0->framebuffer.height = blit->saved.fb.height;
765 nvc0->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
766 nvc0->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
767 nvc0->framebuffer.zsbuf = blit->saved.fb.zsbuf;
768
769 nvc0->rast = blit->saved.rast;
770
771 nvc0->vertprog = blit->saved.vp;
772 nvc0->tctlprog = blit->saved.tcp;
773 nvc0->tevlprog = blit->saved.tep;
774 nvc0->gmtyprog = blit->saved.gp;
775 nvc0->fragprog = blit->saved.fp;
776
777 pipe_sampler_view_reference(&nvc0->textures[4][0], NULL);
778 pipe_sampler_view_reference(&nvc0->textures[4][1], NULL);
779
780 for (s = 0; s <= 4; ++s) {
781 nvc0->num_textures[s] = blit->saved.num_textures[s];
782 nvc0->num_samplers[s] = blit->saved.num_samplers[s];
783 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
784 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
785 }
786 nvc0->textures[4][0] = blit->saved.texture[0];
787 nvc0->textures[4][1] = blit->saved.texture[1];
788 nvc0->samplers[4][0] = blit->saved.sampler[0];
789 nvc0->samplers[4][1] = blit->saved.sampler[1];
790
791 nvc0->textures_dirty[4] |= 3;
792 nvc0->samplers_dirty[4] |= 3;
793
794 if (nvc0->cond_query)
795 nvc0->base.pipe.render_condition(&nvc0->base.pipe, nvc0->cond_query,
796 nvc0->cond_mode);
797
798 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
799 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 0));
800 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 1));
801
802 nvc0->dirty = blit->saved.dirty |
803 (NVC0_NEW_FRAMEBUFFER | NVC0_NEW_SCISSOR | NVC0_NEW_SAMPLE_MASK |
804 NVC0_NEW_RASTERIZER | NVC0_NEW_ZSA | NVC0_NEW_BLEND |
805 NVC0_NEW_TEXTURES | NVC0_NEW_SAMPLERS |
806 NVC0_NEW_VERTPROG | NVC0_NEW_FRAGPROG |
807 NVC0_NEW_TCTLPROG | NVC0_NEW_TEVLPROG | NVC0_NEW_GMTYPROG |
808 NVC0_NEW_TFB_TARGETS);
809 }
810
811 static void
812 nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
813 {
814 struct nvc0_blitctx *blit = nvc0->blit;
815 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
816 struct pipe_resource *src = info->src.resource;
817 struct pipe_resource *dst = info->dst.resource;
818 int32_t minx, maxx, miny, maxy;
819 int32_t i;
820 float x0, x1, y0, y1, z;
821 float dz;
822 float x_range, y_range;
823
824 blit->mode = nv50_blit_select_mode(info);
825 blit->color_mask = nv50_blit_derive_color_mask(info);
826 blit->filter = nv50_blit_get_filter(info);
827
828 nvc0_blit_select_fp(blit, info);
829 nvc0_blitctx_pre_blit(blit);
830
831 nvc0_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
832 nvc0_blit_set_src(blit, src, info->src.level, -1, info->src.format,
833 blit->filter);
834
835 nvc0_blitctx_prepare_state(blit);
836
837 nvc0_state_validate(nvc0, ~0, 48);
838
839 x_range = (float)info->src.box.width / (float)info->dst.box.width;
840 y_range = (float)info->src.box.height / (float)info->dst.box.height;
841
842 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
843 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
844
845 x1 = x0 + 16384.0f * x_range;
846 y1 = y0 + 16384.0f * y_range;
847
848 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
849 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
850 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
851 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
852
853 if (src->last_level > 0) {
854 /* If there are mip maps, GPU always assumes normalized coordinates. */
855 const unsigned l = info->src.level;
856 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
857 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
858 x0 /= fh;
859 x1 /= fh;
860 y0 /= fv;
861 y1 /= fv;
862 }
863
864 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
865 z = (float)info->src.box.z;
866 if (nv50_miptree(src)->layout_3d)
867 z += 0.5f * dz;
868
869 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
870 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
871 PUSH_DATA (push, nvc0->framebuffer.width << 16);
872 PUSH_DATA (push, nvc0->framebuffer.height << 16);
873
874 /* Draw a large triangle in screen coordinates covering the whole
875 * render target, with scissors defining the destination region.
876 * The vertex is supplied with non-normalized texture coordinates
877 * arranged in a way to yield the desired offset and scale.
878 */
879
880 minx = info->dst.box.x;
881 maxx = info->dst.box.x + info->dst.box.width;
882 miny = info->dst.box.y;
883 maxy = info->dst.box.y + info->dst.box.height;
884 if (info->scissor_enable) {
885 minx = MAX2(minx, info->scissor.minx);
886 maxx = MIN2(maxx, info->scissor.maxx);
887 miny = MAX2(miny, info->scissor.miny);
888 maxy = MIN2(maxy, info->scissor.maxy);
889 }
890 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
891 PUSH_DATA (push, (maxx << 16) | minx);
892 PUSH_DATA (push, (maxy << 16) | miny);
893
894 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
895 if (info->dst.box.z + i) {
896 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
897 PUSH_DATA (push, info->dst.box.z + i);
898 }
899
900 IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL),
901 NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
902
903 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 4);
904 PUSH_DATA (push, 0x74301);
905 PUSH_DATAf(push, x0);
906 PUSH_DATAf(push, y0);
907 PUSH_DATAf(push, z);
908 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3);
909 PUSH_DATA (push, 0x74200);
910 PUSH_DATAf(push, 0.0f);
911 PUSH_DATAf(push, 0.0f);
912 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 4);
913 PUSH_DATA (push, 0x74301);
914 PUSH_DATAf(push, x1);
915 PUSH_DATAf(push, y0);
916 PUSH_DATAf(push, z);
917 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3);
918 PUSH_DATA (push, 0x74200);
919 PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_x);
920 PUSH_DATAf(push, 0.0f);
921 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 4);
922 PUSH_DATA (push, 0x74301);
923 PUSH_DATAf(push, x0);
924 PUSH_DATAf(push, y1);
925 PUSH_DATAf(push, z);
926 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3);
927 PUSH_DATA (push, 0x74200);
928 PUSH_DATAf(push, 0.0f);
929 PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_y);
930
931 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
932 }
933 if (info->dst.box.z + info->dst.box.depth - 1)
934 IMMED_NVC0(push, NVC0_3D(LAYER), 0);
935
936 nvc0_blitctx_post_blit(blit);
937
938 /* restore viewport */
939
940 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
941 PUSH_DATA (push, nvc0->framebuffer.width << 16);
942 PUSH_DATA (push, nvc0->framebuffer.height << 16);
943 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
944 }
945
946 static void
947 nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
948 {
949 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
950 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
951 struct nv50_miptree *src = nv50_miptree(info->src.resource);
952 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
953 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
954 const int dz = info->dst.box.z;
955 const int sz = info->src.box.z;
956 uint32_t dstw, dsth;
957 int32_t dstx, dsty;
958 int64_t srcx, srcy;
959 int64_t du_dx, dv_dy;
960 int i;
961 uint32_t mode;
962 const uint32_t mask = nv50_blit_eng2d_get_mask(info);
963
964 mode = nv50_blit_get_filter(info) ?
965 NVC0_2D_BLIT_CONTROL_FILTER_BILINEAR :
966 NVC0_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
967 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
968 NVC0_2D_BLIT_CONTROL_ORIGIN_CORNER : NVC0_2D_BLIT_CONTROL_ORIGIN_CENTER;
969
970 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
971 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
972
973 nvc0_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format);
974 nvc0_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format);
975
976 if (info->scissor_enable) {
977 BEGIN_NVC0(push, NVC0_2D(CLIP_X), 5);
978 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
979 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
980 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
981 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
982 PUSH_DATA (push, 1); /* enable */
983 }
984
985 if (mask != 0xffffffff) {
986 IMMED_NVC0(push, NVC0_2D(ROP), 0xca); /* DPSDxax */
987 IMMED_NVC0(push, NVC0_2D(PATTERN_COLOR_FORMAT),
988 NVC0_2D_PATTERN_COLOR_FORMAT_32BPP);
989 BEGIN_NVC0(push, NVC0_2D(PATTERN_COLOR(0)), 4);
990 PUSH_DATA (push, 0x00000000);
991 PUSH_DATA (push, mask);
992 PUSH_DATA (push, 0xffffffff);
993 PUSH_DATA (push, 0xffffffff);
994 IMMED_NVC0(push, NVC0_2D(OPERATION), NVC0_2D_OPERATION_ROP);
995 }
996
997 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
998 /* ms_x is always >= ms_y */
999 du_dx <<= src->ms_x - dst->ms_x;
1000 dv_dy <<= src->ms_y - dst->ms_y;
1001 } else {
1002 du_dx >>= dst->ms_x - src->ms_x;
1003 dv_dy >>= dst->ms_y - src->ms_y;
1004 }
1005
1006 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1007 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1008
1009 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1010 /* center src coorinates for proper MS resolve filtering */
1011 srcx += (int64_t)src->ms_x << 32;
1012 srcy += (int64_t)src->ms_y << 32;
1013 }
1014
1015 dstx = info->dst.box.x << dst->ms_x;
1016 dsty = info->dst.box.y << dst->ms_y;
1017
1018 dstw = info->dst.box.width << dst->ms_x;
1019 dsth = info->dst.box.height << dst->ms_y;
1020
1021 if (dstx < 0) {
1022 dstw += dstx;
1023 srcx -= du_dx * dstx;
1024 dstx = 0;
1025 }
1026 if (dsty < 0) {
1027 dsth += dsty;
1028 srcy -= dv_dy * dsty;
1029 dsty = 0;
1030 }
1031
1032 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), mode);
1033 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
1034 PUSH_DATA (push, dstx);
1035 PUSH_DATA (push, dsty);
1036 PUSH_DATA (push, dstw);
1037 PUSH_DATA (push, dsth);
1038 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
1039 PUSH_DATA (push, du_dx);
1040 PUSH_DATA (push, du_dx >> 32);
1041 PUSH_DATA (push, dv_dy);
1042 PUSH_DATA (push, dv_dy >> 32);
1043
1044 BCTX_REFN(nvc0->bufctx, 2D, &dst->base, WR);
1045 BCTX_REFN(nvc0->bufctx, 2D, &src->base, RD);
1046 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
1047 if (nouveau_pushbuf_validate(nvc0->base.pushbuf))
1048 return;
1049
1050 for (i = 0; i < info->dst.box.depth; ++i) {
1051 if (i > 0) {
1052 /* no scaling in z-direction possible for eng2d blits */
1053 if (dst->layout_3d) {
1054 BEGIN_NVC0(push, NVC0_2D(DST_LAYER), 1);
1055 PUSH_DATA (push, info->dst.box.z + i);
1056 } else {
1057 const unsigned z = info->dst.box.z + i;
1058 BEGIN_NVC0(push, NVC0_2D(DST_ADDRESS_HIGH), 2);
1059 PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
1060 PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
1061 }
1062 if (src->layout_3d) {
1063 /* not possible because of depth tiling */
1064 assert(0);
1065 } else {
1066 const unsigned z = info->src.box.z + i;
1067 BEGIN_NVC0(push, NVC0_2D(SRC_ADDRESS_HIGH), 2);
1068 PUSH_DATAh(push, src->base.address + z * src->layer_stride);
1069 PUSH_DATA (push, src->base.address + z * src->layer_stride);
1070 }
1071 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1072 PUSH_DATA (push, srcy >> 32);
1073 } else {
1074 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
1075 PUSH_DATA (push, srcx);
1076 PUSH_DATA (push, srcx >> 32);
1077 PUSH_DATA (push, srcy);
1078 PUSH_DATA (push, srcy >> 32);
1079 }
1080 }
1081 nvc0_bufctx_fence(nvc0, nvc0->bufctx, FALSE);
1082
1083 nouveau_bufctx_reset(nvc0->bufctx, NVC0_BIND_2D);
1084
1085 if (info->scissor_enable)
1086 IMMED_NVC0(push, NVC0_2D(CLIP_ENABLE), 0);
1087 if (mask != 0xffffffff)
1088 IMMED_NVC0(push, NVC0_2D(OPERATION), NVC0_2D_OPERATION_SRCCOPY);
1089 }
1090
1091 static void
1092 nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1093 {
1094 struct nvc0_context *nvc0 = nvc0_context(pipe);
1095 boolean eng3d = FALSE;
1096
1097 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1098 if (!(info->mask & PIPE_MASK_ZS))
1099 return;
1100 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1101 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1102 eng3d = TRUE;
1103 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1104 eng3d = TRUE;
1105 } else {
1106 if (!(info->mask & PIPE_MASK_RGBA))
1107 return;
1108 if (info->mask != PIPE_MASK_RGBA)
1109 eng3d = TRUE;
1110 }
1111
1112 if (nv50_miptree(info->src.resource)->layout_3d) {
1113 eng3d = TRUE;
1114 } else
1115 if (info->src.box.depth != info->dst.box.depth) {
1116 eng3d = TRUE;
1117 debug_printf("blit: cannot filter array or cube textures in z direction");
1118 }
1119
1120 if (!eng3d && info->dst.format != info->src.format) {
1121 if (!nvc0_2d_format_faithful(info->dst.format) ||
1122 !nvc0_2d_format_faithful(info->src.format))
1123 eng3d = TRUE;
1124 /* For some retarded reason, if dst is R8/16_UNORM, the 2d engine doesn't
1125 * like to do any format conversion (DATA_ERROR 0x34 on trigger).
1126 */
1127 if (info->dst.format == PIPE_FORMAT_R8_UNORM ||
1128 info->dst.format == PIPE_FORMAT_R16_UNORM)
1129 eng3d = TRUE;
1130 }
1131
1132 if (info->src.resource->nr_samples == 8 &&
1133 info->dst.resource->nr_samples <= 1)
1134 eng3d = TRUE;
1135 #if 0
1136 /* FIXME: can't make this work with eng2d anymore, at least not on nv50 */
1137 if (info->src.resource->nr_samples > 1 ||
1138 info->dst.resource->nr_samples > 1)
1139 eng3d = TRUE;
1140 #endif
1141 /* FIXME: find correct src coordinates adjustments */
1142 if ((info->src.box.width != info->dst.box.width &&
1143 info->src.box.width != -info->dst.box.width) ||
1144 (info->src.box.height != info->dst.box.height &&
1145 info->src.box.height != -info->dst.box.height))
1146 eng3d = TRUE;
1147
1148 if (!eng3d)
1149 nvc0_blit_eng2d(nvc0, info);
1150 else
1151 nvc0_blit_3d(nvc0, info);
1152 }
1153
1154 boolean
1155 nvc0_blitter_create(struct nvc0_screen *screen)
1156 {
1157 screen->blitter = CALLOC_STRUCT(nvc0_blitter);
1158 if (!screen->blitter) {
1159 NOUVEAU_ERR("failed to allocate blitter struct\n");
1160 return FALSE;
1161 }
1162 screen->blitter->screen = screen;
1163
1164 pipe_mutex_init(screen->blitter->mutex);
1165
1166 nvc0_blitter_make_vp(screen->blitter);
1167 nvc0_blitter_make_sampler(screen->blitter);
1168
1169 return TRUE;
1170 }
1171
1172 void
1173 nvc0_blitter_destroy(struct nvc0_screen *screen)
1174 {
1175 struct nvc0_blitter *blitter = screen->blitter;
1176 unsigned i, m;
1177
1178 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1179 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1180 struct nvc0_program *prog = blitter->fp[i][m];
1181 if (prog) {
1182 nvc0_program_destroy(NULL, prog);
1183 FREE((void *)prog->pipe.tokens);
1184 FREE(prog);
1185 }
1186 }
1187 }
1188
1189 FREE(blitter);
1190 }
1191
1192 boolean
1193 nvc0_blitctx_create(struct nvc0_context *nvc0)
1194 {
1195 nvc0->blit = CALLOC_STRUCT(nvc0_blitctx);
1196 if (!nvc0->blit) {
1197 NOUVEAU_ERR("failed to allocate blit context\n");
1198 return FALSE;
1199 }
1200
1201 nvc0->blit->nvc0 = nvc0;
1202
1203 nvc0->blit->rast.pipe.gl_rasterization_rules = 1;
1204
1205 return TRUE;
1206 }
1207
1208 void
1209 nvc0_init_surface_functions(struct nvc0_context *nvc0)
1210 {
1211 struct pipe_context *pipe = &nvc0->base.pipe;
1212
1213 pipe->resource_copy_region = nvc0_resource_copy_region;
1214 pipe->blit = nvc0_blit;
1215 pipe->clear_render_target = nvc0_clear_render_target;
1216 pipe->clear_depth_stencil = nvc0_clear_depth_stencil;
1217 }
1218