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gallium: add condition parameter to render_condition
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "os/os_thread.h"
33
34 #include "nvc0_context.h"
35 #include "nvc0_resource.h"
36
37 #include "nv50/nv50_defs.xml.h"
38 #include "nv50/nv50_texture.xml.h"
39
40 /* these are used in nv50_blit.h */
41 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
42 #define NV50_ENG2D_NOCONVERT_FORMATS 0x009cc02000000000ULL
43 #define NV50_ENG2D_LUMINANCE_FORMATS 0x001cc02000000000ULL
44 #define NV50_ENG2D_INTENSITY_FORMATS 0x0080000000000000ULL
45 #define NV50_ENG2D_OPERATION_FORMATS 0x060001c000638000ULL
46
47 #define NOUVEAU_DRIVER 0xc0
48 #include "nv50/nv50_blit.h"
49
50 static INLINE uint8_t
51 nvc0_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal)
52 {
53 uint8_t id = nvc0_format_table[format].rt;
54
55 /* A8_UNORM is treated as I8_UNORM as far as the 2D engine is concerned. */
56 if (!dst && unlikely(format == PIPE_FORMAT_I8_UNORM) && !dst_src_equal)
57 return NV50_SURFACE_FORMAT_A8_UNORM;
58
59 /* Hardware values for color formats range from 0xc0 to 0xff,
60 * but the 2D engine doesn't support all of them.
61 */
62 if (nv50_2d_format_supported(format))
63 return id;
64 assert(dst_src_equal);
65
66 switch (util_format_get_blocksize(format)) {
67 case 1:
68 return NV50_SURFACE_FORMAT_R8_UNORM;
69 case 2:
70 return NV50_SURFACE_FORMAT_R16_UNORM;
71 case 4:
72 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
73 case 8:
74 return NV50_SURFACE_FORMAT_RGBA16_UNORM;
75 case 16:
76 return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
77 default:
78 assert(0);
79 return 0;
80 }
81 }
82
83 static int
84 nvc0_2d_texture_set(struct nouveau_pushbuf *push, boolean dst,
85 struct nv50_miptree *mt, unsigned level, unsigned layer,
86 enum pipe_format pformat, boolean dst_src_pformat_equal)
87 {
88 struct nouveau_bo *bo = mt->base.bo;
89 uint32_t width, height, depth;
90 uint32_t format;
91 uint32_t mthd = dst ? NVC0_2D_DST_FORMAT : NVC0_2D_SRC_FORMAT;
92 uint32_t offset = mt->level[level].offset;
93
94 format = nvc0_2d_format(pformat, dst, dst_src_pformat_equal);
95 if (!format) {
96 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
97 util_format_name(pformat));
98 return 1;
99 }
100
101 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
102 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
103 depth = u_minify(mt->base.base.depth0, level);
104
105 /* layer has to be < depth, and depth > tile depth / 2 */
106
107 if (!mt->layout_3d) {
108 offset += mt->layer_stride * layer;
109 layer = 0;
110 depth = 1;
111 } else
112 if (!dst) {
113 offset += nvc0_mt_zslice_offset(mt, level, layer);
114 layer = 0;
115 }
116
117 if (!nouveau_bo_memtype(bo)) {
118 BEGIN_NVC0(push, SUBC_2D(mthd), 2);
119 PUSH_DATA (push, format);
120 PUSH_DATA (push, 1);
121 BEGIN_NVC0(push, SUBC_2D(mthd + 0x14), 5);
122 PUSH_DATA (push, mt->level[level].pitch);
123 PUSH_DATA (push, width);
124 PUSH_DATA (push, height);
125 PUSH_DATAh(push, bo->offset + offset);
126 PUSH_DATA (push, bo->offset + offset);
127 } else {
128 BEGIN_NVC0(push, SUBC_2D(mthd), 5);
129 PUSH_DATA (push, format);
130 PUSH_DATA (push, 0);
131 PUSH_DATA (push, mt->level[level].tile_mode);
132 PUSH_DATA (push, depth);
133 PUSH_DATA (push, layer);
134 BEGIN_NVC0(push, SUBC_2D(mthd + 0x18), 4);
135 PUSH_DATA (push, width);
136 PUSH_DATA (push, height);
137 PUSH_DATAh(push, bo->offset + offset);
138 PUSH_DATA (push, bo->offset + offset);
139 }
140
141 #if 0
142 if (dst) {
143 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_CLIP_X), 4);
144 PUSH_DATA (push, 0);
145 PUSH_DATA (push, 0);
146 PUSH_DATA (push, width);
147 PUSH_DATA (push, height);
148 }
149 #endif
150 return 0;
151 }
152
153 static int
154 nvc0_2d_texture_do_copy(struct nouveau_pushbuf *push,
155 struct nv50_miptree *dst, unsigned dst_level,
156 unsigned dx, unsigned dy, unsigned dz,
157 struct nv50_miptree *src, unsigned src_level,
158 unsigned sx, unsigned sy, unsigned sz,
159 unsigned w, unsigned h)
160 {
161 const enum pipe_format dfmt = dst->base.base.format;
162 const enum pipe_format sfmt = src->base.base.format;
163 int ret;
164 boolean eqfmt = dfmt == sfmt;
165
166 if (!PUSH_SPACE(push, 2 * 16 + 32))
167 return PIPE_ERROR;
168
169 ret = nvc0_2d_texture_set(push, TRUE, dst, dst_level, dz, dfmt, eqfmt);
170 if (ret)
171 return ret;
172
173 ret = nvc0_2d_texture_set(push, FALSE, src, src_level, sz, sfmt, eqfmt);
174 if (ret)
175 return ret;
176
177 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), 0x00);
178 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
179 PUSH_DATA (push, dx << dst->ms_x);
180 PUSH_DATA (push, dy << dst->ms_y);
181 PUSH_DATA (push, w << dst->ms_x);
182 PUSH_DATA (push, h << dst->ms_y);
183 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
184 PUSH_DATA (push, 0);
185 PUSH_DATA (push, 1);
186 PUSH_DATA (push, 0);
187 PUSH_DATA (push, 1);
188 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
189 PUSH_DATA (push, 0);
190 PUSH_DATA (push, sx << src->ms_x);
191 PUSH_DATA (push, 0);
192 PUSH_DATA (push, sy << src->ms_x);
193
194 return 0;
195 }
196
197 static void
198 nvc0_resource_copy_region(struct pipe_context *pipe,
199 struct pipe_resource *dst, unsigned dst_level,
200 unsigned dstx, unsigned dsty, unsigned dstz,
201 struct pipe_resource *src, unsigned src_level,
202 const struct pipe_box *src_box)
203 {
204 struct nvc0_context *nvc0 = nvc0_context(pipe);
205 int ret;
206 boolean m2mf;
207 unsigned dst_layer = dstz, src_layer = src_box->z;
208
209 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
210 nouveau_copy_buffer(&nvc0->base,
211 nv04_resource(dst), dstx,
212 nv04_resource(src), src_box->x, src_box->width);
213 NOUVEAU_DRV_STAT(&nvc0->screen->base, buf_copy_bytes, src_box->width);
214 return;
215 }
216 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_copy_count, 1);
217
218 /* 0 and 1 are equal, only supporting 0/1, 2, 4 and 8 */
219 assert((src->nr_samples | 1) == (dst->nr_samples | 1));
220
221 m2mf = (src->format == dst->format) ||
222 (util_format_get_blocksizebits(src->format) ==
223 util_format_get_blocksizebits(dst->format));
224
225 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
226
227 if (m2mf) {
228 struct nv50_m2mf_rect drect, srect;
229 unsigned i;
230 unsigned nx = util_format_get_nblocksx(src->format, src_box->width);
231 unsigned ny = util_format_get_nblocksy(src->format, src_box->height);
232
233 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
234 nv50_m2mf_rect_setup(&srect, src, src_level,
235 src_box->x, src_box->y, src_box->z);
236
237 for (i = 0; i < src_box->depth; ++i) {
238 nvc0->m2mf_copy_rect(nvc0, &drect, &srect, nx, ny);
239
240 if (nv50_miptree(dst)->layout_3d)
241 drect.z++;
242 else
243 drect.base += nv50_miptree(dst)->layer_stride;
244
245 if (nv50_miptree(src)->layout_3d)
246 srect.z++;
247 else
248 srect.base += nv50_miptree(src)->layer_stride;
249 }
250 return;
251 }
252
253 assert(nv50_2d_dst_format_faithful(dst->format));
254 assert(nv50_2d_src_format_faithful(src->format));
255
256 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(src), RD);
257 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(dst), WR);
258 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
259 nouveau_pushbuf_validate(nvc0->base.pushbuf);
260
261 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
262 ret = nvc0_2d_texture_do_copy(nvc0->base.pushbuf,
263 nv50_miptree(dst), dst_level,
264 dstx, dsty, dst_layer,
265 nv50_miptree(src), src_level,
266 src_box->x, src_box->y, src_layer,
267 src_box->width, src_box->height);
268 if (ret)
269 break;
270 }
271 nouveau_bufctx_reset(nvc0->bufctx, 0);
272 }
273
274 static void
275 nvc0_clear_render_target(struct pipe_context *pipe,
276 struct pipe_surface *dst,
277 const union pipe_color_union *color,
278 unsigned dstx, unsigned dsty,
279 unsigned width, unsigned height)
280 {
281 struct nvc0_context *nvc0 = nvc0_context(pipe);
282 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
283 struct nv50_surface *sf = nv50_surface(dst);
284 struct nv04_resource *res = nv04_resource(sf->base.texture);
285 unsigned z;
286
287 if (!PUSH_SPACE(push, 32 + sf->depth))
288 return;
289
290 PUSH_REFN (push, res->bo, res->domain | NOUVEAU_BO_WR);
291
292 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
293 PUSH_DATAf(push, color->f[0]);
294 PUSH_DATAf(push, color->f[1]);
295 PUSH_DATAf(push, color->f[2]);
296 PUSH_DATAf(push, color->f[3]);
297
298 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
299 PUSH_DATA (push, ( width << 16) | dstx);
300 PUSH_DATA (push, (height << 16) | dsty);
301
302 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
303 PUSH_DATA (push, 1);
304 BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
305 PUSH_DATAh(push, res->address + sf->offset);
306 PUSH_DATA (push, res->address + sf->offset);
307 if (likely(nouveau_bo_memtype(res->bo))) {
308 struct nv50_miptree *mt = nv50_miptree(dst->texture);
309
310 PUSH_DATA(push, sf->width);
311 PUSH_DATA(push, sf->height);
312 PUSH_DATA(push, nvc0_format_table[dst->format].rt);
313 PUSH_DATA(push, (mt->layout_3d << 16) |
314 mt->level[sf->base.u.tex.level].tile_mode);
315 PUSH_DATA(push, dst->u.tex.first_layer + sf->depth);
316 PUSH_DATA(push, mt->layer_stride >> 2);
317 PUSH_DATA(push, dst->u.tex.first_layer);
318 } else {
319 if (res->base.target == PIPE_BUFFER) {
320 PUSH_DATA(push, 262144);
321 PUSH_DATA(push, 1);
322 } else {
323 PUSH_DATA(push, nv50_miptree(&res->base)->level[0].pitch);
324 PUSH_DATA(push, sf->height);
325 }
326 PUSH_DATA(push, nvc0_format_table[sf->base.format].rt);
327 PUSH_DATA(push, 1 << 12);
328 PUSH_DATA(push, 1);
329 PUSH_DATA(push, 0);
330 PUSH_DATA(push, 0);
331
332 IMMED_NVC0(push, NVC0_3D(ZETA_ENABLE), 0);
333
334 /* tiled textures don't have to be fenced, they're not mapped directly */
335 nvc0_resource_fence(res, NOUVEAU_BO_WR);
336 }
337
338 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
339 for (z = 0; z < sf->depth; ++z) {
340 PUSH_DATA (push, 0x3c |
341 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
342 }
343
344 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
345 }
346
347 static void
348 nvc0_clear_depth_stencil(struct pipe_context *pipe,
349 struct pipe_surface *dst,
350 unsigned clear_flags,
351 double depth,
352 unsigned stencil,
353 unsigned dstx, unsigned dsty,
354 unsigned width, unsigned height)
355 {
356 struct nvc0_context *nvc0 = nvc0_context(pipe);
357 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
358 struct nv50_miptree *mt = nv50_miptree(dst->texture);
359 struct nv50_surface *sf = nv50_surface(dst);
360 uint32_t mode = 0;
361 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
362 unsigned z;
363
364 if (!PUSH_SPACE(push, 32 + sf->depth))
365 return;
366
367 PUSH_REFN (push, mt->base.bo, mt->base.domain | NOUVEAU_BO_WR);
368
369 if (clear_flags & PIPE_CLEAR_DEPTH) {
370 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
371 PUSH_DATAf(push, depth);
372 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
373 }
374
375 if (clear_flags & PIPE_CLEAR_STENCIL) {
376 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
377 PUSH_DATA (push, stencil & 0xff);
378 mode |= NVC0_3D_CLEAR_BUFFERS_S;
379 }
380
381 BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
382 PUSH_DATA (push, ( width << 16) | dstx);
383 PUSH_DATA (push, (height << 16) | dsty);
384
385 BEGIN_NVC0(push, NVC0_3D(ZETA_ADDRESS_HIGH), 5);
386 PUSH_DATAh(push, mt->base.address + sf->offset);
387 PUSH_DATA (push, mt->base.address + sf->offset);
388 PUSH_DATA (push, nvc0_format_table[dst->format].rt);
389 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode);
390 PUSH_DATA (push, mt->layer_stride >> 2);
391 BEGIN_NVC0(push, NVC0_3D(ZETA_ENABLE), 1);
392 PUSH_DATA (push, 1);
393 BEGIN_NVC0(push, NVC0_3D(ZETA_HORIZ), 3);
394 PUSH_DATA (push, sf->width);
395 PUSH_DATA (push, sf->height);
396 PUSH_DATA (push, (unk << 16) | (dst->u.tex.first_layer + sf->depth));
397 BEGIN_NVC0(push, NVC0_3D(ZETA_BASE_LAYER), 1);
398 PUSH_DATA (push, dst->u.tex.first_layer);
399
400 BEGIN_NIC0(push, NVC0_3D(CLEAR_BUFFERS), sf->depth);
401 for (z = 0; z < sf->depth; ++z) {
402 PUSH_DATA (push, mode |
403 (z << NVC0_3D_CLEAR_BUFFERS_LAYER__SHIFT));
404 }
405
406 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
407 }
408
409 void
410 nvc0_clear(struct pipe_context *pipe, unsigned buffers,
411 const union pipe_color_union *color,
412 double depth, unsigned stencil)
413 {
414 struct nvc0_context *nvc0 = nvc0_context(pipe);
415 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
416 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
417 unsigned i;
418 uint32_t mode = 0;
419
420 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
421 if (!nvc0_state_validate(nvc0, NVC0_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2)))
422 return;
423
424 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
425 BEGIN_NVC0(push, NVC0_3D(CLEAR_COLOR(0)), 4);
426 PUSH_DATAf(push, color->f[0]);
427 PUSH_DATAf(push, color->f[1]);
428 PUSH_DATAf(push, color->f[2]);
429 PUSH_DATAf(push, color->f[3]);
430 mode =
431 NVC0_3D_CLEAR_BUFFERS_R | NVC0_3D_CLEAR_BUFFERS_G |
432 NVC0_3D_CLEAR_BUFFERS_B | NVC0_3D_CLEAR_BUFFERS_A;
433 }
434
435 if (buffers & PIPE_CLEAR_DEPTH) {
436 BEGIN_NVC0(push, NVC0_3D(CLEAR_DEPTH), 1);
437 PUSH_DATA (push, fui(depth));
438 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
439 }
440
441 if (buffers & PIPE_CLEAR_STENCIL) {
442 BEGIN_NVC0(push, NVC0_3D(CLEAR_STENCIL), 1);
443 PUSH_DATA (push, stencil & 0xff);
444 mode |= NVC0_3D_CLEAR_BUFFERS_S;
445 }
446
447 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
448 PUSH_DATA (push, mode);
449
450 for (i = 1; i < fb->nr_cbufs; i++) {
451 BEGIN_NVC0(push, NVC0_3D(CLEAR_BUFFERS), 1);
452 PUSH_DATA (push, (i << 6) | 0x3c);
453 }
454 }
455
456
457 /* =============================== BLIT CODE ===================================
458 */
459
460 struct nvc0_blitter
461 {
462 struct nvc0_program *fp[NV50_BLIT_MAX_TEXTURE_TYPES][NV50_BLIT_MODES];
463 struct nvc0_program vp;
464
465 struct nv50_tsc_entry sampler[2]; /* nearest, bilinear */
466
467 pipe_mutex mutex;
468
469 struct nvc0_screen *screen;
470 };
471
472 struct nvc0_blitctx
473 {
474 struct nvc0_context *nvc0;
475 struct nvc0_program *fp;
476 uint8_t mode;
477 uint16_t color_mask;
478 uint8_t filter;
479 enum pipe_texture_target target;
480 struct {
481 struct pipe_framebuffer_state fb;
482 struct nvc0_rasterizer_stateobj *rast;
483 struct nvc0_program *vp;
484 struct nvc0_program *tcp;
485 struct nvc0_program *tep;
486 struct nvc0_program *gp;
487 struct nvc0_program *fp;
488 unsigned num_textures[5];
489 unsigned num_samplers[5];
490 struct pipe_sampler_view *texture[2];
491 struct nv50_tsc_entry *sampler[2];
492 uint32_t dirty;
493 } saved;
494 struct nvc0_rasterizer_stateobj rast;
495 };
496
497 static void
498 nvc0_blitter_make_vp(struct nvc0_blitter *blit)
499 {
500 static const uint32_t code_nvc0[] =
501 {
502 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
503 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
504 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
505 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
506 0x00001de7, 0x80000000, /* exit */
507 };
508 static const uint32_t code_nve4[] =
509 {
510 0x00000007, 0x20000000, /* sched */
511 0xfff11c26, 0x06000080, /* vfetch b64 $r4:$r5 a[0x80] */
512 0xfff01c46, 0x06000090, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
513 0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
514 0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
515 0x00001de7, 0x80000000, /* exit */
516 };
517
518 blit->vp.type = PIPE_SHADER_VERTEX;
519 blit->vp.translated = TRUE;
520 if (blit->screen->base.class_3d >= NVE4_3D_CLASS) {
521 blit->vp.code = (uint32_t *)code_nve4; /* const_cast */
522 blit->vp.code_size = sizeof(code_nve4);
523 } else {
524 blit->vp.code = (uint32_t *)code_nvc0; /* const_cast */
525 blit->vp.code_size = sizeof(code_nvc0);
526 }
527 blit->vp.num_gprs = 6;
528 blit->vp.vp.edgeflag = PIPE_MAX_ATTRIBS;
529
530 blit->vp.hdr[0] = 0x00020461; /* vertprog magic */
531 blit->vp.hdr[4] = 0x000ff000; /* no outputs read */
532 blit->vp.hdr[6] = 0x00000073; /* a[0x80].xy, a[0x90].xyz */
533 blit->vp.hdr[13] = 0x00073000; /* o[0x70].xy, o[0x80].xyz */
534 }
535
536 static void
537 nvc0_blitter_make_sampler(struct nvc0_blitter *blit)
538 {
539 /* clamp to edge, min/max lod = 0, nearest filtering */
540
541 blit->sampler[0].id = -1;
542
543 blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
544 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
545 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
546 (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
547 blit->sampler[0].tsc[1] =
548 NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
549
550 /* clamp to edge, min/max lod = 0, bilinear filtering */
551
552 blit->sampler[1].id = -1;
553
554 blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
555 blit->sampler[1].tsc[1] =
556 NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
557 }
558
559 static void
560 nvc0_blit_select_fp(struct nvc0_blitctx *ctx, const struct pipe_blit_info *info)
561 {
562 struct nvc0_blitter *blitter = ctx->nvc0->screen->blitter;
563
564 const enum pipe_texture_target ptarg =
565 nv50_blit_reinterpret_pipe_texture_target(info->src.resource->target);
566
567 const unsigned targ = nv50_blit_texture_type(ptarg);
568 const unsigned mode = ctx->mode;
569
570 if (!blitter->fp[targ][mode]) {
571 pipe_mutex_lock(blitter->mutex);
572 if (!blitter->fp[targ][mode])
573 blitter->fp[targ][mode] =
574 nv50_blitter_make_fp(&ctx->nvc0->base.pipe, mode, ptarg);
575 pipe_mutex_unlock(blitter->mutex);
576 }
577 ctx->fp = blitter->fp[targ][mode];
578 }
579
580 static void
581 nvc0_blit_set_dst(struct nvc0_blitctx *ctx,
582 struct pipe_resource *res, unsigned level, unsigned layer,
583 enum pipe_format format)
584 {
585 struct nvc0_context *nvc0 = ctx->nvc0;
586 struct pipe_context *pipe = &nvc0->base.pipe;
587 struct pipe_surface templ;
588
589 if (util_format_is_depth_or_stencil(format))
590 templ.format = nv50_blit_zeta_to_colour_format(format);
591 else
592 templ.format = format;
593
594 templ.u.tex.level = level;
595 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
596
597 if (layer == -1) {
598 templ.u.tex.first_layer = 0;
599 templ.u.tex.last_layer =
600 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
601 }
602
603 nvc0->framebuffer.cbufs[0] = nvc0_miptree_surface_new(pipe, res, &templ);
604 nvc0->framebuffer.nr_cbufs = 1;
605 nvc0->framebuffer.zsbuf = NULL;
606 nvc0->framebuffer.width = nvc0->framebuffer.cbufs[0]->width;
607 nvc0->framebuffer.height = nvc0->framebuffer.cbufs[0]->height;
608 }
609
610 static void
611 nvc0_blit_set_src(struct nvc0_blitctx *ctx,
612 struct pipe_resource *res, unsigned level, unsigned layer,
613 enum pipe_format format, const uint8_t filter)
614 {
615 struct nvc0_context *nvc0 = ctx->nvc0;
616 struct pipe_context *pipe = &nvc0->base.pipe;
617 struct pipe_sampler_view templ;
618 uint32_t flags;
619 unsigned s;
620 enum pipe_texture_target target;
621
622 target = nv50_blit_reinterpret_pipe_texture_target(res->target);
623
624 templ.format = format;
625 templ.u.tex.first_layer = templ.u.tex.last_layer = layer;
626 templ.u.tex.first_level = templ.u.tex.last_level = level;
627 templ.swizzle_r = PIPE_SWIZZLE_RED;
628 templ.swizzle_g = PIPE_SWIZZLE_GREEN;
629 templ.swizzle_b = PIPE_SWIZZLE_BLUE;
630 templ.swizzle_a = PIPE_SWIZZLE_ALPHA;
631
632 if (layer == -1) {
633 templ.u.tex.first_layer = 0;
634 templ.u.tex.last_layer =
635 (res->target == PIPE_TEXTURE_3D ? res->depth0 : res->array_size) - 1;
636 }
637
638 flags = res->last_level ? 0 : NV50_TEXVIEW_SCALED_COORDS;
639 flags |= NV50_TEXVIEW_ACCESS_RESOLVE;
640 if (filter && res->nr_samples == 8)
641 flags |= NV50_TEXVIEW_FILTER_MSAA8;
642
643 nvc0->textures[4][0] = nvc0_create_texture_view(
644 pipe, res, &templ, flags, target);
645 nvc0->textures[4][1] = NULL;
646
647 for (s = 0; s <= 3; ++s)
648 nvc0->num_textures[s] = 0;
649 nvc0->num_textures[4] = 1;
650
651 templ.format = nv50_zs_to_s_format(format);
652 if (templ.format != format) {
653 nvc0->textures[4][1] = nvc0_create_texture_view(
654 pipe, res, &templ, flags, target);
655 nvc0->num_textures[4] = 2;
656 }
657 }
658
659 static void
660 nvc0_blitctx_prepare_state(struct nvc0_blitctx *blit)
661 {
662 struct nouveau_pushbuf *push = blit->nvc0->base.pushbuf;
663
664 /* TODO: maybe make this a MACRO (if we need more logic) ? */
665
666 if (blit->nvc0->cond_query)
667 IMMED_NVC0(push, NVC0_3D(COND_MODE), NVC0_3D_COND_MODE_ALWAYS);
668
669 /* blend state */
670 BEGIN_NVC0(push, NVC0_3D(COLOR_MASK(0)), 1);
671 PUSH_DATA (push, blit->color_mask);
672 IMMED_NVC0(push, NVC0_3D(BLEND_ENABLE(0)), 0);
673 IMMED_NVC0(push, NVC0_3D(LOGIC_OP_ENABLE), 0);
674
675 /* rasterizer state */
676 IMMED_NVC0(push, NVC0_3D(FRAG_COLOR_CLAMP_EN), 0);
677 IMMED_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 0);
678 BEGIN_NVC0(push, NVC0_3D(MSAA_MASK(0)), 4);
679 PUSH_DATA (push, 0xffff);
680 PUSH_DATA (push, 0xffff);
681 PUSH_DATA (push, 0xffff);
682 PUSH_DATA (push, 0xffff);
683 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_FRONT), 1);
684 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_FRONT_FILL);
685 BEGIN_NVC0(push, NVC0_3D(MACRO_POLYGON_MODE_BACK), 1);
686 PUSH_DATA (push, NVC0_3D_MACRO_POLYGON_MODE_BACK_FILL);
687 IMMED_NVC0(push, NVC0_3D(POLYGON_SMOOTH_ENABLE), 0);
688 IMMED_NVC0(push, NVC0_3D(POLYGON_OFFSET_FILL_ENABLE), 0);
689 IMMED_NVC0(push, NVC0_3D(POLYGON_STIPPLE_ENABLE), 0);
690 IMMED_NVC0(push, NVC0_3D(CULL_FACE_ENABLE), 0);
691
692 /* zsa state */
693 IMMED_NVC0(push, NVC0_3D(DEPTH_TEST_ENABLE), 0);
694 IMMED_NVC0(push, NVC0_3D(STENCIL_ENABLE), 0);
695 IMMED_NVC0(push, NVC0_3D(ALPHA_TEST_ENABLE), 0);
696
697 /* disable transform feedback */
698 IMMED_NVC0(push, NVC0_3D(TFB_ENABLE), 0);
699 }
700
701 static void
702 nvc0_blitctx_pre_blit(struct nvc0_blitctx *ctx)
703 {
704 struct nvc0_context *nvc0 = ctx->nvc0;
705 struct nvc0_blitter *blitter = nvc0->screen->blitter;
706 int s;
707
708 ctx->saved.fb.width = nvc0->framebuffer.width;
709 ctx->saved.fb.height = nvc0->framebuffer.height;
710 ctx->saved.fb.nr_cbufs = nvc0->framebuffer.nr_cbufs;
711 ctx->saved.fb.cbufs[0] = nvc0->framebuffer.cbufs[0];
712 ctx->saved.fb.zsbuf = nvc0->framebuffer.zsbuf;
713
714 ctx->saved.rast = nvc0->rast;
715
716 ctx->saved.vp = nvc0->vertprog;
717 ctx->saved.tcp = nvc0->tctlprog;
718 ctx->saved.tep = nvc0->tevlprog;
719 ctx->saved.gp = nvc0->gmtyprog;
720 ctx->saved.fp = nvc0->fragprog;
721
722 nvc0->rast = &ctx->rast;
723
724 nvc0->vertprog = &blitter->vp;
725 nvc0->tctlprog = NULL;
726 nvc0->tevlprog = NULL;
727 nvc0->gmtyprog = NULL;
728 nvc0->fragprog = ctx->fp;
729
730 for (s = 0; s <= 4; ++s) {
731 ctx->saved.num_textures[s] = nvc0->num_textures[s];
732 ctx->saved.num_samplers[s] = nvc0->num_samplers[s];
733 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
734 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
735 }
736 ctx->saved.texture[0] = nvc0->textures[4][0];
737 ctx->saved.texture[1] = nvc0->textures[4][1];
738 ctx->saved.sampler[0] = nvc0->samplers[4][0];
739 ctx->saved.sampler[1] = nvc0->samplers[4][1];
740
741 nvc0->samplers[4][0] = &blitter->sampler[ctx->filter];
742 nvc0->samplers[4][1] = &blitter->sampler[ctx->filter];
743
744 for (s = 0; s <= 3; ++s)
745 nvc0->num_samplers[s] = 0;
746 nvc0->num_samplers[4] = 2;
747
748 ctx->saved.dirty = nvc0->dirty;
749
750 nvc0->textures_dirty[4] |= 3;
751 nvc0->samplers_dirty[4] |= 3;
752
753 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
754 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 0));
755 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 1));
756
757 nvc0->dirty = NVC0_NEW_FRAMEBUFFER |
758 NVC0_NEW_VERTPROG | NVC0_NEW_FRAGPROG |
759 NVC0_NEW_TCTLPROG | NVC0_NEW_TEVLPROG | NVC0_NEW_GMTYPROG |
760 NVC0_NEW_TEXTURES | NVC0_NEW_SAMPLERS;
761 }
762
763 static void
764 nvc0_blitctx_post_blit(struct nvc0_blitctx *blit)
765 {
766 struct nvc0_context *nvc0 = blit->nvc0;
767 int s;
768
769 pipe_surface_reference(&nvc0->framebuffer.cbufs[0], NULL);
770
771 nvc0->framebuffer.width = blit->saved.fb.width;
772 nvc0->framebuffer.height = blit->saved.fb.height;
773 nvc0->framebuffer.nr_cbufs = blit->saved.fb.nr_cbufs;
774 nvc0->framebuffer.cbufs[0] = blit->saved.fb.cbufs[0];
775 nvc0->framebuffer.zsbuf = blit->saved.fb.zsbuf;
776
777 nvc0->rast = blit->saved.rast;
778
779 nvc0->vertprog = blit->saved.vp;
780 nvc0->tctlprog = blit->saved.tcp;
781 nvc0->tevlprog = blit->saved.tep;
782 nvc0->gmtyprog = blit->saved.gp;
783 nvc0->fragprog = blit->saved.fp;
784
785 pipe_sampler_view_reference(&nvc0->textures[4][0], NULL);
786 pipe_sampler_view_reference(&nvc0->textures[4][1], NULL);
787
788 for (s = 0; s <= 4; ++s) {
789 nvc0->num_textures[s] = blit->saved.num_textures[s];
790 nvc0->num_samplers[s] = blit->saved.num_samplers[s];
791 nvc0->textures_dirty[s] = (1 << nvc0->num_textures[s]) - 1;
792 nvc0->samplers_dirty[s] = (1 << nvc0->num_samplers[s]) - 1;
793 }
794 nvc0->textures[4][0] = blit->saved.texture[0];
795 nvc0->textures[4][1] = blit->saved.texture[1];
796 nvc0->samplers[4][0] = blit->saved.sampler[0];
797 nvc0->samplers[4][1] = blit->saved.sampler[1];
798
799 nvc0->textures_dirty[4] |= 3;
800 nvc0->samplers_dirty[4] |= 3;
801
802 if (nvc0->cond_query)
803 nvc0->base.pipe.render_condition(&nvc0->base.pipe, nvc0->cond_query,
804 nvc0->cond_cond, nvc0->cond_mode);
805
806 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
807 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 0));
808 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(4, 1));
809
810 nvc0->dirty = blit->saved.dirty |
811 (NVC0_NEW_FRAMEBUFFER | NVC0_NEW_SCISSOR | NVC0_NEW_SAMPLE_MASK |
812 NVC0_NEW_RASTERIZER | NVC0_NEW_ZSA | NVC0_NEW_BLEND |
813 NVC0_NEW_TEXTURES | NVC0_NEW_SAMPLERS |
814 NVC0_NEW_VERTPROG | NVC0_NEW_FRAGPROG |
815 NVC0_NEW_TCTLPROG | NVC0_NEW_TEVLPROG | NVC0_NEW_GMTYPROG |
816 NVC0_NEW_TFB_TARGETS);
817 }
818
819 static void
820 nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
821 {
822 struct nvc0_blitctx *blit = nvc0->blit;
823 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
824 struct pipe_resource *src = info->src.resource;
825 struct pipe_resource *dst = info->dst.resource;
826 int32_t minx, maxx, miny, maxy;
827 int32_t i;
828 float x0, x1, y0, y1, z;
829 float dz;
830 float x_range, y_range;
831
832 blit->mode = nv50_blit_select_mode(info);
833 blit->color_mask = nv50_blit_derive_color_mask(info);
834 blit->filter = nv50_blit_get_filter(info);
835
836 nvc0_blit_select_fp(blit, info);
837 nvc0_blitctx_pre_blit(blit);
838
839 nvc0_blit_set_dst(blit, dst, info->dst.level, -1, info->dst.format);
840 nvc0_blit_set_src(blit, src, info->src.level, -1, info->src.format,
841 blit->filter);
842
843 nvc0_blitctx_prepare_state(blit);
844
845 nvc0_state_validate(nvc0, ~0, 48);
846
847 x_range = (float)info->src.box.width / (float)info->dst.box.width;
848 y_range = (float)info->src.box.height / (float)info->dst.box.height;
849
850 x0 = (float)info->src.box.x - x_range * (float)info->dst.box.x;
851 y0 = (float)info->src.box.y - y_range * (float)info->dst.box.y;
852
853 x1 = x0 + 16384.0f * x_range;
854 y1 = y0 + 16384.0f * y_range;
855
856 x0 *= (float)(1 << nv50_miptree(src)->ms_x);
857 x1 *= (float)(1 << nv50_miptree(src)->ms_x);
858 y0 *= (float)(1 << nv50_miptree(src)->ms_y);
859 y1 *= (float)(1 << nv50_miptree(src)->ms_y);
860
861 if (src->last_level > 0) {
862 /* If there are mip maps, GPU always assumes normalized coordinates. */
863 const unsigned l = info->src.level;
864 const float fh = u_minify(src->width0 << nv50_miptree(src)->ms_x, l);
865 const float fv = u_minify(src->height0 << nv50_miptree(src)->ms_y, l);
866 x0 /= fh;
867 x1 /= fh;
868 y0 /= fv;
869 y1 /= fv;
870 }
871
872 dz = (float)info->src.box.depth / (float)info->dst.box.depth;
873 z = (float)info->src.box.z;
874 if (nv50_miptree(src)->layout_3d)
875 z += 0.5f * dz;
876
877 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
878 IMMED_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 0x2 |
879 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1);
880 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
881 PUSH_DATA (push, nvc0->framebuffer.width << 16);
882 PUSH_DATA (push, nvc0->framebuffer.height << 16);
883
884 /* Draw a large triangle in screen coordinates covering the whole
885 * render target, with scissors defining the destination region.
886 * The vertex is supplied with non-normalized texture coordinates
887 * arranged in a way to yield the desired offset and scale.
888 */
889
890 minx = info->dst.box.x;
891 maxx = info->dst.box.x + info->dst.box.width;
892 miny = info->dst.box.y;
893 maxy = info->dst.box.y + info->dst.box.height;
894 if (info->scissor_enable) {
895 minx = MAX2(minx, info->scissor.minx);
896 maxx = MIN2(maxx, info->scissor.maxx);
897 miny = MAX2(miny, info->scissor.miny);
898 maxy = MIN2(maxy, info->scissor.maxy);
899 }
900 BEGIN_NVC0(push, NVC0_3D(SCISSOR_HORIZ(0)), 2);
901 PUSH_DATA (push, (maxx << 16) | minx);
902 PUSH_DATA (push, (maxy << 16) | miny);
903
904 for (i = 0; i < info->dst.box.depth; ++i, z += dz) {
905 if (info->dst.box.z + i) {
906 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
907 PUSH_DATA (push, info->dst.box.z + i);
908 }
909
910 IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL),
911 NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
912
913 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 4);
914 PUSH_DATA (push, 0x74301);
915 PUSH_DATAf(push, x0);
916 PUSH_DATAf(push, y0);
917 PUSH_DATAf(push, z);
918 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3);
919 PUSH_DATA (push, 0x74200);
920 PUSH_DATAf(push, 0.0f);
921 PUSH_DATAf(push, 0.0f);
922 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 4);
923 PUSH_DATA (push, 0x74301);
924 PUSH_DATAf(push, x1);
925 PUSH_DATAf(push, y0);
926 PUSH_DATAf(push, z);
927 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3);
928 PUSH_DATA (push, 0x74200);
929 PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_x);
930 PUSH_DATAf(push, 0.0f);
931 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 4);
932 PUSH_DATA (push, 0x74301);
933 PUSH_DATAf(push, x0);
934 PUSH_DATAf(push, y1);
935 PUSH_DATAf(push, z);
936 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3);
937 PUSH_DATA (push, 0x74200);
938 PUSH_DATAf(push, 0.0f);
939 PUSH_DATAf(push, 16384 << nv50_miptree(dst)->ms_y);
940
941 IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
942 }
943 if (info->dst.box.z + info->dst.box.depth - 1)
944 IMMED_NVC0(push, NVC0_3D(LAYER), 0);
945
946 nvc0_blitctx_post_blit(blit);
947
948 /* restore viewport */
949
950 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
951 PUSH_DATA (push, nvc0->framebuffer.width << 16);
952 PUSH_DATA (push, nvc0->framebuffer.height << 16);
953 IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
954 }
955
956 static void
957 nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
958 {
959 struct nouveau_pushbuf *push = nvc0->base.pushbuf;
960 struct nv50_miptree *dst = nv50_miptree(info->dst.resource);
961 struct nv50_miptree *src = nv50_miptree(info->src.resource);
962 const int32_t srcx_adj = info->src.box.width < 0 ? -1 : 0;
963 const int32_t srcy_adj = info->src.box.height < 0 ? -1 : 0;
964 const int dz = info->dst.box.z;
965 const int sz = info->src.box.z;
966 uint32_t dstw, dsth;
967 int32_t dstx, dsty;
968 int64_t srcx, srcy;
969 int64_t du_dx, dv_dy;
970 int i;
971 uint32_t mode;
972 uint32_t mask = nv50_blit_eng2d_get_mask(info);
973 boolean b;
974
975 mode = nv50_blit_get_filter(info) ?
976 NVC0_2D_BLIT_CONTROL_FILTER_BILINEAR :
977 NVC0_2D_BLIT_CONTROL_FILTER_POINT_SAMPLE;
978 mode |= (src->base.base.nr_samples > dst->base.base.nr_samples) ?
979 NVC0_2D_BLIT_CONTROL_ORIGIN_CORNER : NVC0_2D_BLIT_CONTROL_ORIGIN_CENTER;
980
981 du_dx = ((int64_t)info->src.box.width << 32) / info->dst.box.width;
982 dv_dy = ((int64_t)info->src.box.height << 32) / info->dst.box.height;
983
984 b = info->dst.format == info->src.format;
985 nvc0_2d_texture_set(push, 1, dst, info->dst.level, dz, info->dst.format, b);
986 nvc0_2d_texture_set(push, 0, src, info->src.level, sz, info->src.format, b);
987
988 if (info->scissor_enable) {
989 BEGIN_NVC0(push, NVC0_2D(CLIP_X), 5);
990 PUSH_DATA (push, info->scissor.minx << dst->ms_x);
991 PUSH_DATA (push, info->scissor.miny << dst->ms_y);
992 PUSH_DATA (push, (info->scissor.maxx - info->scissor.minx) << dst->ms_x);
993 PUSH_DATA (push, (info->scissor.maxy - info->scissor.miny) << dst->ms_y);
994 PUSH_DATA (push, 1); /* enable */
995 }
996
997 if (mask != 0xffffffff) {
998 IMMED_NVC0(push, NVC0_2D(ROP), 0xca); /* DPSDxax */
999 IMMED_NVC0(push, NVC0_2D(PATTERN_COLOR_FORMAT),
1000 NVC0_2D_PATTERN_COLOR_FORMAT_32BPP);
1001 BEGIN_NVC0(push, NVC0_2D(PATTERN_COLOR(0)), 4);
1002 PUSH_DATA (push, 0x00000000);
1003 PUSH_DATA (push, mask);
1004 PUSH_DATA (push, 0xffffffff);
1005 PUSH_DATA (push, 0xffffffff);
1006 IMMED_NVC0(push, NVC0_2D(OPERATION), NVC0_2D_OPERATION_ROP);
1007 } else
1008 if (info->src.format != info->dst.format) {
1009 if (info->src.format == PIPE_FORMAT_R8_UNORM ||
1010 info->src.format == PIPE_FORMAT_R8_SNORM ||
1011 info->src.format == PIPE_FORMAT_R16_UNORM ||
1012 info->src.format == PIPE_FORMAT_R16_SNORM ||
1013 info->src.format == PIPE_FORMAT_R16_FLOAT ||
1014 info->src.format == PIPE_FORMAT_R32_FLOAT) {
1015 mask = 0xffff0000; /* also makes condition for OPERATION reset true */
1016 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1017 PUSH_DATA (push, mask);
1018 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY_PREMULT);
1019 } else
1020 if (info->src.format == PIPE_FORMAT_A8_UNORM) {
1021 mask = 0xff000000;
1022 BEGIN_NVC0(push, NVC0_2D(BETA4), 2);
1023 PUSH_DATA (push, mask);
1024 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY_PREMULT);
1025 }
1026 }
1027
1028 if (src->ms_x > dst->ms_x || src->ms_y > dst->ms_y) {
1029 /* ms_x is always >= ms_y */
1030 du_dx <<= src->ms_x - dst->ms_x;
1031 dv_dy <<= src->ms_y - dst->ms_y;
1032 } else {
1033 du_dx >>= dst->ms_x - src->ms_x;
1034 dv_dy >>= dst->ms_y - src->ms_y;
1035 }
1036
1037 srcx = (int64_t)(info->src.box.x + srcx_adj) << (src->ms_x + 32);
1038 srcy = (int64_t)(info->src.box.y + srcy_adj) << (src->ms_y + 32);
1039
1040 if (src->base.base.nr_samples > dst->base.base.nr_samples) {
1041 /* center src coorinates for proper MS resolve filtering */
1042 srcx += (int64_t)(src->ms_x + 0) << 32;
1043 srcy += (int64_t)(src->ms_y + 1) << 31;
1044 }
1045
1046 dstx = info->dst.box.x << dst->ms_x;
1047 dsty = info->dst.box.y << dst->ms_y;
1048
1049 dstw = info->dst.box.width << dst->ms_x;
1050 dsth = info->dst.box.height << dst->ms_y;
1051
1052 if (dstx < 0) {
1053 dstw += dstx;
1054 srcx -= du_dx * dstx;
1055 dstx = 0;
1056 }
1057 if (dsty < 0) {
1058 dsth += dsty;
1059 srcy -= dv_dy * dsty;
1060 dsty = 0;
1061 }
1062
1063 IMMED_NVC0(push, NVC0_2D(BLIT_CONTROL), mode);
1064 BEGIN_NVC0(push, NVC0_2D(BLIT_DST_X), 4);
1065 PUSH_DATA (push, dstx);
1066 PUSH_DATA (push, dsty);
1067 PUSH_DATA (push, dstw);
1068 PUSH_DATA (push, dsth);
1069 BEGIN_NVC0(push, NVC0_2D(BLIT_DU_DX_FRACT), 4);
1070 PUSH_DATA (push, du_dx);
1071 PUSH_DATA (push, du_dx >> 32);
1072 PUSH_DATA (push, dv_dy);
1073 PUSH_DATA (push, dv_dy >> 32);
1074
1075 BCTX_REFN(nvc0->bufctx, 2D, &dst->base, WR);
1076 BCTX_REFN(nvc0->bufctx, 2D, &src->base, RD);
1077 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx);
1078 if (nouveau_pushbuf_validate(nvc0->base.pushbuf))
1079 return;
1080
1081 for (i = 0; i < info->dst.box.depth; ++i) {
1082 if (i > 0) {
1083 /* no scaling in z-direction possible for eng2d blits */
1084 if (dst->layout_3d) {
1085 BEGIN_NVC0(push, NVC0_2D(DST_LAYER), 1);
1086 PUSH_DATA (push, info->dst.box.z + i);
1087 } else {
1088 const unsigned z = info->dst.box.z + i;
1089 BEGIN_NVC0(push, NVC0_2D(DST_ADDRESS_HIGH), 2);
1090 PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
1091 PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
1092 }
1093 if (src->layout_3d) {
1094 /* not possible because of depth tiling */
1095 assert(0);
1096 } else {
1097 const unsigned z = info->src.box.z + i;
1098 BEGIN_NVC0(push, NVC0_2D(SRC_ADDRESS_HIGH), 2);
1099 PUSH_DATAh(push, src->base.address + z * src->layer_stride);
1100 PUSH_DATA (push, src->base.address + z * src->layer_stride);
1101 }
1102 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_Y_INT), 1); /* trigger */
1103 PUSH_DATA (push, srcy >> 32);
1104 } else {
1105 BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_X_FRACT), 4);
1106 PUSH_DATA (push, srcx);
1107 PUSH_DATA (push, srcx >> 32);
1108 PUSH_DATA (push, srcy);
1109 PUSH_DATA (push, srcy >> 32);
1110 }
1111 }
1112 nvc0_resource_validate(&dst->base, NOUVEAU_BO_WR);
1113 nvc0_resource_validate(&src->base, NOUVEAU_BO_RD);
1114
1115 nouveau_bufctx_reset(nvc0->bufctx, NVC0_BIND_2D);
1116
1117 if (info->scissor_enable)
1118 IMMED_NVC0(push, NVC0_2D(CLIP_ENABLE), 0);
1119 if (mask != 0xffffffff)
1120 IMMED_NVC0(push, NVC0_2D(OPERATION), NVC0_2D_OPERATION_SRCCOPY);
1121 }
1122
1123 static void
1124 nvc0_blit(struct pipe_context *pipe, const struct pipe_blit_info *info)
1125 {
1126 struct nvc0_context *nvc0 = nvc0_context(pipe);
1127 boolean eng3d = FALSE;
1128
1129 if (util_format_is_depth_or_stencil(info->dst.resource->format)) {
1130 if (!(info->mask & PIPE_MASK_ZS))
1131 return;
1132 if (info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT ||
1133 info->dst.resource->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
1134 eng3d = TRUE;
1135 if (info->filter != PIPE_TEX_FILTER_NEAREST)
1136 eng3d = TRUE;
1137 } else {
1138 if (!(info->mask & PIPE_MASK_RGBA))
1139 return;
1140 if (info->mask != PIPE_MASK_RGBA)
1141 eng3d = TRUE;
1142 }
1143
1144 if (nv50_miptree(info->src.resource)->layout_3d) {
1145 eng3d = TRUE;
1146 } else
1147 if (info->src.box.depth != info->dst.box.depth) {
1148 eng3d = TRUE;
1149 debug_printf("blit: cannot filter array or cube textures in z direction");
1150 }
1151
1152 if (!eng3d && info->dst.format != info->src.format) {
1153 if (!nv50_2d_dst_format_faithful(info->dst.format)) {
1154 eng3d = TRUE;
1155 } else
1156 if (!nv50_2d_src_format_faithful(info->src.format)) {
1157 if (!util_format_is_luminance(info->src.format)) {
1158 if (util_format_is_intensity(info->src.format))
1159 eng3d = info->src.format != PIPE_FORMAT_I8_UNORM;
1160 else
1161 if (!nv50_2d_dst_format_ops_supported(info->dst.format))
1162 eng3d = TRUE;
1163 else
1164 eng3d = !nv50_2d_format_supported(info->src.format);
1165 }
1166 } else
1167 if (util_format_is_luminance_alpha(info->src.format))
1168 eng3d = TRUE;
1169 }
1170
1171 if (info->src.resource->nr_samples == 8 &&
1172 info->dst.resource->nr_samples <= 1)
1173 eng3d = TRUE;
1174 #if 0
1175 /* FIXME: can't make this work with eng2d anymore, at least not on nv50 */
1176 if (info->src.resource->nr_samples > 1 ||
1177 info->dst.resource->nr_samples > 1)
1178 eng3d = TRUE;
1179 #endif
1180 /* FIXME: find correct src coordinates adjustments */
1181 if ((info->src.box.width != info->dst.box.width &&
1182 info->src.box.width != -info->dst.box.width) ||
1183 (info->src.box.height != info->dst.box.height &&
1184 info->src.box.height != -info->dst.box.height))
1185 eng3d = TRUE;
1186
1187 if (!eng3d)
1188 nvc0_blit_eng2d(nvc0, info);
1189 else
1190 nvc0_blit_3d(nvc0, info);
1191
1192 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_blit_count, 1);
1193 }
1194
1195 boolean
1196 nvc0_blitter_create(struct nvc0_screen *screen)
1197 {
1198 screen->blitter = CALLOC_STRUCT(nvc0_blitter);
1199 if (!screen->blitter) {
1200 NOUVEAU_ERR("failed to allocate blitter struct\n");
1201 return FALSE;
1202 }
1203 screen->blitter->screen = screen;
1204
1205 pipe_mutex_init(screen->blitter->mutex);
1206
1207 nvc0_blitter_make_vp(screen->blitter);
1208 nvc0_blitter_make_sampler(screen->blitter);
1209
1210 return TRUE;
1211 }
1212
1213 void
1214 nvc0_blitter_destroy(struct nvc0_screen *screen)
1215 {
1216 struct nvc0_blitter *blitter = screen->blitter;
1217 unsigned i, m;
1218
1219 for (i = 0; i < NV50_BLIT_MAX_TEXTURE_TYPES; ++i) {
1220 for (m = 0; m < NV50_BLIT_MODES; ++m) {
1221 struct nvc0_program *prog = blitter->fp[i][m];
1222 if (prog) {
1223 nvc0_program_destroy(NULL, prog);
1224 FREE((void *)prog->pipe.tokens);
1225 FREE(prog);
1226 }
1227 }
1228 }
1229
1230 FREE(blitter);
1231 }
1232
1233 boolean
1234 nvc0_blitctx_create(struct nvc0_context *nvc0)
1235 {
1236 nvc0->blit = CALLOC_STRUCT(nvc0_blitctx);
1237 if (!nvc0->blit) {
1238 NOUVEAU_ERR("failed to allocate blit context\n");
1239 return FALSE;
1240 }
1241
1242 nvc0->blit->nvc0 = nvc0;
1243
1244 nvc0->blit->rast.pipe.half_pixel_center = 1;
1245
1246 return TRUE;
1247 }
1248
1249 void
1250 nvc0_init_surface_functions(struct nvc0_context *nvc0)
1251 {
1252 struct pipe_context *pipe = &nvc0->base.pipe;
1253
1254 pipe->resource_copy_region = nvc0_resource_copy_region;
1255 pipe->blit = nvc0_blit;
1256 pipe->clear_render_target = nvc0_clear_render_target;
1257 pipe->clear_depth_stencil = nvc0_clear_depth_stencil;
1258 }
1259