nv50,nvc0: extensive surface format renaming to get consistency
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_surface.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include <stdint.h>
24
25 #include "pipe/p_defines.h"
26
27 #include "util/u_inlines.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_format.h"
30 #include "util/u_surface.h"
31
32 #include "nvc0_context.h"
33 #include "nvc0_resource.h"
34
35 #include "nv50/nv50_defs.xml.h"
36
37 #define NVC0_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
38
39 /* return TRUE for formats that can be converted among each other by NVC0_2D */
40 static INLINE boolean
41 nvc0_2d_format_faithful(enum pipe_format format)
42 {
43 uint8_t id = nvc0_format_table[format].rt;
44
45 return (id >= 0xc0) && (NVC0_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0)));
46 }
47
48 static INLINE uint8_t
49 nvc0_2d_format(enum pipe_format format)
50 {
51 uint8_t id = nvc0_format_table[format].rt;
52
53 /* Hardware values for color formats range from 0xc0 to 0xff,
54 * but the 2D engine doesn't support all of them.
55 */
56 if (nvc0_2d_format_faithful(format))
57 return id;
58
59 switch (util_format_get_blocksize(format)) {
60 case 1:
61 return NV50_SURFACE_FORMAT_R8_UNORM;
62 case 2:
63 return NV50_SURFACE_FORMAT_R16_UNORM;
64 case 4:
65 return NV50_SURFACE_FORMAT_BGRA8_UNORM;
66 case 8:
67 return NV50_SURFACE_FORMAT_RGBA16_UNORM;
68 case 16:
69 return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
70 default:
71 return 0;
72 }
73 }
74
75 static int
76 nvc0_2d_texture_set(struct nouveau_channel *chan, int dst,
77 struct nv50_miptree *mt, unsigned level, unsigned layer)
78 {
79 struct nouveau_bo *bo = mt->base.bo;
80 uint32_t width, height, depth;
81 uint32_t format;
82 uint32_t mthd = dst ? NVC0_2D_DST_FORMAT : NVC0_2D_SRC_FORMAT;
83 uint32_t flags = mt->base.domain | (dst ? NOUVEAU_BO_WR : NOUVEAU_BO_RD);
84 uint32_t offset = mt->level[level].offset;
85
86 format = nvc0_2d_format(mt->base.base.format);
87 if (!format) {
88 NOUVEAU_ERR("invalid/unsupported surface format: %s\n",
89 util_format_name(mt->base.base.format));
90 return 1;
91 }
92
93 width = u_minify(mt->base.base.width0, level) << mt->ms_x;
94 height = u_minify(mt->base.base.height0, level) << mt->ms_y;
95 depth = u_minify(mt->base.base.depth0, level);
96
97 /* layer has to be < depth, and depth > tile depth / 2 */
98
99 if (!mt->layout_3d) {
100 offset += mt->layer_stride * layer;
101 layer = 0;
102 depth = 1;
103 } else
104 if (!dst) {
105 offset += nvc0_mt_zslice_offset(mt, level, layer);
106 layer = 0;
107 }
108
109 if (!(bo->tile_flags & NOUVEAU_BO_TILE_LAYOUT_MASK)) {
110 BEGIN_RING(chan, RING_2D_(mthd), 2);
111 OUT_RING (chan, format);
112 OUT_RING (chan, 1);
113 BEGIN_RING(chan, RING_2D_(mthd + 0x14), 5);
114 OUT_RING (chan, mt->level[level].pitch);
115 OUT_RING (chan, width);
116 OUT_RING (chan, height);
117 OUT_RELOCh(chan, bo, offset, flags);
118 OUT_RELOCl(chan, bo, offset, flags);
119 } else {
120 BEGIN_RING(chan, RING_2D_(mthd), 5);
121 OUT_RING (chan, format);
122 OUT_RING (chan, 0);
123 OUT_RING (chan, mt->level[level].tile_mode);
124 OUT_RING (chan, depth);
125 OUT_RING (chan, layer);
126 BEGIN_RING(chan, RING_2D_(mthd + 0x18), 4);
127 OUT_RING (chan, width);
128 OUT_RING (chan, height);
129 OUT_RELOCh(chan, bo, offset, flags);
130 OUT_RELOCl(chan, bo, offset, flags);
131 }
132
133 #if 0
134 if (dst) {
135 BEGIN_RING(chan, RING_2D_(NVC0_2D_CLIP_X), 4);
136 OUT_RING (chan, 0);
137 OUT_RING (chan, 0);
138 OUT_RING (chan, width);
139 OUT_RING (chan, height);
140 }
141 #endif
142 return 0;
143 }
144
145 static int
146 nvc0_2d_texture_do_copy(struct nouveau_channel *chan,
147 struct nv50_miptree *dst, unsigned dst_level,
148 unsigned dx, unsigned dy, unsigned dz,
149 struct nv50_miptree *src, unsigned src_level,
150 unsigned sx, unsigned sy, unsigned sz,
151 unsigned w, unsigned h)
152 {
153 static const uint32_t duvdxy[5] =
154 {
155 0x40000000, 0x80000000, 0x00000001, 0x00000002, 0x00000004
156 };
157
158 int ret;
159 uint32_t ctrl = 0x00;
160
161 ret = MARK_RING(chan, 2 * 16 + 32, 4);
162 if (ret)
163 return ret;
164
165 ret = nvc0_2d_texture_set(chan, 1, dst, dst_level, dz);
166 if (ret)
167 return ret;
168
169 ret = nvc0_2d_texture_set(chan, 0, src, src_level, sz);
170 if (ret)
171 return ret;
172
173 /* NOTE: 2D engine doesn't work for MS8 */
174 if (src->ms_x)
175 ctrl = 0x11;
176
177 /* 0/1 = CENTER/CORNER, 00/10 = POINT/BILINEAR */
178 BEGIN_RING(chan, RING_2D(BLIT_CONTROL), 1);
179 OUT_RING (chan, ctrl);
180 BEGIN_RING(chan, RING_2D(BLIT_DST_X), 4);
181 OUT_RING (chan, dx << dst->ms_x);
182 OUT_RING (chan, dy << dst->ms_y);
183 OUT_RING (chan, w << dst->ms_x);
184 OUT_RING (chan, h << dst->ms_y);
185 BEGIN_RING(chan, RING_2D(BLIT_DU_DX_FRACT), 4);
186 OUT_RING (chan, duvdxy[2 + ((int)src->ms_x - (int)dst->ms_x)] & 0xf0000000);
187 OUT_RING (chan, duvdxy[2 + ((int)src->ms_x - (int)dst->ms_x)] & 0x0000000f);
188 OUT_RING (chan, duvdxy[2 + ((int)src->ms_y - (int)dst->ms_y)] & 0xf0000000);
189 OUT_RING (chan, duvdxy[2 + ((int)src->ms_y - (int)dst->ms_y)] & 0x0000000f);
190 BEGIN_RING(chan, RING_2D(BLIT_SRC_X_FRACT), 4);
191 OUT_RING (chan, 0);
192 OUT_RING (chan, sx << src->ms_x);
193 OUT_RING (chan, 0);
194 OUT_RING (chan, sy << src->ms_x);
195
196 return 0;
197 }
198
199 static void
200 nvc0_resource_copy_region(struct pipe_context *pipe,
201 struct pipe_resource *dst, unsigned dst_level,
202 unsigned dstx, unsigned dsty, unsigned dstz,
203 struct pipe_resource *src, unsigned src_level,
204 const struct pipe_box *src_box)
205 {
206 struct nvc0_screen *screen = nvc0_context(pipe)->screen;
207 int ret;
208 unsigned dst_layer = dstz, src_layer = src_box->z;
209
210 /* Fallback for buffers. */
211 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
212 util_resource_copy_region(pipe, dst, dst_level, dstx, dsty, dstz,
213 src, src_level, src_box);
214 return;
215 }
216
217 nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
218
219 if (src->format == dst->format && src->nr_samples == dst->nr_samples) {
220 struct nv50_m2mf_rect drect, srect;
221 unsigned i;
222 unsigned nx = util_format_get_nblocksx(src->format, src_box->width);
223 unsigned ny = util_format_get_nblocksy(src->format, src_box->height);
224
225 nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
226 nv50_m2mf_rect_setup(&srect, src, src_level,
227 src_box->x, src_box->y, src_box->z);
228
229 for (i = 0; i < src_box->depth; ++i) {
230 nvc0_m2mf_transfer_rect(&screen->base.base, &drect, &srect, nx, ny);
231
232 if (nv50_miptree(dst)->layout_3d)
233 drect.z++;
234 else
235 drect.base += nv50_miptree(dst)->layer_stride;
236
237 if (nv50_miptree(src)->layout_3d)
238 srect.z++;
239 else
240 srect.base += nv50_miptree(src)->layer_stride;
241 }
242 return;
243 }
244
245 assert(nvc0_2d_format_faithful(src->format));
246 assert(nvc0_2d_format_faithful(dst->format));
247
248 for (; dst_layer < dstz + src_box->depth; ++dst_layer, ++src_layer) {
249 ret = nvc0_2d_texture_do_copy(screen->base.channel,
250 nv50_miptree(dst), dst_level,
251 dstx, dsty, dst_layer,
252 nv50_miptree(src), src_level,
253 src_box->x, src_box->y, src_layer,
254 src_box->width, src_box->height);
255 if (ret)
256 return;
257 }
258 }
259
260 static void
261 nvc0_clear_render_target(struct pipe_context *pipe,
262 struct pipe_surface *dst,
263 const float *rgba,
264 unsigned dstx, unsigned dsty,
265 unsigned width, unsigned height)
266 {
267 struct nvc0_context *nv50 = nvc0_context(pipe);
268 struct nvc0_screen *screen = nv50->screen;
269 struct nouveau_channel *chan = screen->base.channel;
270 struct nv50_miptree *mt = nv50_miptree(dst->texture);
271 struct nv50_surface *sf = nv50_surface(dst);
272 struct nouveau_bo *bo = mt->base.bo;
273
274 BEGIN_RING(chan, RING_3D(CLEAR_COLOR(0)), 4);
275 OUT_RINGf (chan, rgba[0]);
276 OUT_RINGf (chan, rgba[1]);
277 OUT_RINGf (chan, rgba[2]);
278 OUT_RINGf (chan, rgba[3]);
279
280 if (MARK_RING(chan, 18, 2))
281 return;
282
283 BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
284 OUT_RING (chan, 1);
285 BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(0)), 9);
286 OUT_RELOCh(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
287 OUT_RELOCl(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
288 OUT_RING (chan, sf->width);
289 OUT_RING (chan, sf->height);
290 OUT_RING (chan, nvc0_format_table[dst->format].rt);
291 OUT_RING (chan, (mt->layout_3d << 16) |
292 mt->level[sf->base.u.tex.level].tile_mode);
293 OUT_RING (chan, dst->u.tex.first_layer + sf->depth);
294 OUT_RING (chan, mt->layer_stride >> 2);
295 OUT_RING (chan, dst->u.tex.first_layer);
296
297 BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 2);
298 OUT_RING (chan, ((dstx + width) << 16) | dstx);
299 OUT_RING (chan, ((dsty + height) << 16) | dsty);
300 IMMED_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
301
302 BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
303 OUT_RING (chan, 0x3c);
304
305 IMMED_RING(chan, RING_3D(CLIP_RECTS_EN), 0);
306
307 nv50->dirty |= NVC0_NEW_FRAMEBUFFER;
308 }
309
310 static void
311 nvc0_clear_depth_stencil(struct pipe_context *pipe,
312 struct pipe_surface *dst,
313 unsigned clear_flags,
314 double depth,
315 unsigned stencil,
316 unsigned dstx, unsigned dsty,
317 unsigned width, unsigned height)
318 {
319 struct nvc0_context *nv50 = nvc0_context(pipe);
320 struct nvc0_screen *screen = nv50->screen;
321 struct nouveau_channel *chan = screen->base.channel;
322 struct nv50_miptree *mt = nv50_miptree(dst->texture);
323 struct nv50_surface *sf = nv50_surface(dst);
324 struct nouveau_bo *bo = mt->base.bo;
325 uint32_t mode = 0;
326 int unk = mt->base.base.target == PIPE_TEXTURE_2D;
327
328 if (clear_flags & PIPE_CLEAR_DEPTH) {
329 BEGIN_RING(chan, RING_3D(CLEAR_DEPTH), 1);
330 OUT_RINGf (chan, depth);
331 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
332 }
333
334 if (clear_flags & PIPE_CLEAR_STENCIL) {
335 BEGIN_RING(chan, RING_3D(CLEAR_STENCIL), 1);
336 OUT_RING (chan, stencil & 0xff);
337 mode |= NVC0_3D_CLEAR_BUFFERS_S;
338 }
339
340 if (MARK_RING(chan, 17, 2))
341 return;
342
343 BEGIN_RING(chan, RING_3D(ZETA_ADDRESS_HIGH), 5);
344 OUT_RELOCh(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
345 OUT_RELOCl(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
346 OUT_RING (chan, nvc0_format_table[dst->format].rt);
347 OUT_RING (chan, mt->level[sf->base.u.tex.level].tile_mode);
348 OUT_RING (chan, mt->layer_stride >> 2);
349 BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1);
350 OUT_RING (chan, 1);
351 BEGIN_RING(chan, RING_3D(ZETA_HORIZ), 3);
352 OUT_RING (chan, sf->width);
353 OUT_RING (chan, sf->height);
354 OUT_RING (chan, (unk << 16) | (dst->u.tex.first_layer + sf->depth));
355 BEGIN_RING(chan, RING_3D(ZETA_BASE_LAYER), 1);
356 OUT_RING (chan, dst->u.tex.first_layer);
357
358 BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 2);
359 OUT_RING (chan, ((dstx + width) << 16) | dstx);
360 OUT_RING (chan, ((dsty + height) << 16) | dsty);
361 IMMED_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
362
363 BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
364 OUT_RING (chan, mode);
365
366 IMMED_RING(chan, RING_3D(CLIP_RECTS_EN), 0);
367
368 nv50->dirty |= NVC0_NEW_FRAMEBUFFER;
369 }
370
371 void
372 nvc0_clear(struct pipe_context *pipe, unsigned buffers,
373 const float *rgba, double depth, unsigned stencil)
374 {
375 struct nvc0_context *nvc0 = nvc0_context(pipe);
376 struct nouveau_channel *chan = nvc0->screen->base.channel;
377 struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
378 unsigned i;
379 const unsigned dirty = nvc0->dirty;
380 uint32_t mode = 0;
381
382 /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */
383 nvc0->dirty &= NVC0_NEW_FRAMEBUFFER;
384 if (!nvc0_state_validate(nvc0))
385 return;
386
387 if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
388 BEGIN_RING(chan, RING_3D(CLEAR_COLOR(0)), 4);
389 OUT_RINGf (chan, rgba[0]);
390 OUT_RINGf (chan, rgba[1]);
391 OUT_RINGf (chan, rgba[2]);
392 OUT_RINGf (chan, rgba[3]);
393 mode =
394 NVC0_3D_CLEAR_BUFFERS_R | NVC0_3D_CLEAR_BUFFERS_G |
395 NVC0_3D_CLEAR_BUFFERS_B | NVC0_3D_CLEAR_BUFFERS_A;
396 }
397
398 if (buffers & PIPE_CLEAR_DEPTH) {
399 BEGIN_RING(chan, RING_3D(CLEAR_DEPTH), 1);
400 OUT_RING (chan, fui(depth));
401 mode |= NVC0_3D_CLEAR_BUFFERS_Z;
402 }
403
404 if (buffers & PIPE_CLEAR_STENCIL) {
405 BEGIN_RING(chan, RING_3D(CLEAR_STENCIL), 1);
406 OUT_RING (chan, stencil & 0xff);
407 mode |= NVC0_3D_CLEAR_BUFFERS_S;
408 }
409
410 BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
411 OUT_RING (chan, mode);
412
413 for (i = 1; i < fb->nr_cbufs; i++) {
414 BEGIN_RING(chan, RING_3D(CLEAR_BUFFERS), 1);
415 OUT_RING (chan, (i << 6) | 0x3c);
416 }
417
418 nvc0->dirty = dirty & ~NVC0_NEW_FRAMEBUFFER;
419 }
420
421 void
422 nvc0_init_surface_functions(struct nvc0_context *nvc0)
423 {
424 struct pipe_context *pipe = &nvc0->base.pipe;
425
426 pipe->resource_copy_region = nvc0_resource_copy_region;
427 pipe->clear_render_target = nvc0_clear_render_target;
428 pipe->clear_depth_stencil = nvc0_clear_depth_stencil;
429 }
430
431