2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "nvc0_context.h"
24 #include "nvc0_resource.h"
25 #include "nv50/nv50_texture.xml.h"
27 #include "util/u_format.h"
29 #define NV50_TIC_0_SWIZZLE__MASK \
30 (NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK | \
31 NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK)
33 static INLINE
uint32_t
34 nv50_tic_swizzle(uint32_t tc
, unsigned swz
, boolean tex_int
)
37 case PIPE_SWIZZLE_RED
:
38 return (tc
& NV50_TIC_0_MAPR__MASK
) >> NV50_TIC_0_MAPR__SHIFT
;
39 case PIPE_SWIZZLE_GREEN
:
40 return (tc
& NV50_TIC_0_MAPG__MASK
) >> NV50_TIC_0_MAPG__SHIFT
;
41 case PIPE_SWIZZLE_BLUE
:
42 return (tc
& NV50_TIC_0_MAPB__MASK
) >> NV50_TIC_0_MAPB__SHIFT
;
43 case PIPE_SWIZZLE_ALPHA
:
44 return (tc
& NV50_TIC_0_MAPA__MASK
) >> NV50_TIC_0_MAPA__SHIFT
;
45 case PIPE_SWIZZLE_ONE
:
46 return tex_int
? NV50_TIC_MAP_ONE_INT
: NV50_TIC_MAP_ONE_FLOAT
;
47 case PIPE_SWIZZLE_ZERO
:
49 return NV50_TIC_MAP_ZERO
;
53 struct pipe_sampler_view
*
54 nvc0_create_sampler_view(struct pipe_context
*pipe
,
55 struct pipe_resource
*texture
,
56 const struct pipe_sampler_view
*templ
)
58 const struct util_format_description
*desc
;
62 struct nv50_tic_entry
*view
;
63 struct nv50_miptree
*mt
= nv50_miptree(texture
);
66 view
= MALLOC_STRUCT(nv50_tic_entry
);
71 view
->pipe
.reference
.count
= 1;
72 view
->pipe
.texture
= NULL
;
73 view
->pipe
.context
= pipe
;
77 pipe_resource_reference(&view
->pipe
.texture
, texture
);
81 desc
= util_format_description(view
->pipe
.format
);
85 tic
[0] = nvc0_format_table
[view
->pipe
.format
].tic
;
87 tex_int
= util_format_is_pure_integer(view
->pipe
.format
);
89 swz
[0] = nv50_tic_swizzle(tic
[0], view
->pipe
.swizzle_r
, tex_int
);
90 swz
[1] = nv50_tic_swizzle(tic
[0], view
->pipe
.swizzle_g
, tex_int
);
91 swz
[2] = nv50_tic_swizzle(tic
[0], view
->pipe
.swizzle_b
, tex_int
);
92 swz
[3] = nv50_tic_swizzle(tic
[0], view
->pipe
.swizzle_a
, tex_int
);
93 tic
[0] = (tic
[0] & ~NV50_TIC_0_SWIZZLE__MASK
) |
94 (swz
[0] << NV50_TIC_0_MAPR__SHIFT
) |
95 (swz
[1] << NV50_TIC_0_MAPG__SHIFT
) |
96 (swz
[2] << NV50_TIC_0_MAPB__SHIFT
) |
97 (swz
[3] << NV50_TIC_0_MAPA__SHIFT
);
99 tic
[1] = /* mt->base.bo->offset; */ 0;
100 tic
[2] = /* mt->base.bo->offset >> 32 */ 0;
102 tic
[2] |= 0x10001000 | NV50_TIC_2_NO_BORDER
;
104 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
105 tic
[2] |= NV50_TIC_2_COLORSPACE_SRGB
;
107 if (mt
->base
.base
.target
!= PIPE_TEXTURE_RECT
)
108 tic
[2] |= NV50_TIC_2_NORMALIZED_COORDS
;
111 ((mt
->base
.bo
->tile_mode
& 0x0f0) << (22 - 4)) |
112 ((mt
->base
.bo
->tile_mode
& 0xf00) << (25 - 8));
114 depth
= MAX2(mt
->base
.base
.array_size
, mt
->base
.base
.depth0
);
116 if (mt
->base
.base
.target
== PIPE_TEXTURE_1D_ARRAY
||
117 /* mt->base.base.target == PIPE_TEXTURE_2D_ARRAY_MS || */
118 mt
->base
.base
.target
== PIPE_TEXTURE_2D_ARRAY
) {
119 /* there doesn't seem to be a base layer field in TIC */
120 tic
[1] = view
->pipe
.u
.tex
.first_layer
* mt
->layer_stride
;
121 depth
= view
->pipe
.u
.tex
.last_layer
- view
->pipe
.u
.tex
.first_layer
+ 1;
124 switch (mt
->base
.base
.target
) {
125 case PIPE_TEXTURE_1D
:
126 tic
[2] |= NV50_TIC_2_TARGET_1D
;
128 /* case PIPE_TEXTURE_2D_MS: */
129 case PIPE_TEXTURE_2D
:
130 tic
[2] |= NV50_TIC_2_TARGET_2D
;
132 case PIPE_TEXTURE_RECT
:
133 tic
[2] |= NV50_TIC_2_TARGET_RECT
;
135 case PIPE_TEXTURE_3D
:
136 tic
[2] |= NV50_TIC_2_TARGET_3D
;
138 case PIPE_TEXTURE_CUBE
:
141 tic
[2] |= NV50_TIC_2_TARGET_CUBE_ARRAY
;
143 tic
[2] |= NV50_TIC_2_TARGET_CUBE
;
145 case PIPE_TEXTURE_1D_ARRAY
:
146 tic
[2] |= NV50_TIC_2_TARGET_1D_ARRAY
;
148 /* case PIPE_TEXTURE_2D_ARRAY_MS: */
149 case PIPE_TEXTURE_2D_ARRAY
:
150 tic
[2] |= NV50_TIC_2_TARGET_2D_ARRAY
;
153 tic
[2] |= NV50_TIC_2_TARGET_BUFFER
| NV50_TIC_2_LINEAR
;
156 NOUVEAU_ERR("invalid texture target: %d\n", mt
->base
.base
.target
);
160 if (mt
->base
.base
.target
== PIPE_BUFFER
)
161 tic
[3] = mt
->base
.base
.width0
;
165 tic
[4] = (1 << 31) | (mt
->base
.base
.width0
<< mt
->ms_x
);
167 tic
[5] = (mt
->base
.base
.height0
<< mt
->ms_y
) & 0xffff;
168 tic
[5] |= depth
<< 16;
169 tic
[5] |= mt
->base
.base
.last_level
<< 28;
171 tic
[6] = (mt
->ms_x
> 1) ? 0x88000000 : 0x03000000; /* sampling points */
173 tic
[7] = (view
->pipe
.u
.tex
.last_level
<< 4) | view
->pipe
.u
.tex
.first_level
;
176 if (mt->base.base.target == PIPE_TEXTURE_2D_MS ||
177 mt->base.base.target == PIPE_TEXTURE_2D_ARRAY_MS)
178 tic[7] |= mt->ms_mode << 12;
185 nvc0_validate_tic(struct nvc0_context
*nvc0
, int s
)
187 struct nouveau_channel
*chan
= nvc0
->screen
->base
.channel
;
188 struct nouveau_bo
*txc
= nvc0
->screen
->txc
;
190 boolean need_flush
= FALSE
;
192 for (i
= 0; i
< nvc0
->num_textures
[s
]; ++i
) {
193 struct nv50_tic_entry
*tic
= nv50_tic_entry(nvc0
->textures
[s
][i
]);
194 struct nv04_resource
*res
;
197 BEGIN_RING(chan
, RING_3D(BIND_TIC(s
)), 1);
198 OUT_RING (chan
, (i
<< 1) | 0);
201 res
= &nv50_miptree(tic
->pipe
.texture
)->base
;
204 uint32_t offset
= tic
->tic
[1];
206 tic
->id
= nvc0_screen_tic_alloc(nvc0
->screen
, tic
);
208 MARK_RING (chan
, 9 + 8, 4);
209 BEGIN_RING(chan
, RING_MF(OFFSET_OUT_HIGH
), 2);
210 OUT_RELOCh(chan
, txc
, tic
->id
* 32, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
211 OUT_RELOCl(chan
, txc
, tic
->id
* 32, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
212 BEGIN_RING(chan
, RING_MF(LINE_LENGTH_IN
), 2);
215 BEGIN_RING(chan
, RING_MF(EXEC
), 1);
216 OUT_RING (chan
, 0x100111);
217 BEGIN_RING_NI(chan
, RING_MF(DATA
), 8);
218 OUT_RING (chan
, tic
->tic
[0]);
219 OUT_RELOCl(chan
, res
->bo
, offset
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
220 OUT_RELOC (chan
, res
->bo
, offset
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
221 NOUVEAU_BO_HIGH
| NOUVEAU_BO_OR
, tic
->tic
[2], tic
->tic
[2]);
222 OUT_RINGp (chan
, &tic
->tic
[3], 5);
226 if (res
->status
& NOUVEAU_BUFFER_STATUS_GPU_WRITING
) {
227 BEGIN_RING(chan
, RING_3D(TEX_CACHE_CTL
), 1);
228 OUT_RING (chan
, (tic
->id
<< 4) | 1);
230 nvc0
->screen
->tic
.lock
[tic
->id
/ 32] |= 1 << (tic
->id
% 32);
232 res
->status
&= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING
;
233 res
->status
|= NOUVEAU_BUFFER_STATUS_GPU_READING
;
235 nvc0_bufctx_add_resident(nvc0
, NVC0_BUFCTX_TEXTURES
, res
,
236 NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
238 BEGIN_RING(chan
, RING_3D(BIND_TIC(s
)), 1);
239 OUT_RING (chan
, (tic
->id
<< 9) | (i
<< 1) | 1);
241 for (; i
< nvc0
->state
.num_textures
[s
]; ++i
) {
242 BEGIN_RING(chan
, RING_3D(BIND_TIC(s
)), 1);
243 OUT_RING (chan
, (i
<< 1) | 0);
245 nvc0
->state
.num_textures
[s
] = nvc0
->num_textures
[s
];
250 void nvc0_validate_textures(struct nvc0_context
*nvc0
)
254 need_flush
= nvc0_validate_tic(nvc0
, 0);
255 need_flush
|= nvc0_validate_tic(nvc0
, 4);
258 BEGIN_RING(nvc0
->screen
->base
.channel
, RING_3D(TIC_FLUSH
), 1);
259 OUT_RING (nvc0
->screen
->base
.channel
, 0);
264 nvc0_validate_tsc(struct nvc0_context
*nvc0
, int s
)
266 struct nouveau_channel
*chan
= nvc0
->screen
->base
.channel
;
268 boolean need_flush
= FALSE
;
270 for (i
= 0; i
< nvc0
->num_samplers
[s
]; ++i
) {
271 struct nv50_tsc_entry
*tsc
= nv50_tsc_entry(nvc0
->samplers
[s
][i
]);
274 BEGIN_RING(chan
, RING_3D(BIND_TSC(s
)), 1);
275 OUT_RING (chan
, (i
<< 4) | 0);
279 tsc
->id
= nvc0_screen_tsc_alloc(nvc0
->screen
, tsc
);
281 nvc0_m2mf_push_linear(&nvc0
->base
, nvc0
->screen
->txc
,
282 65536 + tsc
->id
* 32, NOUVEAU_BO_VRAM
,
286 nvc0
->screen
->tsc
.lock
[tsc
->id
/ 32] |= 1 << (tsc
->id
% 32);
288 BEGIN_RING(chan
, RING_3D(BIND_TSC(s
)), 1);
289 OUT_RING (chan
, (tsc
->id
<< 12) | (i
<< 4) | 1);
291 for (; i
< nvc0
->state
.num_samplers
[s
]; ++i
) {
292 BEGIN_RING(chan
, RING_3D(BIND_TSC(s
)), 1);
293 OUT_RING (chan
, (i
<< 4) | 0);
295 nvc0
->state
.num_samplers
[s
] = nvc0
->num_samplers
[s
];
300 void nvc0_validate_samplers(struct nvc0_context
*nvc0
)
304 need_flush
= nvc0_validate_tsc(nvc0
, 0);
305 need_flush
|= nvc0_validate_tsc(nvc0
, 4);
308 BEGIN_RING(nvc0
->screen
->base
.channel
, RING_3D(TSC_FLUSH
), 1);
309 OUT_RING (nvc0
->screen
->base
.channel
, 0);