src/gallium/drivers/nvc0/nvc0_tex.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "nvc0_context.h"
  24 #include "nvc0_resource.h"
  25 #include "nv50_texture.xml.h"
  26
  27 #include "util/u_format.h"
  28
  29 static INLINE uint32_t
  30 nv50_tic_swizzle(uint32_t tc, unsigned swz)
  31 {
  32    switch (swz) {
  33    case PIPE_SWIZZLE_RED:
  34       return (tc & NV50_TIC_0_MAPR__MASK) >> NV50_TIC_0_MAPR__SHIFT;
  35    case PIPE_SWIZZLE_GREEN:
  36       return (tc & NV50_TIC_0_MAPG__MASK) >> NV50_TIC_0_MAPG__SHIFT;
  37    case PIPE_SWIZZLE_BLUE:
  38       return (tc & NV50_TIC_0_MAPB__MASK) >> NV50_TIC_0_MAPB__SHIFT;
  39    case PIPE_SWIZZLE_ALPHA:
  40       return (tc & NV50_TIC_0_MAPA__MASK) >> NV50_TIC_0_MAPA__SHIFT;
  41    case PIPE_SWIZZLE_ONE:
  42       return NV50_TIC_MAP_ONE;
  43    case PIPE_SWIZZLE_ZERO:
  44    default:
  45       return NV50_TIC_MAP_ZERO;
  46    }
  47 }
  48
  49 struct pipe_sampler_view *
  50 nvc0_create_sampler_view(struct pipe_context *pipe,
  51                          struct pipe_resource *texture,
  52                          const struct pipe_sampler_view *templ)
  53 {
  54    const struct util_format_description *desc;
  55    uint32_t *tic;
  56    uint32_t swz[4];
  57    struct nvc0_tic_entry *view;
  58    struct nvc0_miptree *mt = nvc0_miptree(texture);
  59
  60    view = MALLOC_STRUCT(nvc0_tic_entry);
  61    if (!view)
  62       return NULL;
  63
  64    view->pipe = *templ;
  65    view->pipe.reference.count = 1;
  66    view->pipe.texture = NULL;
  67    view->pipe.context = pipe;
  68
  69    view->id = -1;
  70
  71    pipe_resource_reference(&view->pipe.texture, texture);
  72
  73    tic = &view->tic[0];
  74
  75    desc = util_format_description(mt->base.base.format);
  76
  77    /* TIC[0] */
  78
  79    tic[0] = nvc0_format_table[view->pipe.format].tic;
  80
  81    swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r);
  82    swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g);
  83    swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b);
  84    swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a);
  85    tic[0] = (tic[0] & ~NV50_TIC_0_SWIZZLE__MASK) |
  86       (swz[0] << NV50_TIC_0_MAPR__SHIFT) |
  87       (swz[1] << NV50_TIC_0_MAPG__SHIFT) |
  88       (swz[2] << NV50_TIC_0_MAPB__SHIFT) |
  89       (swz[3] << NV50_TIC_0_MAPA__SHIFT);
  90
  91    tic[1] = nouveau_bo_gpu_address(mt->base.bo);
  92    tic[2] = nouveau_bo_gpu_address(mt->base.bo) >> 32;
  93
  94    tic[2] |= 0x10001000 | /* NV50_TIC_2_NO_BORDER */ 0x40000000;
  95
  96    if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
  97       tic[2] |= NV50_TIC_2_COLORSPACE_SRGB;
  98
  99    if (mt->base.base.target != PIPE_TEXTURE_RECT)
 100       tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
 101
 102    tic[2] |=
 103       ((mt->base.bo->tile_mode & 0x0f0) << (22 - 4)) |
 104       ((mt->base.bo->tile_mode & 0xf00) << (21 - 4));
 105
 106    switch (mt->base.base.target) {
 107    case PIPE_TEXTURE_1D:
 108       tic[2] |= NV50_TIC_2_TARGET_1D;
 109       break;
 110    case PIPE_TEXTURE_2D:
 111       tic[2] |= NV50_TIC_2_TARGET_2D;
 112       break;
 113    case PIPE_TEXTURE_RECT:
 114       tic[2] |= NV50_TIC_2_TARGET_RECT;
 115       break;
 116    case PIPE_TEXTURE_3D:
 117       tic[2] |= NV50_TIC_2_TARGET_3D;
 118       break;
 119    case PIPE_TEXTURE_CUBE:
 120       tic[2] |= NV50_TIC_2_TARGET_CUBE;
 121       break;
 122    case PIPE_BUFFER:
 123       tic[2] |= NV50_TIC_2_TARGET_BUFFER | /* NV50_TIC_2_LINEAR */ (1 << 18);
 124    default:
 125       NOUVEAU_ERR("invalid texture target: %d\n", mt->base.base.target);
 126       return FALSE;
 127    }
 128
 129    if (mt->base.base.target == PIPE_BUFFER)
 130       tic[3] = mt->base.base.width0;
 131    else
 132       tic[3] = 0x00300000;
 133
 134    tic[4] = (1 << 31) | mt->base.base.width0;
 135
 136    tic[5] = mt->base.base.height0 & 0xffff;
 137    tic[5] |= mt->base.base.depth0 << 16;
 138    tic[5] |= mt->base.base.last_level << 28;
 139
 140    tic[6] = 0x03000000;
 141
 142    tic[7] = (view->pipe.last_level << 4) | view->pipe.first_level;
 143
 144    return &view->pipe;
 145 }
 146
 147 static boolean
 148 nvc0_validate_tic(struct nvc0_context *nvc0, int s)
 149 {
 150    struct nouveau_channel *chan = nvc0->screen->base.channel;
 151    unsigned i;
 152    boolean need_flush = FALSE;
 153
 154    for (i = 0; i < nvc0->num_textures[s]; ++i) {
 155       struct nvc0_tic_entry *tic = nvc0_tic_entry(nvc0->textures[s][i]);
 156       struct nvc0_resource *res;
 157
 158       if (!tic) {
 159          BEGIN_RING(chan, RING_3D(BIND_TIC(s)), 1);
 160          OUT_RING  (chan, (i << 1) | 0);
 161          continue;
 162       }
 163       res = &nvc0_miptree(tic->pipe.texture)->base;
 164
 165       if (tic->id < 0) {
 166          tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
 167
 168          nvc0_m2mf_push_linear(nvc0, nvc0->screen->txc, NOUVEAU_BO_VRAM,
 169                                tic->id * 32, 32, tic->tic);
 170          need_flush = TRUE;
 171       }
 172       nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
 173
 174       nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_TEXTURES, res,
 175                                NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 176
 177       BEGIN_RING(chan, RING_3D(BIND_TIC(s)), 1);
 178       OUT_RING  (chan, (tic->id << 9) | (i << 1) | 1);
 179    }
 180    for (; i < nvc0->state.num_textures[s]; ++i) {
 181       BEGIN_RING(chan, RING_3D(BIND_TIC(s)), 1);
 182       OUT_RING  (chan, (i << 1) | 0);
 183    }
 184    nvc0->state.num_textures[s] = nvc0->num_textures[s];
 185
 186    return need_flush;
 187 }
 188
 189 void nvc0_validate_textures(struct nvc0_context *nvc0)
 190 {
 191    boolean need_flush;
 192
 193    nvc0_bufctx_reset(nvc0, NVC0_BUFCTX_TEXTURES);
 194
 195    need_flush  = nvc0_validate_tic(nvc0, 0);
 196    need_flush |= nvc0_validate_tic(nvc0, 4);
 197
 198    if (need_flush) {
 199       BEGIN_RING(nvc0->screen->base.channel, RING_3D(TIC_FLUSH), 1);
 200       OUT_RING  (nvc0->screen->base.channel, 0);
 201    }
 202 }
 203
 204 static boolean
 205 nvc0_validate_tsc(struct nvc0_context *nvc0, int s)
 206 {
 207    struct nouveau_channel *chan = nvc0->screen->base.channel;
 208    unsigned i;
 209    boolean need_flush = FALSE;
 210
 211    for (i = 0; i < nvc0->num_samplers[s]; ++i) {
 212       struct nvc0_tsc_entry *tsc = nvc0_tsc_entry(nvc0->samplers[s][i]);
 213
 214       if (!tsc) {
 215          BEGIN_RING(chan, RING_3D(BIND_TSC(s)), 1);
 216          OUT_RING  (chan, (i << 4) | 0);
 217          continue;
 218       }
 219       if (tsc->id < 0) {
 220          tsc->id = nvc0_screen_tsc_alloc(nvc0->screen, tsc);
 221
 222          nvc0_m2mf_push_linear(nvc0, nvc0->screen->txc, NOUVEAU_BO_VRAM,
 223                                65536 + tsc->id * 32, 32, tsc->tsc);
 224          need_flush = TRUE;
 225       }
 226       nvc0->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
 227
 228       BEGIN_RING(chan, RING_3D(BIND_TSC(s)), 1);
 229       OUT_RING  (chan, (tsc->id << 12) | (i << 4) | 1);
 230    }
 231    for (; i < nvc0->state.num_samplers[s]; ++i) {
 232       BEGIN_RING(chan, RING_3D(BIND_TSC(s)), 1);
 233       OUT_RING  (chan, (i << 4) | 0);
 234    }
 235    nvc0->state.num_samplers[s] = nvc0->num_samplers[s];
 236
 237    return need_flush;
 238 }
 239
 240 void nvc0_validate_samplers(struct nvc0_context *nvc0)
 241 {
 242    boolean need_flush;
 243
 244    need_flush  = nvc0_validate_tsc(nvc0, 0);
 245    need_flush |= nvc0_validate_tsc(nvc0, 4);
 246
 247    if (need_flush) {
 248       BEGIN_RING(nvc0->screen->base.channel, RING_3D(TSC_FLUSH), 1);
 249       OUT_RING  (nvc0->screen->base.channel, 0);
 250    }
 251 }