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3e95d509f99617e59ba8ce934eb37ae8a1f064a9
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_vbo.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
27 #include "translate/translate.h"
28
29 #include "nvc0_context.h"
30 #include "nvc0_resource.h"
31
32 #include "nvc0_3d.xml.h"
33
34 void
35 nvc0_vertex_state_delete(struct pipe_context *pipe,
36 void *hwcso)
37 {
38 struct nvc0_vertex_stateobj *so = hwcso;
39
40 if (so->translate)
41 so->translate->release(so->translate);
42 FREE(hwcso);
43 }
44
45 void *
46 nvc0_vertex_state_create(struct pipe_context *pipe,
47 unsigned num_elements,
48 const struct pipe_vertex_element *elements)
49 {
50 struct nvc0_vertex_stateobj *so;
51 struct translate_key transkey;
52 unsigned i;
53
54 so = MALLOC(sizeof(*so) +
55 num_elements * sizeof(struct nvc0_vertex_element));
56 if (!so)
57 return NULL;
58 so->num_elements = num_elements;
59 so->instance_elts = 0;
60 so->instance_bufs = 0;
61 so->need_conversion = FALSE;
62
63 transkey.nr_elements = 0;
64 transkey.output_stride = 0;
65
66 for (i = 0; i < num_elements; ++i) {
67 const struct pipe_vertex_element *ve = &elements[i];
68 const unsigned vbi = ve->vertex_buffer_index;
69 enum pipe_format fmt = ve->src_format;
70
71 so->element[i].pipe = elements[i];
72 so->element[i].state = nvc0_format_table[fmt].vtx;
73
74 if (!so->element[i].state) {
75 switch (util_format_get_nr_components(fmt)) {
76 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
77 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
78 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
79 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
80 default:
81 assert(0);
82 return NULL;
83 }
84 so->element[i].state = nvc0_format_table[fmt].vtx;
85 so->need_conversion = TRUE;
86 }
87 so->element[i].state |= i;
88
89 if (1) {
90 unsigned j = transkey.nr_elements++;
91
92 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
93 transkey.element[j].input_format = ve->src_format;
94 transkey.element[j].input_buffer = vbi;
95 transkey.element[j].input_offset = ve->src_offset;
96 transkey.element[j].instance_divisor = ve->instance_divisor;
97
98 transkey.element[j].output_format = fmt;
99 transkey.element[j].output_offset = transkey.output_stride;
100 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
101
102 if (unlikely(ve->instance_divisor)) {
103 so->instance_elts |= 1 << i;
104 so->instance_bufs |= 1 << vbi;
105 }
106 }
107 }
108
109 so->translate = translate_create(&transkey);
110 so->vtx_size = transkey.output_stride / 4;
111 so->vtx_per_packet_max = NV04_PFIFO_MAX_PACKET_LEN / MAX2(so->vtx_size, 1);
112
113 return so;
114 }
115
116 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE \
117 NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT | \
118 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
119
120 #define VTX_ATTR(a, c, t, s) \
121 ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) | \
122 (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) | \
123 ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) | \
124 ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
125
126 static void
127 nvc0_emit_vtxattr(struct nvc0_context *nvc0, struct pipe_vertex_buffer *vb,
128 struct pipe_vertex_element *ve, unsigned attr)
129 {
130 const void *data;
131 struct nouveau_channel *chan = nvc0->screen->base.channel;
132 struct nv04_resource *res = nv04_resource(vb->buffer);
133 float v[4];
134 int i;
135 const unsigned nc = util_format_get_nr_components(ve->src_format);
136
137 data = nouveau_resource_map_offset(&nvc0->base, res, vb->buffer_offset +
138 ve->src_offset, NOUVEAU_BO_RD);
139
140 util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
141
142 BEGIN_RING(chan, RING_3D(VTX_ATTR_DEFINE), nc + 1);
143 OUT_RING (chan, VTX_ATTR(attr, nc, FLOAT, 32));
144 for (i = 0; i < nc; ++i)
145 OUT_RINGf(chan, v[i]);
146 }
147
148 static INLINE void
149 nvc0_vbuf_range(struct nvc0_context *nvc0, int vbi,
150 uint32_t *base, uint32_t *size)
151 {
152 if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
153 /* TODO: use min and max instance divisor to get a proper range */
154 *base = 0;
155 *size = nvc0->vtxbuf[vbi].buffer->width0;
156 } else {
157 assert(nvc0->vbo_max_index != ~0);
158 *base = nvc0->vbo_min_index * nvc0->vtxbuf[vbi].stride;
159 *size = (nvc0->vbo_max_index -
160 nvc0->vbo_min_index + 1) * nvc0->vtxbuf[vbi].stride;
161 }
162 }
163
164 static void
165 nvc0_prevalidate_vbufs(struct nvc0_context *nvc0)
166 {
167 struct pipe_vertex_buffer *vb;
168 struct nv04_resource *buf;
169 int i;
170 uint32_t base, size;
171
172 nvc0->vbo_fifo = nvc0->vbo_user = 0;
173
174 nvc0_bufctx_reset(nvc0, NVC0_BUFCTX_VERTEX);
175
176 for (i = 0; i < nvc0->num_vtxbufs; ++i) {
177 vb = &nvc0->vtxbuf[i];
178 if (!vb->stride)
179 continue;
180 buf = nv04_resource(vb->buffer);
181
182 /* NOTE: user buffers with temporary storage count as mapped by GPU */
183 if (!nouveau_resource_mapped_by_gpu(vb->buffer)) {
184 if (nvc0->vbo_push_hint) {
185 nvc0->vbo_fifo = ~0;
186 continue;
187 } else {
188 if (buf->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY) {
189 nvc0->vbo_user |= 1 << i;
190 assert(vb->stride > vb->buffer_offset);
191 nvc0_vbuf_range(nvc0, i, &base, &size);
192 nouveau_user_buffer_upload(buf, base, size);
193 } else {
194 nouveau_buffer_migrate(&nvc0->base, buf, NOUVEAU_BO_GART);
195 }
196 nvc0->base.vbo_dirty = TRUE;
197 }
198 }
199 nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_VERTEX, buf, NOUVEAU_BO_RD);
200 nouveau_buffer_adjust_score(&nvc0->base, buf, 1);
201 }
202 }
203
204 static void
205 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
206 {
207 struct nouveau_channel *chan = nvc0->screen->base.channel;
208 uint32_t base, offset, size;
209 int i;
210 uint32_t written = 0;
211
212 for (i = 0; i < nvc0->vertex->num_elements; ++i) {
213 struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
214 const int b = ve->vertex_buffer_index;
215 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
216 struct nv04_resource *buf = nv04_resource(vb->buffer);
217
218 if (!(nvc0->vbo_user & (1 << b)))
219 continue;
220
221 if (!vb->stride) {
222 nvc0_emit_vtxattr(nvc0, vb, ve, i);
223 continue;
224 }
225 nvc0_vbuf_range(nvc0, b, &base, &size);
226
227 if (!(written & (1 << b))) {
228 written |= 1 << b;
229 nouveau_user_buffer_upload(buf, base, size);
230 }
231 offset = vb->buffer_offset + ve->src_offset;
232
233 MARK_RING (chan, 6, 4);
234 BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
235 OUT_RING (chan, i);
236 OUT_RESRCh(chan, buf, base + size - 1, NOUVEAU_BO_RD);
237 OUT_RESRCl(chan, buf, base + size - 1, NOUVEAU_BO_RD);
238 OUT_RESRCh(chan, buf, offset, NOUVEAU_BO_RD);
239 OUT_RESRCl(chan, buf, offset, NOUVEAU_BO_RD);
240 }
241 nvc0->base.vbo_dirty = TRUE;
242 }
243
244 static INLINE void
245 nvc0_release_user_vbufs(struct nvc0_context *nvc0)
246 {
247 uint32_t vbo_user = nvc0->vbo_user;
248
249 while (vbo_user) {
250 int i = ffs(vbo_user) - 1;
251 vbo_user &= ~(1 << i);
252
253 nouveau_buffer_release_gpu_storage(nv04_resource(nvc0->vtxbuf[i].buffer));
254 }
255 }
256
257 void
258 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
259 {
260 struct nouveau_channel *chan = nvc0->screen->base.channel;
261 struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
262 struct pipe_vertex_buffer *vb;
263 struct nvc0_vertex_element *ve;
264 unsigned i;
265
266 if (unlikely(vertex->need_conversion) ||
267 unlikely(nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS)) {
268 nvc0->vbo_fifo = ~0;
269 nvc0->vbo_user = 0;
270 } else {
271 nvc0_prevalidate_vbufs(nvc0);
272 }
273
274 BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(0)), vertex->num_elements);
275 for (i = 0; i < vertex->num_elements; ++i) {
276 ve = &vertex->element[i];
277 vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
278
279 if (likely(vb->stride) || nvc0->vbo_fifo) {
280 OUT_RING(chan, ve->state);
281 } else {
282 OUT_RING(chan, ve->state | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
283 nvc0->vbo_fifo &= ~(1 << i);
284 }
285 }
286
287 for (i = 0; i < vertex->num_elements; ++i) {
288 struct nv04_resource *res;
289 unsigned size, offset;
290
291 ve = &vertex->element[i];
292 vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
293
294 if (unlikely(ve->pipe.instance_divisor)) {
295 if (!(nvc0->state.instance_elts & (1 << i))) {
296 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
297 }
298 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
299 OUT_RING (chan, ve->pipe.instance_divisor);
300 } else
301 if (unlikely(nvc0->state.instance_elts & (1 << i))) {
302 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 0);
303 }
304
305 res = nv04_resource(vb->buffer);
306
307 if (nvc0->vbo_fifo || unlikely(vb->stride == 0)) {
308 if (!nvc0->vbo_fifo)
309 nvc0_emit_vtxattr(nvc0, vb, &ve->pipe, i);
310 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
311 OUT_RING (chan, 0);
312 continue;
313 }
314
315 size = vb->buffer->width0;
316 offset = ve->pipe.src_offset + vb->buffer_offset;
317
318 MARK_RING (chan, 8, 4);
319 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
320 OUT_RING (chan, (1 << 12) | vb->stride);
321 BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
322 OUT_RING (chan, i);
323 OUT_RESRCh(chan, res, size - 1, NOUVEAU_BO_RD);
324 OUT_RESRCl(chan, res, size - 1, NOUVEAU_BO_RD);
325 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
326 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
327 }
328 for (; i < nvc0->state.num_vtxelts; ++i) {
329 BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(i)), 1);
330 OUT_RING (chan, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
331 if (unlikely(nvc0->state.instance_elts & (1 << i)))
332 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 0);
333 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
334 OUT_RING (chan, 0);
335 }
336
337 nvc0->state.num_vtxelts = vertex->num_elements;
338 nvc0->state.instance_elts = vertex->instance_elts;
339 }
340
341 #define NVC0_PRIM_GL_CASE(n) \
342 case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
343
344 static INLINE unsigned
345 nvc0_prim_gl(unsigned prim)
346 {
347 switch (prim) {
348 NVC0_PRIM_GL_CASE(POINTS);
349 NVC0_PRIM_GL_CASE(LINES);
350 NVC0_PRIM_GL_CASE(LINE_LOOP);
351 NVC0_PRIM_GL_CASE(LINE_STRIP);
352 NVC0_PRIM_GL_CASE(TRIANGLES);
353 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
354 NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
355 NVC0_PRIM_GL_CASE(QUADS);
356 NVC0_PRIM_GL_CASE(QUAD_STRIP);
357 NVC0_PRIM_GL_CASE(POLYGON);
358 NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
359 NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
360 NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
361 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
362 /*
363 NVC0_PRIM_GL_CASE(PATCHES); */
364 default:
365 return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
366 break;
367 }
368 }
369
370 static void
371 nvc0_draw_vbo_flush_notify(struct nouveau_channel *chan)
372 {
373 struct nvc0_screen *screen = chan->user_private;
374
375 nouveau_fence_update(&screen->base, TRUE);
376
377 nvc0_bufctx_emit_relocs(screen->cur_ctx);
378 }
379
380 static void
381 nvc0_draw_arrays(struct nvc0_context *nvc0,
382 unsigned mode, unsigned start, unsigned count,
383 unsigned instance_count)
384 {
385 struct nouveau_channel *chan = nvc0->screen->base.channel;
386 unsigned prim;
387
388 if (nvc0->state.index_bias) {
389 IMMED_RING(chan, RING_3D(VB_ELEMENT_BASE), 0);
390 nvc0->state.index_bias = 0;
391 }
392
393 prim = nvc0_prim_gl(mode);
394
395 while (instance_count--) {
396 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
397 OUT_RING (chan, prim);
398 BEGIN_RING(chan, RING_3D(VERTEX_BUFFER_FIRST), 2);
399 OUT_RING (chan, start);
400 OUT_RING (chan, count);
401 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
402
403 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
404 }
405 }
406
407 static void
408 nvc0_draw_elements_inline_u08(struct nouveau_channel *chan, uint8_t *map,
409 unsigned start, unsigned count)
410 {
411 map += start;
412
413 if (count & 3) {
414 unsigned i;
415 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), count & 3);
416 for (i = 0; i < (count & 3); ++i)
417 OUT_RING(chan, *map++);
418 count &= ~3;
419 }
420 while (count) {
421 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
422
423 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U8), nr);
424 for (i = 0; i < nr; ++i) {
425 OUT_RING(chan,
426 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
427 map += 4;
428 }
429 count -= nr * 4;
430 }
431 }
432
433 static void
434 nvc0_draw_elements_inline_u16(struct nouveau_channel *chan, uint16_t *map,
435 unsigned start, unsigned count)
436 {
437 map += start;
438
439 if (count & 1) {
440 count &= ~1;
441 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
442 OUT_RING (chan, *map++);
443 }
444 while (count) {
445 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
446
447 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
448 for (i = 0; i < nr; ++i) {
449 OUT_RING(chan, (map[1] << 16) | map[0]);
450 map += 2;
451 }
452 count -= nr * 2;
453 }
454 }
455
456 static void
457 nvc0_draw_elements_inline_u32(struct nouveau_channel *chan, uint32_t *map,
458 unsigned start, unsigned count)
459 {
460 map += start;
461
462 while (count) {
463 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
464
465 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), nr);
466 OUT_RINGp (chan, map, nr);
467
468 map += nr;
469 count -= nr;
470 }
471 }
472
473 static void
474 nvc0_draw_elements_inline_u32_short(struct nouveau_channel *chan, uint32_t *map,
475 unsigned start, unsigned count)
476 {
477 map += start;
478
479 if (count & 1) {
480 count--;
481 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
482 OUT_RING (chan, *map++);
483 }
484 while (count) {
485 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
486
487 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
488 for (i = 0; i < nr; ++i) {
489 OUT_RING(chan, (map[1] << 16) | map[0]);
490 map += 2;
491 }
492 count -= nr * 2;
493 }
494 }
495
496 static void
497 nvc0_draw_elements(struct nvc0_context *nvc0, boolean shorten,
498 unsigned mode, unsigned start, unsigned count,
499 unsigned instance_count, int32_t index_bias)
500 {
501 struct nouveau_channel *chan = nvc0->screen->base.channel;
502 void *data;
503 unsigned prim;
504 const unsigned index_size = nvc0->idxbuf.index_size;
505
506 prim = nvc0_prim_gl(mode);
507
508 if (index_bias != nvc0->state.index_bias) {
509 BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
510 OUT_RING (chan, index_bias);
511 nvc0->state.index_bias = index_bias;
512 }
513
514 if (nouveau_resource_mapped_by_gpu(nvc0->idxbuf.buffer)) {
515 struct nv04_resource *res = nv04_resource(nvc0->idxbuf.buffer);
516 unsigned offset = nvc0->idxbuf.offset;
517 unsigned limit = nvc0->idxbuf.buffer->width0 - 1;
518
519 nouveau_buffer_adjust_score(&nvc0->base, res, 1);
520
521 while (instance_count--) {
522 MARK_RING (chan, 11, 4);
523 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
524 OUT_RING (chan, mode);
525 BEGIN_RING(chan, RING_3D(INDEX_ARRAY_START_HIGH), 7);
526 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
527 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
528 OUT_RESRCh(chan, res, limit, NOUVEAU_BO_RD);
529 OUT_RESRCl(chan, res, limit, NOUVEAU_BO_RD);
530 OUT_RING (chan, index_size >> 1);
531 OUT_RING (chan, start);
532 OUT_RING (chan, count);
533 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
534
535 nvc0_resource_fence(res, NOUVEAU_BO_RD);
536
537 mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
538 }
539 } else {
540 data = nouveau_resource_map_offset(&nvc0->base,
541 nv04_resource(nvc0->idxbuf.buffer),
542 nvc0->idxbuf.offset, NOUVEAU_BO_RD);
543 if (!data)
544 return;
545
546 while (instance_count--) {
547 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
548 OUT_RING (chan, prim);
549 switch (index_size) {
550 case 1:
551 nvc0_draw_elements_inline_u08(chan, data, start, count);
552 break;
553 case 2:
554 nvc0_draw_elements_inline_u16(chan, data, start, count);
555 break;
556 case 4:
557 if (shorten)
558 nvc0_draw_elements_inline_u32_short(chan, data, start, count);
559 else
560 nvc0_draw_elements_inline_u32(chan, data, start, count);
561 break;
562 default:
563 assert(0);
564 return;
565 }
566 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
567
568 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
569 }
570 }
571 }
572
573 static void
574 nvc0_draw_stream_output(struct nvc0_context *nvc0,
575 const struct pipe_draw_info *info)
576 {
577 struct nouveau_channel *chan = nvc0->screen->base.channel;
578 struct nvc0_so_target *so = nvc0_so_target(info->count_from_stream_output);
579 struct nv04_resource *res = nv04_resource(so->pipe.buffer);
580 unsigned mode = nvc0_prim_gl(info->mode);
581 unsigned num_instances = info->instance_count;
582
583 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
584 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
585 IMMED_RING(chan, RING_3D(SERIALIZE), 0);
586 nvc0_query_fifo_wait(chan, so->pq);
587 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 0);
588 }
589
590 while (num_instances--) {
591 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
592 OUT_RING (chan, mode);
593 BEGIN_RING(chan, RING_3D(DRAW_TFB_BASE), 1);
594 OUT_RING (chan, 0);
595 BEGIN_RING(chan, RING_3D(DRAW_TFB_STRIDE), 1);
596 OUT_RING (chan, so->stride);
597 BEGIN_RING(chan, RING_3D(DRAW_TFB_BYTES), 1);
598 nvc0_query_pushbuf_submit(chan, so->pq, 0x4);
599 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
600
601 mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
602 }
603 }
604
605 void
606 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
607 {
608 struct nvc0_context *nvc0 = nvc0_context(pipe);
609 struct nouveau_channel *chan = nvc0->screen->base.channel;
610
611 /* For picking only a few vertices from a large user buffer, push is better,
612 * if index count is larger and we expect repeated vertices, suggest upload.
613 */
614 nvc0->vbo_push_hint = /* the 64 is heuristic */
615 !(info->indexed &&
616 ((info->max_index - info->min_index + 64) < info->count));
617
618 nvc0->vbo_min_index = info->min_index;
619 nvc0->vbo_max_index = info->max_index;
620
621 if (nvc0->vbo_push_hint != !!nvc0->vbo_fifo)
622 nvc0->dirty |= NVC0_NEW_ARRAYS;
623
624 if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS)))
625 nvc0_update_user_vbufs(nvc0);
626
627 /* 8 as minimum to avoid immediate double validation of new buffers */
628 nvc0_state_validate(nvc0, ~0, 8);
629
630 chan->flush_notify = nvc0_draw_vbo_flush_notify;
631
632 if (nvc0->vbo_fifo) {
633 nvc0_push_vbo(nvc0, info);
634 chan->flush_notify = nvc0_default_flush_notify;
635 return;
636 }
637
638 if (nvc0->state.instance_base != info->start_instance) {
639 nvc0->state.instance_base = info->start_instance;
640 /* NOTE: this does not affect the shader input, should it ? */
641 BEGIN_RING(chan, RING_3D(VB_INSTANCE_BASE), 1);
642 OUT_RING (chan, info->start_instance);
643 }
644
645 if (nvc0->base.vbo_dirty) {
646 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 1);
647 OUT_RING (chan, 0);
648 nvc0->base.vbo_dirty = FALSE;
649 }
650
651 if (unlikely(info->count_from_stream_output)) {
652 nvc0_draw_stream_output(nvc0, info);
653 } else
654 if (!info->indexed) {
655 nvc0_draw_arrays(nvc0,
656 info->mode, info->start, info->count,
657 info->instance_count);
658 } else {
659 boolean shorten = info->max_index <= 65535;
660
661 assert(nvc0->idxbuf.buffer);
662
663 if (info->primitive_restart != nvc0->state.prim_restart) {
664 if (info->primitive_restart) {
665 BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 2);
666 OUT_RING (chan, 1);
667 OUT_RING (chan, info->restart_index);
668
669 if (info->restart_index > 65535)
670 shorten = FALSE;
671 } else {
672 IMMED_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 0);
673 }
674 nvc0->state.prim_restart = info->primitive_restart;
675 } else
676 if (info->primitive_restart) {
677 BEGIN_RING(chan, RING_3D(PRIM_RESTART_INDEX), 1);
678 OUT_RING (chan, info->restart_index);
679
680 if (info->restart_index > 65535)
681 shorten = FALSE;
682 }
683
684 nvc0_draw_elements(nvc0, shorten,
685 info->mode, info->start, info->count,
686 info->instance_count, info->index_bias);
687 }
688 chan->flush_notify = nvc0_default_flush_notify;
689
690 nvc0_release_user_vbufs(nvc0);
691 }