src/gallium/drivers/nvc0/nvc0_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "pipe/p_context.h"
  24 #include "pipe/p_state.h"
  25 #include "util/u_inlines.h"
  26 #include "util/u_format.h"
  27 #include "translate/translate.h"
  28
  29 #include "nvc0_context.h"
  30 #include "nvc0_resource.h"
  31
  32 #include "nvc0_3d.xml.h"
  33
  34 void
  35 nvc0_vertex_state_delete(struct pipe_context *pipe,
  36                          void *hwcso)
  37 {
  38    struct nvc0_vertex_stateobj *so = hwcso;
  39
  40    if (so->translate)
  41       so->translate->release(so->translate);
  42    FREE(hwcso);
  43 }
  44
  45 void *
  46 nvc0_vertex_state_create(struct pipe_context *pipe,
  47                          unsigned num_elements,
  48                          const struct pipe_vertex_element *elements)
  49 {
  50     struct nvc0_vertex_stateobj *so;
  51     struct translate_key transkey;
  52     unsigned i;
  53
  54     assert(num_elements);
  55
  56     so = MALLOC(sizeof(*so) +
  57                 num_elements * sizeof(struct nvc0_vertex_element));
  58     if (!so)
  59         return NULL;
  60     so->num_elements = num_elements;
  61     so->instance_elts = 0;
  62     so->instance_bufs = 0;
  63
  64     transkey.nr_elements = 0;
  65     transkey.output_stride = 0;
  66
  67     for (i = 0; i < num_elements; ++i) {
  68         const struct pipe_vertex_element *ve = &elements[i];
  69         const unsigned vbi = ve->vertex_buffer_index;
  70         enum pipe_format fmt = ve->src_format;
  71
  72         so->element[i].pipe = elements[i];
  73         so->element[i].state = nvc0_format_table[fmt].vtx;
  74
  75         if (!so->element[i].state) {
  76             switch (util_format_get_nr_components(fmt)) {
  77             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  78             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  79             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  80             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  81             default:
  82                 assert(0);
  83                 return NULL;
  84             }
  85             so->element[i].state = nvc0_format_table[fmt].vtx;
  86         }
  87         so->element[i].state |= i;
  88
  89         if (1) {
  90             unsigned j = transkey.nr_elements++;
  91
  92             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
  93             transkey.element[j].input_format = ve->src_format;
  94             transkey.element[j].input_buffer = vbi;
  95             transkey.element[j].input_offset = ve->src_offset;
  96             transkey.element[j].instance_divisor = ve->instance_divisor;
  97
  98             transkey.element[j].output_format = fmt;
  99             transkey.element[j].output_offset = transkey.output_stride;
 100             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
 101
 102             if (unlikely(ve->instance_divisor)) {
 103                so->instance_elts |= 1 << i;
 104                so->instance_bufs |= 1 << vbi;
 105             }
 106         }
 107     }
 108
 109     so->translate = translate_create(&transkey);
 110     so->vtx_size = transkey.output_stride / 4;
 111     so->vtx_per_packet_max = NV04_PFIFO_MAX_PACKET_LEN / MAX2(so->vtx_size, 1);
 112
 113     return so;
 114 }
 115
 116 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE                                       \
 117    NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |                                 \
 118    NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
 119
 120 #define VTX_ATTR(a, c, t, s)                            \
 121    ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) |                \
 122     (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) |                \
 123     ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) |      \
 124     ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
 125
 126 static void
 127 nvc0_emit_vtxattr(struct nvc0_context *nvc0, struct pipe_vertex_buffer *vb,
 128                   struct pipe_vertex_element *ve, unsigned attr)
 129 {
 130    const void *data;
 131    struct nouveau_channel *chan = nvc0->screen->base.channel;
 132    struct nvc0_resource *res = nvc0_resource(vb->buffer);
 133    float v[4];
 134    int i;
 135    const unsigned nc = util_format_get_nr_components(ve->src_format);
 136
 137    data = nvc0_resource_map_offset(nvc0, res, vb->buffer_offset +
 138                                    ve->src_offset, NOUVEAU_BO_RD);
 139
 140    util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
 141
 142    BEGIN_RING(chan, RING_3D(VTX_ATTR_DEFINE), nc + 1);
 143    OUT_RING  (chan, VTX_ATTR(attr, nc, FLOAT, 32));
 144    for (i = 0; i < nc; ++i)
 145       OUT_RINGf(chan, v[i]);
 146 }
 147
 148 static INLINE void
 149 nvc0_vbuf_range(struct nvc0_context *nvc0, int vbi,
 150                 uint32_t *base, uint32_t *size)
 151 {
 152    if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
 153       /* TODO: use min and max instance divisor to get a proper range */
 154       *base = 0;
 155       *size = nvc0->vtxbuf[vbi].buffer->width0;
 156    } else {
 157       assert(nvc0->vbo_max_index != ~0);
 158       *base = nvc0->vbo_min_index * nvc0->vtxbuf[vbi].stride;
 159       *size = (nvc0->vbo_max_index -
 160                nvc0->vbo_min_index + 1) * nvc0->vtxbuf[vbi].stride;
 161    }
 162 }
 163
 164 static void
 165 nvc0_prevalidate_vbufs(struct nvc0_context *nvc0)
 166 {
 167    struct pipe_vertex_buffer *vb;
 168    struct nvc0_resource *buf;
 169    int i;
 170    uint32_t base, size;
 171
 172    nvc0->vbo_fifo = nvc0->vbo_user = 0;
 173
 174    for (i = 0; i < nvc0->num_vtxbufs; ++i) {
 175       vb = &nvc0->vtxbuf[i];
 176       if (!vb->stride)
 177          continue;
 178       buf = nvc0_resource(vb->buffer);
 179
 180       if (!nvc0_resource_mapped_by_gpu(vb->buffer)) {
 181          if (nvc0->vbo_push_hint) {
 182             nvc0->vbo_fifo = ~0;
 183             continue;
 184          } else {
 185             if (buf->status & NVC0_BUFFER_STATUS_USER_MEMORY) {
 186                nvc0->vbo_user |= 1 << i;
 187                assert(vb->stride > vb->buffer_offset);
 188                nvc0_vbuf_range(nvc0, i, &base, &size);
 189                nvc0_user_buffer_upload(buf, base, size);
 190             } else {
 191                nvc0_buffer_migrate(nvc0, buf, NOUVEAU_BO_GART);
 192             }
 193             nvc0->vbo_dirty = TRUE;
 194          }
 195       }
 196       nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_VERTEX, buf, NOUVEAU_BO_RD);
 197       nvc0_buffer_adjust_score(nvc0, buf, 1);
 198    }
 199 }
 200
 201 static void
 202 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
 203 {
 204    struct nouveau_channel *chan = nvc0->screen->base.channel;
 205    uint32_t base, offset, size;
 206    int i;
 207    uint32_t written = 0;
 208
 209    for (i = 0; i < nvc0->vertex->num_elements; ++i) {
 210       struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
 211       const int b = ve->vertex_buffer_index;
 212       struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
 213       struct nvc0_resource *buf = nvc0_resource(vb->buffer);
 214
 215       if (!(nvc0->vbo_user & (1 << b)))
 216          continue;
 217
 218       if (!vb->stride) {
 219          nvc0_emit_vtxattr(nvc0, vb, ve, i);
 220          continue;
 221       }
 222       nvc0_vbuf_range(nvc0, b, &base, &size);
 223
 224       if (!(written & (1 << b))) {
 225          written |= 1 << b;
 226          nvc0_user_buffer_upload(buf, base, size);
 227       }
 228       offset = vb->buffer_offset + ve->src_offset;
 229
 230       MARK_RING (chan, 6, 4);
 231       BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
 232       OUT_RING  (chan, i);
 233       OUT_RESRCh(chan, buf, size - 1, NOUVEAU_BO_RD);
 234       OUT_RESRCl(chan, buf, size - 1, NOUVEAU_BO_RD);
 235       OUT_RESRCh(chan, buf, offset, NOUVEAU_BO_RD);
 236       OUT_RESRCl(chan, buf, offset, NOUVEAU_BO_RD);
 237    }
 238    nvc0->vbo_dirty = TRUE;
 239 }
 240
 241 void
 242 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
 243 {
 244    struct nouveau_channel *chan = nvc0->screen->base.channel;
 245    struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
 246    struct pipe_vertex_buffer *vb;
 247    struct nvc0_vertex_element *ve;
 248    unsigned i;
 249
 250    nvc0_prevalidate_vbufs(nvc0);
 251
 252    BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(0)), vertex->num_elements);
 253    for (i = 0; i < vertex->num_elements; ++i) {
 254       ve = &vertex->element[i];
 255       vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
 256
 257       if (likely(vb->stride) || nvc0->vbo_fifo) {
 258          OUT_RING(chan, ve->state);
 259       } else {
 260          OUT_RING(chan, ve->state | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
 261          nvc0->vbo_fifo &= ~(1 << i);
 262       }
 263    }
 264
 265    for (i = 0; i < vertex->num_elements; ++i) {
 266       struct nvc0_resource *res;
 267       unsigned size, offset;
 268
 269       ve = &vertex->element[i];
 270       vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
 271
 272       if (unlikely(ve->pipe.instance_divisor)) {
 273          if (!(nvc0->state.instance_elts & (1 << i))) {
 274             IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 275          }
 276          BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
 277          OUT_RING  (chan, ve->pipe.instance_divisor);
 278       } else
 279       if (unlikely(nvc0->state.instance_elts & (1 << i))) {
 280          IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 0);
 281       }
 282
 283       res = nvc0_resource(vb->buffer);
 284
 285       if (nvc0->vbo_fifo || unlikely(vb->stride == 0)) {
 286          if (!nvc0->vbo_fifo)
 287             nvc0_emit_vtxattr(nvc0, vb, &ve->pipe, i);
 288          BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
 289          OUT_RING  (chan, 0);
 290          continue;
 291       }
 292
 293       size = vb->buffer->width0;
 294       offset = ve->pipe.src_offset + vb->buffer_offset;
 295
 296       MARK_RING (chan, 8, 4);
 297       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
 298       OUT_RING  (chan, (1 << 12) | vb->stride);
 299       BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
 300       OUT_RING  (chan, i);
 301       OUT_RESRCh(chan, res, size - 1, NOUVEAU_BO_RD);
 302       OUT_RESRCl(chan, res, size - 1, NOUVEAU_BO_RD);
 303       OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
 304       OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
 305    }
 306    for (; i < nvc0->state.num_vtxelts; ++i) {
 307       BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(i)), 1);
 308       OUT_RING  (chan, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
 309       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
 310       OUT_RING  (chan, 0);
 311    }
 312
 313    nvc0->state.num_vtxelts = vertex->num_elements;
 314    nvc0->state.instance_elts = vertex->instance_elts;
 315 }
 316
 317 #define NVC0_PRIM_GL_CASE(n) \
 318    case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 319
 320 static INLINE unsigned
 321 nvc0_prim_gl(unsigned prim)
 322 {
 323    switch (prim) {
 324    NVC0_PRIM_GL_CASE(POINTS);
 325    NVC0_PRIM_GL_CASE(LINES);
 326    NVC0_PRIM_GL_CASE(LINE_LOOP);
 327    NVC0_PRIM_GL_CASE(LINE_STRIP);
 328    NVC0_PRIM_GL_CASE(TRIANGLES);
 329    NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
 330    NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
 331    NVC0_PRIM_GL_CASE(QUADS);
 332    NVC0_PRIM_GL_CASE(QUAD_STRIP);
 333    NVC0_PRIM_GL_CASE(POLYGON);
 334    NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
 335    NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 336    NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 337    NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 338    /*
 339    NVC0_PRIM_GL_CASE(PATCHES); */
 340    default:
 341       return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 342       break;
 343    }
 344 }
 345
 346 static void
 347 nvc0_draw_vbo_flush_notify(struct nouveau_channel *chan)
 348 {
 349    struct nvc0_context *nvc0 = chan->user_private;
 350
 351    nvc0_bufctx_emit_relocs(nvc0);
 352 }
 353
 354 static void
 355 nvc0_draw_arrays(struct nvc0_context *nvc0,
 356                  unsigned mode, unsigned start, unsigned count,
 357                  unsigned instance_count)
 358 {
 359    struct nouveau_channel *chan = nvc0->screen->base.channel;
 360    unsigned prim;
 361
 362    chan->flush_notify = nvc0_draw_vbo_flush_notify;
 363    chan->user_private = nvc0;
 364
 365    prim = nvc0_prim_gl(mode);
 366
 367    while (instance_count--) {
 368       BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
 369       OUT_RING  (chan, prim);
 370       BEGIN_RING(chan, RING_3D(VERTEX_BUFFER_FIRST), 2);
 371       OUT_RING  (chan, start);
 372       OUT_RING  (chan, count);
 373       IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
 374
 375       prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 376    }
 377
 378    chan->flush_notify = NULL;
 379 }
 380
 381 static void
 382 nvc0_draw_elements_inline_u08(struct nouveau_channel *chan, uint8_t *map,
 383                               unsigned start, unsigned count)
 384 {
 385    map += start;
 386
 387    if (count & 3) {
 388       unsigned i;
 389       BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), count & 3);
 390       for (i = 0; i < (count & 3); ++i)
 391          OUT_RING(chan, *map++);
 392       count &= ~3;
 393    }
 394    while (count) {
 395       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 396
 397       BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U8), nr);
 398       for (i = 0; i < nr; ++i) {
 399          OUT_RING(chan,
 400                   (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 401          map += 4;
 402       }
 403       count -= nr * 4;
 404    }
 405 }
 406
 407 static void
 408 nvc0_draw_elements_inline_u16(struct nouveau_channel *chan, uint16_t *map,
 409                               unsigned start, unsigned count)
 410 {
 411    map += start;
 412
 413    if (count & 1) {
 414       count &= ~1;
 415       BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
 416       OUT_RING  (chan, *map++);
 417    }
 418    while (count) {
 419       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 420
 421       BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
 422       for (i = 0; i < nr; ++i) {
 423          OUT_RING(chan, (map[1] << 16) | map[0]);
 424          map += 2;
 425       }
 426       count -= nr * 2;
 427    }
 428 }
 429
 430 static void
 431 nvc0_draw_elements_inline_u32(struct nouveau_channel *chan, uint32_t *map,
 432                               unsigned start, unsigned count)
 433 {
 434    map += start;
 435
 436    while (count) {
 437       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 438
 439       BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), nr);
 440       OUT_RINGp    (chan, map, nr);
 441
 442       map += nr;
 443       count -= nr;
 444    }
 445 }
 446
 447 static void
 448 nvc0_draw_elements_inline_u32_short(struct nouveau_channel *chan, uint32_t *map,
 449                                     unsigned start, unsigned count)
 450 {
 451    map += start;
 452
 453    if (count & 1) {
 454       count--;
 455       BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
 456       OUT_RING  (chan, *map++);
 457    }
 458    while (count) {
 459       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 460
 461       BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
 462       for (i = 0; i < nr; ++i) {
 463          OUT_RING(chan, (map[1] << 16) | map[0]);
 464          map += 2;
 465       }
 466       count -= nr * 2;
 467    }
 468 }
 469
 470 static void
 471 nvc0_draw_elements(struct nvc0_context *nvc0, boolean shorten,
 472                    unsigned mode, unsigned start, unsigned count,
 473                    unsigned instance_count, int32_t index_bias)
 474 {
 475    struct nouveau_channel *chan = nvc0->screen->base.channel;
 476    void *data;
 477    unsigned prim;
 478    const unsigned index_size = nvc0->idxbuf.index_size;
 479
 480    chan->flush_notify = nvc0_draw_vbo_flush_notify;
 481    chan->user_private = nvc0;
 482
 483    prim = nvc0_prim_gl(mode);
 484
 485    if (index_bias != nvc0->state.index_bias) {
 486       BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
 487       OUT_RING  (chan, index_bias);
 488       nvc0->state.index_bias = index_bias;
 489    }
 490
 491    if (nvc0_resource_mapped_by_gpu(nvc0->idxbuf.buffer)) {
 492       struct nvc0_resource *res = nvc0_resource(nvc0->idxbuf.buffer);
 493       unsigned offset = nvc0->idxbuf.offset;
 494       unsigned limit = nvc0->idxbuf.buffer->width0 - 1;
 495
 496       nvc0_buffer_adjust_score(nvc0, res, 1);
 497
 498       while (instance_count--) {
 499          MARK_RING (chan, 11, 4);
 500          BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
 501          OUT_RING  (chan, mode);
 502          BEGIN_RING(chan, RING_3D(INDEX_ARRAY_START_HIGH), 7);
 503          OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
 504          OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
 505          OUT_RESRCh(chan, res, limit, NOUVEAU_BO_RD);
 506          OUT_RESRCl(chan, res, limit, NOUVEAU_BO_RD);
 507          OUT_RING  (chan, index_size >> 1);
 508          OUT_RING  (chan, start);
 509          OUT_RING  (chan, count);
 510          IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
 511
 512          nvc0_resource_fence(res, NOUVEAU_BO_RD);
 513
 514          mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 515       }
 516    } else {
 517       data = nvc0_resource_map_offset(nvc0, nvc0_resource(nvc0->idxbuf.buffer),
 518                                       nvc0->idxbuf.offset, NOUVEAU_BO_RD);
 519       if (!data)
 520          return;
 521
 522       while (instance_count--) {
 523          BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
 524          OUT_RING  (chan, prim);
 525          switch (index_size) {
 526          case 1:
 527             nvc0_draw_elements_inline_u08(chan, data, start, count);
 528             break;
 529          case 2:
 530             nvc0_draw_elements_inline_u16(chan, data, start, count);
 531             break;
 532          case 4:
 533             if (shorten)
 534                nvc0_draw_elements_inline_u32_short(chan, data, start, count);
 535             else
 536                nvc0_draw_elements_inline_u32(chan, data, start, count);
 537             break;
 538          default:
 539             assert(0);
 540             return;
 541          }
 542          IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
 543
 544          prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 545       }
 546    }
 547
 548    chan->flush_notify = NULL;
 549 }
 550
 551 void
 552 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 553 {
 554    struct nvc0_context *nvc0 = nvc0_context(pipe);
 555    struct nouveau_channel *chan = nvc0->screen->base.channel;
 556
 557    /* For picking only a few vertices from a large user buffer, push is better,
 558     * if index count is larger and we expect repeated vertices, suggest upload.
 559     */
 560    nvc0->vbo_push_hint = /* the 64 is heuristic */
 561       !(info->indexed &&
 562         ((info->max_index - info->min_index + 64) < info->count));
 563
 564    nvc0->vbo_min_index = info->min_index;
 565    nvc0->vbo_max_index = info->max_index;
 566
 567    if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS)))
 568       nvc0_update_user_vbufs(nvc0);
 569
 570    nvc0_state_validate(nvc0);
 571
 572    if (nvc0->vbo_fifo) {
 573       nvc0_push_vbo(nvc0, info);
 574       return;
 575    }
 576
 577    if (nvc0->state.instance_base != info->start_instance) {
 578       nvc0->state.instance_base = info->start_instance;
 579       /* NOTE: this does not affect the shader input, should it ? */
 580       BEGIN_RING(chan, RING_3D(VB_INSTANCE_BASE), 1);
 581       OUT_RING  (chan, info->start_instance);
 582    }
 583
 584    if (nvc0->vbo_dirty) {
 585       BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 1);
 586       OUT_RING  (chan, 0);
 587       nvc0->vbo_dirty = FALSE;
 588    }
 589
 590    if (!info->indexed) {
 591       nvc0_draw_arrays(nvc0,
 592                        info->mode, info->start, info->count,
 593                        info->instance_count);
 594    } else {
 595       boolean shorten = info->max_index <= 65535;
 596
 597       assert(nvc0->idxbuf.buffer);
 598
 599       if (info->primitive_restart != nvc0->state.prim_restart) {
 600          if (info->primitive_restart) {
 601             BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 2);
 602             OUT_RING  (chan, 1);
 603             OUT_RING  (chan, info->restart_index);
 604
 605             if (info->restart_index > 65535)
 606                shorten = FALSE;
 607          } else {
 608             IMMED_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 0);
 609          }
 610          nvc0->state.prim_restart = info->primitive_restart;
 611       } else
 612       if (info->primitive_restart) {
 613          BEGIN_RING(chan, RING_3D(PRIM_RESTART_INDEX), 1);
 614          OUT_RING  (chan, info->restart_index);
 615
 616          if (info->restart_index > 65535)
 617             shorten = FALSE;
 618       }
 619
 620       nvc0_draw_elements(nvc0, shorten,
 621                          info->mode, info->start, info->count,
 622                          info->instance_count, info->index_bias);
 623    }
 624 }