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[mesa.git] / src / gallium / drivers / nvc0 / nvc0_vbo.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
27 #include "translate/translate.h"
28
29 #include "nvc0_context.h"
30 #include "nvc0_resource.h"
31
32 #include "nvc0_3d.xml.h"
33
34 void
35 nvc0_vertex_state_delete(struct pipe_context *pipe,
36 void *hwcso)
37 {
38 struct nvc0_vertex_stateobj *so = hwcso;
39
40 if (so->translate)
41 so->translate->release(so->translate);
42 FREE(hwcso);
43 }
44
45 void *
46 nvc0_vertex_state_create(struct pipe_context *pipe,
47 unsigned num_elements,
48 const struct pipe_vertex_element *elements)
49 {
50 struct nvc0_vertex_stateobj *so;
51 struct translate_key transkey;
52 unsigned i;
53
54 assert(num_elements);
55
56 so = MALLOC(sizeof(*so) +
57 (num_elements - 1) * sizeof(struct nvc0_vertex_element));
58 if (!so)
59 return NULL;
60 so->num_elements = num_elements;
61 so->instance_bits = 0;
62
63 transkey.nr_elements = 0;
64 transkey.output_stride = 0;
65
66 for (i = 0; i < num_elements; ++i) {
67 const struct pipe_vertex_element *ve = &elements[i];
68 const unsigned vbi = ve->vertex_buffer_index;
69 enum pipe_format fmt = ve->src_format;
70
71 so->element[i].pipe = elements[i];
72 so->element[i].state = nvc0_format_table[fmt].vtx;
73
74 if (!so->element[i].state) {
75 switch (util_format_get_nr_components(fmt)) {
76 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
77 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
78 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
79 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
80 default:
81 assert(0);
82 return NULL;
83 }
84 so->element[i].state = nvc0_format_table[fmt].vtx;
85 }
86 so->element[i].state |= i;
87
88 if (likely(!ve->instance_divisor)) {
89 unsigned j = transkey.nr_elements++;
90
91 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
92 transkey.element[j].input_format = ve->src_format;
93 transkey.element[j].input_buffer = vbi;
94 transkey.element[j].input_offset = ve->src_offset;
95 transkey.element[j].instance_divisor = ve->instance_divisor;
96
97 transkey.element[j].output_format = fmt;
98 transkey.element[j].output_offset = transkey.output_stride;
99 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
100 } else {
101 so->instance_bits |= 1 << i;
102 }
103 }
104
105 so->translate = translate_create(&transkey);
106 so->vtx_size = transkey.output_stride / 4;
107 so->vtx_per_packet_max = NV04_PFIFO_MAX_PACKET_LEN / MAX2(so->vtx_size, 1);
108
109 return so;
110 }
111
112 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE \
113 NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT | \
114 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
115
116 #define VTX_ATTR(a, c, t, s) \
117 ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) | \
118 (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) | \
119 ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) | \
120 ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
121
122 static void
123 nvc0_emit_vtxattr(struct nvc0_context *nvc0, struct pipe_vertex_buffer *vb,
124 struct pipe_vertex_element *ve, unsigned attr)
125 {
126 const void *data;
127 struct nouveau_channel *chan = nvc0->screen->base.channel;
128 struct nvc0_resource *res = nvc0_resource(vb->buffer);
129 float v[4];
130 int i;
131 const unsigned nc = util_format_get_nr_components(ve->src_format);
132
133 data = nvc0_resource_map_offset(nvc0, res, vb->buffer_offset +
134 ve->src_offset, NOUVEAU_BO_RD);
135
136 util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
137
138 BEGIN_RING(chan, RING_3D(VTX_ATTR_DEFINE), nc + 1);
139 OUT_RING (chan, VTX_ATTR(attr, nc, FLOAT, 32));
140 for (i = 0; i < nc; ++i)
141 OUT_RINGf(chan, v[i]);
142 }
143
144 static void
145 nvc0_prevalidate_vbufs(struct nvc0_context *nvc0)
146 {
147 struct pipe_vertex_buffer *vb;
148 struct nvc0_resource *buf;
149 int i;
150 uint32_t base, size;
151
152 nvc0->vbo_fifo = nvc0->vbo_user = 0;
153
154 for (i = 0; i < nvc0->num_vtxbufs; ++i) {
155 vb = &nvc0->vtxbuf[i];
156 if (!vb->stride)
157 continue;
158 buf = nvc0_resource(vb->buffer);
159
160 if (!nvc0_resource_mapped_by_gpu(vb->buffer)) {
161 if (nvc0->vbo_push_hint) {
162 nvc0->vbo_fifo = ~0;
163 continue;
164 } else {
165 if (buf->status & NVC0_BUFFER_STATUS_USER_MEMORY) {
166 nvc0->vbo_user |= 1 << i;
167 assert(vb->stride > vb->buffer_offset);
168 size = vb->stride * (nvc0->vbo_max_index -
169 nvc0->vbo_min_index + 1);
170 base = vb->stride * nvc0->vbo_min_index;
171 nvc0_user_buffer_upload(buf, base, size);
172 } else {
173 nvc0_buffer_migrate(nvc0, buf, NOUVEAU_BO_GART);
174 }
175 nvc0->vbo_dirty = TRUE;
176 }
177 }
178 nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_VERTEX, buf, NOUVEAU_BO_RD);
179 nvc0_buffer_adjust_score(nvc0, buf, 1);
180 }
181 }
182
183 static void
184 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
185 {
186 struct nouveau_channel *chan = nvc0->screen->base.channel;
187 const uint32_t vertex_count = nvc0->vbo_max_index - nvc0->vbo_min_index + 1;
188 uint32_t base, offset, size;
189 int i;
190 uint32_t written = 0;
191
192 for (i = 0; i < nvc0->vertex->num_elements; ++i) {
193 struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
194 const int b = ve->vertex_buffer_index;
195 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
196 struct nvc0_resource *buf = nvc0_resource(vb->buffer);
197
198 if (!(nvc0->vbo_user & (1 << b)))
199 continue;
200
201 if (!vb->stride) {
202 nvc0_emit_vtxattr(nvc0, vb, ve, i);
203 continue;
204 }
205 size = vb->stride * vertex_count;
206 base = vb->stride * nvc0->vbo_min_index;
207
208 if (!(written & (1 << b))) {
209 written |= 1 << b;
210 nvc0_user_buffer_upload(buf, base, size);
211 }
212 offset = vb->buffer_offset + ve->src_offset;
213
214 BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
215 OUT_RING (chan, i);
216 OUT_RESRCh(chan, buf, size - 1, NOUVEAU_BO_RD);
217 OUT_RESRCl(chan, buf, size - 1, NOUVEAU_BO_RD);
218 OUT_RESRCh(chan, buf, offset, NOUVEAU_BO_RD);
219 OUT_RESRCl(chan, buf, offset, NOUVEAU_BO_RD);
220 }
221 nvc0->vbo_dirty = TRUE;
222 }
223
224 void
225 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
226 {
227 struct nouveau_channel *chan = nvc0->screen->base.channel;
228 struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
229 struct pipe_vertex_buffer *vb;
230 struct nvc0_vertex_element *ve;
231 unsigned i;
232
233 nvc0_prevalidate_vbufs(nvc0);
234
235 BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(0)), vertex->num_elements);
236 for (i = 0; i < vertex->num_elements; ++i) {
237 ve = &vertex->element[i];
238 vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
239
240 if (likely(vb->stride) || nvc0->vbo_fifo) {
241 OUT_RING(chan, ve->state);
242 } else {
243 OUT_RING(chan, ve->state | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
244 nvc0->vbo_fifo &= ~(1 << i);
245 }
246 }
247
248 for (i = 0; i < vertex->num_elements; ++i) {
249 struct nvc0_resource *res;
250 unsigned size, offset;
251
252 ve = &vertex->element[i];
253 vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
254
255 if (unlikely(ve->pipe.instance_divisor)) {
256 if (!(nvc0->state.instance_bits & (1 << i))) {
257 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
258 }
259 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
260 OUT_RING (chan, ve->pipe.instance_divisor);
261 } else
262 if (unlikely(nvc0->state.instance_bits & (1 << i))) {
263 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 0);
264 }
265
266 res = nvc0_resource(vb->buffer);
267
268 if (nvc0->vbo_fifo || unlikely(vb->stride == 0)) {
269 if (!nvc0->vbo_fifo)
270 nvc0_emit_vtxattr(nvc0, vb, &ve->pipe, i);
271 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
272 OUT_RING (chan, 0);
273 continue;
274 }
275
276 size = vb->buffer->width0;
277 offset = ve->pipe.src_offset + vb->buffer_offset;
278
279 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
280 OUT_RING (chan, (1 << 12) | vb->stride);
281 BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
282 OUT_RING (chan, i);
283 OUT_RESRCh(chan, res, size - 1, NOUVEAU_BO_RD);
284 OUT_RESRCl(chan, res, size - 1, NOUVEAU_BO_RD);
285 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
286 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
287 }
288 for (; i < nvc0->state.num_vtxelts; ++i) {
289 BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(i)), 1);
290 OUT_RING (chan, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
291 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
292 OUT_RING (chan, 0);
293 }
294
295 nvc0->state.num_vtxelts = vertex->num_elements;
296 nvc0->state.instance_bits = vertex->instance_bits;
297 }
298
299 #define NVC0_PRIM_GL_CASE(n) \
300 case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
301
302 static INLINE unsigned
303 nvc0_prim_gl(unsigned prim)
304 {
305 switch (prim) {
306 NVC0_PRIM_GL_CASE(POINTS);
307 NVC0_PRIM_GL_CASE(LINES);
308 NVC0_PRIM_GL_CASE(LINE_LOOP);
309 NVC0_PRIM_GL_CASE(LINE_STRIP);
310 NVC0_PRIM_GL_CASE(TRIANGLES);
311 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
312 NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
313 NVC0_PRIM_GL_CASE(QUADS);
314 NVC0_PRIM_GL_CASE(QUAD_STRIP);
315 NVC0_PRIM_GL_CASE(POLYGON);
316 NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
317 NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
318 NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
319 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
320 /*
321 NVC0_PRIM_GL_CASE(PATCHES); */
322 default:
323 return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
324 break;
325 }
326 }
327
328 static void
329 nvc0_draw_vbo_flush_notify(struct nouveau_channel *chan)
330 {
331 struct nvc0_context *nvc0 = chan->user_private;
332
333 nvc0_bufctx_emit_relocs(nvc0);
334 }
335
336 #if 0
337 static struct nouveau_bo *
338 nvc0_tfb_setup(struct nvc0_context *nvc0)
339 {
340 struct nouveau_channel *chan = nvc0->screen->base.channel;
341 struct nouveau_bo *tfb = NULL;
342 int ret, i;
343
344 ret = nouveau_bo_new(nvc0->screen->base.device,
345 NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, &tfb);
346 if (ret)
347 return NULL;
348
349 ret = nouveau_bo_map(tfb, NOUVEAU_BO_WR);
350 if (ret)
351 return NULL;
352 memset(tfb->map, 0xee, 8 * 4 * 3);
353 nouveau_bo_unmap(tfb);
354
355 BEGIN_RING(chan, RING_3D(TFB_ENABLE), 1);
356 OUT_RING (chan, 1);
357 BEGIN_RING(chan, RING_3D(TFB_BUFFER_ENABLE(0)), 5);
358 OUT_RING (chan, 1);
359 OUT_RELOCh(chan, tfb, 0, NOUVEAU_BO_GART | NOUVEAU_BO_WR);
360 OUT_RELOCl(chan, tfb, 0, NOUVEAU_BO_GART | NOUVEAU_BO_WR);
361 OUT_RING (chan, tfb->size);
362 OUT_RING (chan, 0); /* TFB_PRIMITIVE_ID(0) */
363 BEGIN_RING(chan, RING_3D(TFB_UNK0700(0)), 3);
364 OUT_RING (chan, 0);
365 OUT_RING (chan, 8); /* TFB_VARYING_COUNT(0) */
366 OUT_RING (chan, 32); /* TFB_BUFFER_STRIDE(0) */
367 BEGIN_RING(chan, RING_3D(TFB_VARYING_LOCS(0)), 2);
368 OUT_RING (chan, 0x1f1e1d1c);
369 OUT_RING (chan, 0xa3a2a1a0);
370 for (i = 1; i < 4; ++i) {
371 BEGIN_RING(chan, RING_3D(TFB_BUFFER_ENABLE(i)), 1);
372 OUT_RING (chan, 0);
373 }
374 BEGIN_RING(chan, RING_3D(TFB_ENABLE), 1);
375 OUT_RING (chan, 1);
376 BEGIN_RING(chan, RING_3D_(0x135c), 1);
377 OUT_RING (chan, 1);
378 BEGIN_RING(chan, RING_3D_(0x135c), 1);
379 OUT_RING (chan, 0);
380
381 return tfb;
382 }
383 #endif
384
385 static void
386 nvc0_draw_arrays(struct nvc0_context *nvc0,
387 unsigned mode, unsigned start, unsigned count,
388 unsigned instance_count)
389 {
390 struct nouveau_channel *chan = nvc0->screen->base.channel;
391 unsigned prim;
392
393 chan->flush_notify = nvc0_draw_vbo_flush_notify;
394 chan->user_private = nvc0;
395
396 prim = nvc0_prim_gl(mode);
397
398 while (instance_count--) {
399 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
400 OUT_RING (chan, prim);
401 BEGIN_RING(chan, RING_3D(VERTEX_BUFFER_FIRST), 2);
402 OUT_RING (chan, start);
403 OUT_RING (chan, count);
404 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
405
406 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
407 }
408
409 chan->flush_notify = NULL;
410 }
411
412 static void
413 nvc0_draw_elements_inline_u08(struct nouveau_channel *chan, uint8_t *map,
414 unsigned start, unsigned count)
415 {
416 map += start;
417
418 if (count & 3) {
419 unsigned i;
420 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), count & 3);
421 for (i = 0; i < (count & 3); ++i)
422 OUT_RING(chan, *map++);
423 count &= ~3;
424 }
425 while (count) {
426 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
427
428 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U8), nr);
429 for (i = 0; i < nr; ++i) {
430 OUT_RING(chan,
431 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
432 map += 4;
433 }
434 count -= nr * 4;
435 }
436 }
437
438 static void
439 nvc0_draw_elements_inline_u16(struct nouveau_channel *chan, uint16_t *map,
440 unsigned start, unsigned count)
441 {
442 map += start;
443
444 if (count & 1) {
445 count &= ~1;
446 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
447 OUT_RING (chan, *map++);
448 }
449 while (count) {
450 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
451
452 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
453 for (i = 0; i < nr; ++i) {
454 OUT_RING(chan, (map[1] << 16) | map[0]);
455 map += 2;
456 }
457 count -= nr * 2;
458 }
459 }
460
461 static void
462 nvc0_draw_elements_inline_u32(struct nouveau_channel *chan, uint32_t *map,
463 unsigned start, unsigned count)
464 {
465 map += start;
466
467 while (count) {
468 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
469
470 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), nr);
471 OUT_RINGp (chan, map, nr);
472
473 map += nr;
474 count -= nr;
475 }
476 }
477
478 static void
479 nvc0_draw_elements_inline_u32_short(struct nouveau_channel *chan, uint32_t *map,
480 unsigned start, unsigned count)
481 {
482 map += start;
483
484 if (count & 1) {
485 count--;
486 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
487 OUT_RING (chan, *map++);
488 }
489 while (count) {
490 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
491
492 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
493 for (i = 0; i < nr; ++i) {
494 OUT_RING(chan, (map[1] << 16) | map[0]);
495 map += 2;
496 }
497 count -= nr * 2;
498 }
499 }
500
501 static void
502 nvc0_draw_elements(struct nvc0_context *nvc0, boolean shorten,
503 unsigned mode, unsigned start, unsigned count,
504 unsigned instance_count, int32_t index_bias)
505 {
506 struct nouveau_channel *chan = nvc0->screen->base.channel;
507 void *data;
508 unsigned prim;
509 const unsigned index_size = nvc0->idxbuf.index_size;
510
511 chan->flush_notify = nvc0_draw_vbo_flush_notify;
512 chan->user_private = nvc0;
513
514 prim = nvc0_prim_gl(mode);
515
516 if (index_bias != nvc0->state.index_bias) {
517 BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
518 OUT_RING (chan, index_bias);
519 nvc0->state.index_bias = index_bias;
520 }
521
522 if (nvc0_resource_mapped_by_gpu(nvc0->idxbuf.buffer)) {
523 struct nvc0_resource *res = nvc0_resource(nvc0->idxbuf.buffer);
524 unsigned offset = nvc0->idxbuf.offset;
525 unsigned limit = nvc0->idxbuf.buffer->width0 - 1;
526
527 nvc0_buffer_adjust_score(nvc0, res, 1);
528
529 while (instance_count--) {
530 MARK_RING (chan, 11, 4);
531 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
532 OUT_RING (chan, mode);
533 BEGIN_RING(chan, RING_3D(INDEX_ARRAY_START_HIGH), 7);
534 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
535 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
536 OUT_RESRCh(chan, res, limit, NOUVEAU_BO_RD);
537 OUT_RESRCl(chan, res, limit, NOUVEAU_BO_RD);
538 OUT_RING (chan, index_size >> 1);
539 OUT_RING (chan, start);
540 OUT_RING (chan, count);
541 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
542
543 nvc0_resource_fence(res, NOUVEAU_BO_RD);
544
545 mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
546 }
547 } else {
548 data = nvc0_resource_map_offset(nvc0, nvc0_resource(nvc0->idxbuf.buffer),
549 nvc0->idxbuf.offset, NOUVEAU_BO_RD);
550 if (!data)
551 return;
552
553 while (instance_count--) {
554 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
555 OUT_RING (chan, prim);
556 switch (index_size) {
557 case 1:
558 nvc0_draw_elements_inline_u08(chan, data, start, count);
559 break;
560 case 2:
561 nvc0_draw_elements_inline_u16(chan, data, start, count);
562 break;
563 case 4:
564 if (shorten)
565 nvc0_draw_elements_inline_u32_short(chan, data, start, count);
566 else
567 nvc0_draw_elements_inline_u32(chan, data, start, count);
568 break;
569 default:
570 assert(0);
571 return;
572 }
573 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
574
575 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
576 }
577 }
578
579 chan->flush_notify = NULL;
580 }
581
582 void
583 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
584 {
585 struct nvc0_context *nvc0 = nvc0_context(pipe);
586 struct nouveau_channel *chan = nvc0->screen->base.channel;
587
588 /* For picking only a few vertices from a large user buffer, push is better,
589 * if index count is larger and we expect repeated vertices, suggest upload.
590 */
591 nvc0->vbo_push_hint = /* the 64 is heuristic */
592 !(info->indexed &&
593 ((info->max_index - info->min_index + 64) < info->count));
594
595 nvc0->vbo_min_index = info->min_index;
596 nvc0->vbo_max_index = info->max_index;
597
598 if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS)))
599 nvc0_update_user_vbufs(nvc0);
600
601 nvc0_state_validate(nvc0);
602
603 if (nvc0->state.instance_base != info->start_instance) {
604 nvc0->state.instance_base = info->start_instance;
605 BEGIN_RING(chan, RING_3D(VB_INSTANCE_BASE), 1);
606 OUT_RING (chan, info->start_instance);
607 }
608
609 if (nvc0->vbo_fifo) {
610 nvc0_push_vbo(nvc0, info);
611 return;
612 }
613
614 if (nvc0->vbo_dirty) {
615 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 1);
616 OUT_RING (chan, 0);
617 nvc0->vbo_dirty = FALSE;
618 }
619
620 if (!info->indexed) {
621 nvc0_draw_arrays(nvc0,
622 info->mode, info->start, info->count,
623 info->instance_count);
624 } else {
625 boolean shorten = info->max_index <= 65535;
626
627 assert(nvc0->idxbuf.buffer);
628
629 if (info->primitive_restart != nvc0->state.prim_restart) {
630 if (info->primitive_restart) {
631 BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 2);
632 OUT_RING (chan, 1);
633 OUT_RING (chan, info->restart_index);
634
635 if (info->restart_index > 65535)
636 shorten = FALSE;
637 } else {
638 IMMED_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 0);
639 }
640 nvc0->state.prim_restart = info->primitive_restart;
641 } else
642 if (info->primitive_restart) {
643 BEGIN_RING(chan, RING_3D(PRIM_RESTART_INDEX), 1);
644 OUT_RING (chan, info->restart_index);
645
646 if (info->restart_index > 65535)
647 shorten = FALSE;
648 }
649
650 nvc0_draw_elements(nvc0, shorten,
651 info->mode, info->start, info->count,
652 info->instance_count, info->index_bias);
653 }
654 }