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de456b91945273e6fce7c813aeadfbd5e0c76193
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_vbo.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
27 #include "translate/translate.h"
28
29 #include "nvc0_context.h"
30 #include "nvc0_resource.h"
31
32 #include "nvc0_3d.xml.h"
33
34 void
35 nvc0_vertex_state_delete(struct pipe_context *pipe,
36 void *hwcso)
37 {
38 struct nvc0_vertex_stateobj *so = hwcso;
39
40 if (so->translate)
41 so->translate->release(so->translate);
42 FREE(hwcso);
43 }
44
45 void *
46 nvc0_vertex_state_create(struct pipe_context *pipe,
47 unsigned num_elements,
48 const struct pipe_vertex_element *elements)
49 {
50 struct nvc0_vertex_stateobj *so;
51 struct translate_key transkey;
52 unsigned i;
53
54 so = MALLOC(sizeof(*so) +
55 num_elements * sizeof(struct nvc0_vertex_element));
56 if (!so)
57 return NULL;
58 so->num_elements = num_elements;
59 so->instance_elts = 0;
60 so->instance_bufs = 0;
61 so->need_conversion = FALSE;
62
63 transkey.nr_elements = 0;
64 transkey.output_stride = 0;
65
66 for (i = 0; i < num_elements; ++i) {
67 const struct pipe_vertex_element *ve = &elements[i];
68 const unsigned vbi = ve->vertex_buffer_index;
69 enum pipe_format fmt = ve->src_format;
70
71 so->element[i].pipe = elements[i];
72 so->element[i].state = nvc0_format_table[fmt].vtx;
73
74 if (!so->element[i].state) {
75 switch (util_format_get_nr_components(fmt)) {
76 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
77 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
78 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
79 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
80 default:
81 assert(0);
82 return NULL;
83 }
84 so->element[i].state = nvc0_format_table[fmt].vtx;
85 so->need_conversion = TRUE;
86 }
87 so->element[i].state |= i;
88
89 if (1) {
90 unsigned j = transkey.nr_elements++;
91
92 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
93 transkey.element[j].input_format = ve->src_format;
94 transkey.element[j].input_buffer = vbi;
95 transkey.element[j].input_offset = ve->src_offset;
96 transkey.element[j].instance_divisor = ve->instance_divisor;
97
98 transkey.element[j].output_format = fmt;
99 transkey.element[j].output_offset = transkey.output_stride;
100 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
101
102 if (unlikely(ve->instance_divisor)) {
103 so->instance_elts |= 1 << i;
104 so->instance_bufs |= 1 << vbi;
105 }
106 }
107 }
108
109 so->translate = translate_create(&transkey);
110 so->vtx_size = transkey.output_stride / 4;
111 so->vtx_per_packet_max = NV04_PFIFO_MAX_PACKET_LEN / MAX2(so->vtx_size, 1);
112
113 return so;
114 }
115
116 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE \
117 NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT | \
118 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
119
120 #define VTX_ATTR(a, c, t, s) \
121 ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) | \
122 (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) | \
123 ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) | \
124 ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
125
126 static void
127 nvc0_emit_vtxattr(struct nvc0_context *nvc0, struct pipe_vertex_buffer *vb,
128 struct pipe_vertex_element *ve, unsigned attr)
129 {
130 const void *data;
131 struct nouveau_channel *chan = nvc0->screen->base.channel;
132 struct nv04_resource *res = nv04_resource(vb->buffer);
133 float v[4];
134 int i;
135 const unsigned nc = util_format_get_nr_components(ve->src_format);
136
137 data = nouveau_resource_map_offset(&nvc0->base, res, vb->buffer_offset +
138 ve->src_offset, NOUVEAU_BO_RD);
139
140 util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
141
142 BEGIN_RING(chan, RING_3D(VTX_ATTR_DEFINE), nc + 1);
143 OUT_RING (chan, VTX_ATTR(attr, nc, FLOAT, 32));
144 for (i = 0; i < nc; ++i)
145 OUT_RINGf(chan, v[i]);
146 }
147
148 static INLINE void
149 nvc0_vbuf_range(struct nvc0_context *nvc0, int vbi,
150 uint32_t *base, uint32_t *size)
151 {
152 if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
153 /* TODO: use min and max instance divisor to get a proper range */
154 *base = 0;
155 *size = nvc0->vtxbuf[vbi].buffer->width0;
156 } else {
157 assert(nvc0->vbo_max_index != ~0);
158 *base = nvc0->vbo_min_index * nvc0->vtxbuf[vbi].stride;
159 *size = (nvc0->vbo_max_index -
160 nvc0->vbo_min_index + 1) * nvc0->vtxbuf[vbi].stride;
161 }
162 }
163
164 static void
165 nvc0_prevalidate_vbufs(struct nvc0_context *nvc0)
166 {
167 struct pipe_vertex_buffer *vb;
168 struct nv04_resource *buf;
169 int i;
170 uint32_t base, size;
171
172 nvc0->vbo_fifo = nvc0->vbo_user = 0;
173
174 nvc0_bufctx_reset(nvc0, NVC0_BUFCTX_VERTEX);
175
176 for (i = 0; i < nvc0->num_vtxbufs; ++i) {
177 vb = &nvc0->vtxbuf[i];
178 if (!vb->stride)
179 continue;
180 buf = nv04_resource(vb->buffer);
181
182 /* NOTE: user buffers with temporary storage count as mapped by GPU */
183 if (!nouveau_resource_mapped_by_gpu(vb->buffer)) {
184 if (nvc0->vbo_push_hint) {
185 nvc0->vbo_fifo = ~0;
186 continue;
187 } else {
188 if (buf->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY) {
189 nvc0->vbo_user |= 1 << i;
190 assert(vb->stride > vb->buffer_offset);
191 nvc0_vbuf_range(nvc0, i, &base, &size);
192 nouveau_user_buffer_upload(buf, base, size);
193 } else {
194 nouveau_buffer_migrate(&nvc0->base, buf, NOUVEAU_BO_GART);
195 }
196 nvc0->base.vbo_dirty = TRUE;
197 }
198 }
199 nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_VERTEX, buf, NOUVEAU_BO_RD);
200 }
201 }
202
203 static void
204 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
205 {
206 struct nouveau_channel *chan = nvc0->screen->base.channel;
207 uint32_t base, offset, size;
208 int i;
209 uint32_t written = 0;
210
211 for (i = 0; i < nvc0->vertex->num_elements; ++i) {
212 struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
213 const int b = ve->vertex_buffer_index;
214 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
215 struct nv04_resource *buf = nv04_resource(vb->buffer);
216
217 if (!(nvc0->vbo_user & (1 << b)))
218 continue;
219
220 if (!vb->stride) {
221 nvc0_emit_vtxattr(nvc0, vb, ve, i);
222 continue;
223 }
224 nvc0_vbuf_range(nvc0, b, &base, &size);
225
226 if (!(written & (1 << b))) {
227 written |= 1 << b;
228 nouveau_user_buffer_upload(buf, base, size);
229 }
230 offset = vb->buffer_offset + ve->src_offset;
231
232 MARK_RING (chan, 6, 4);
233 BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
234 OUT_RING (chan, i);
235 OUT_RESRCh(chan, buf, base + size - 1, NOUVEAU_BO_RD);
236 OUT_RESRCl(chan, buf, base + size - 1, NOUVEAU_BO_RD);
237 OUT_RESRCh(chan, buf, offset, NOUVEAU_BO_RD);
238 OUT_RESRCl(chan, buf, offset, NOUVEAU_BO_RD);
239 }
240 nvc0->base.vbo_dirty = TRUE;
241 }
242
243 static INLINE void
244 nvc0_release_user_vbufs(struct nvc0_context *nvc0)
245 {
246 uint32_t vbo_user = nvc0->vbo_user;
247
248 while (vbo_user) {
249 int i = ffs(vbo_user) - 1;
250 vbo_user &= ~(1 << i);
251
252 nouveau_buffer_release_gpu_storage(nv04_resource(nvc0->vtxbuf[i].buffer));
253 }
254 }
255
256 void
257 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
258 {
259 struct nouveau_channel *chan = nvc0->screen->base.channel;
260 struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
261 struct pipe_vertex_buffer *vb;
262 struct nvc0_vertex_element *ve;
263 unsigned i;
264
265 if (unlikely(vertex->need_conversion) ||
266 unlikely(nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS)) {
267 nvc0->vbo_fifo = ~0;
268 nvc0->vbo_user = 0;
269 } else {
270 nvc0_prevalidate_vbufs(nvc0);
271 }
272
273 BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(0)), vertex->num_elements);
274 for (i = 0; i < vertex->num_elements; ++i) {
275 ve = &vertex->element[i];
276 vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
277
278 if (likely(vb->stride) || nvc0->vbo_fifo) {
279 OUT_RING(chan, ve->state);
280 } else {
281 OUT_RING(chan, ve->state | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
282 nvc0->vbo_fifo &= ~(1 << i);
283 }
284 }
285
286 for (i = 0; i < vertex->num_elements; ++i) {
287 struct nv04_resource *res;
288 unsigned size, offset;
289
290 ve = &vertex->element[i];
291 vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
292
293 if (unlikely(ve->pipe.instance_divisor)) {
294 if (!(nvc0->state.instance_elts & (1 << i))) {
295 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
296 }
297 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
298 OUT_RING (chan, ve->pipe.instance_divisor);
299 } else
300 if (unlikely(nvc0->state.instance_elts & (1 << i))) {
301 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 0);
302 }
303
304 res = nv04_resource(vb->buffer);
305
306 if (nvc0->vbo_fifo || unlikely(vb->stride == 0)) {
307 if (!nvc0->vbo_fifo)
308 nvc0_emit_vtxattr(nvc0, vb, &ve->pipe, i);
309 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
310 OUT_RING (chan, 0);
311 continue;
312 }
313
314 size = vb->buffer->width0;
315 offset = ve->pipe.src_offset + vb->buffer_offset;
316
317 MARK_RING (chan, 8, 4);
318 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
319 OUT_RING (chan, (1 << 12) | vb->stride);
320 BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
321 OUT_RING (chan, i);
322 OUT_RESRCh(chan, res, size - 1, NOUVEAU_BO_RD);
323 OUT_RESRCl(chan, res, size - 1, NOUVEAU_BO_RD);
324 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
325 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
326 }
327 for (; i < nvc0->state.num_vtxelts; ++i) {
328 BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(i)), 1);
329 OUT_RING (chan, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
330 if (unlikely(nvc0->state.instance_elts & (1 << i)))
331 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 0);
332 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
333 OUT_RING (chan, 0);
334 }
335
336 nvc0->state.num_vtxelts = vertex->num_elements;
337 nvc0->state.instance_elts = vertex->instance_elts;
338 }
339
340 #define NVC0_PRIM_GL_CASE(n) \
341 case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
342
343 static INLINE unsigned
344 nvc0_prim_gl(unsigned prim)
345 {
346 switch (prim) {
347 NVC0_PRIM_GL_CASE(POINTS);
348 NVC0_PRIM_GL_CASE(LINES);
349 NVC0_PRIM_GL_CASE(LINE_LOOP);
350 NVC0_PRIM_GL_CASE(LINE_STRIP);
351 NVC0_PRIM_GL_CASE(TRIANGLES);
352 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
353 NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
354 NVC0_PRIM_GL_CASE(QUADS);
355 NVC0_PRIM_GL_CASE(QUAD_STRIP);
356 NVC0_PRIM_GL_CASE(POLYGON);
357 NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
358 NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
359 NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
360 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
361 /*
362 NVC0_PRIM_GL_CASE(PATCHES); */
363 default:
364 return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
365 break;
366 }
367 }
368
369 static void
370 nvc0_draw_vbo_flush_notify(struct nouveau_channel *chan)
371 {
372 struct nvc0_screen *screen = chan->user_private;
373
374 nouveau_fence_update(&screen->base, TRUE);
375
376 nvc0_bufctx_emit_relocs(screen->cur_ctx);
377 }
378
379 static void
380 nvc0_draw_arrays(struct nvc0_context *nvc0,
381 unsigned mode, unsigned start, unsigned count,
382 unsigned instance_count)
383 {
384 struct nouveau_channel *chan = nvc0->screen->base.channel;
385 unsigned prim;
386
387 if (nvc0->state.index_bias) {
388 IMMED_RING(chan, RING_3D(VB_ELEMENT_BASE), 0);
389 nvc0->state.index_bias = 0;
390 }
391
392 prim = nvc0_prim_gl(mode);
393
394 while (instance_count--) {
395 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
396 OUT_RING (chan, prim);
397 BEGIN_RING(chan, RING_3D(VERTEX_BUFFER_FIRST), 2);
398 OUT_RING (chan, start);
399 OUT_RING (chan, count);
400 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
401
402 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
403 }
404 }
405
406 static void
407 nvc0_draw_elements_inline_u08(struct nouveau_channel *chan, uint8_t *map,
408 unsigned start, unsigned count)
409 {
410 map += start;
411
412 if (count & 3) {
413 unsigned i;
414 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), count & 3);
415 for (i = 0; i < (count & 3); ++i)
416 OUT_RING(chan, *map++);
417 count &= ~3;
418 }
419 while (count) {
420 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
421
422 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U8), nr);
423 for (i = 0; i < nr; ++i) {
424 OUT_RING(chan,
425 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
426 map += 4;
427 }
428 count -= nr * 4;
429 }
430 }
431
432 static void
433 nvc0_draw_elements_inline_u16(struct nouveau_channel *chan, uint16_t *map,
434 unsigned start, unsigned count)
435 {
436 map += start;
437
438 if (count & 1) {
439 count &= ~1;
440 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
441 OUT_RING (chan, *map++);
442 }
443 while (count) {
444 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
445
446 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
447 for (i = 0; i < nr; ++i) {
448 OUT_RING(chan, (map[1] << 16) | map[0]);
449 map += 2;
450 }
451 count -= nr * 2;
452 }
453 }
454
455 static void
456 nvc0_draw_elements_inline_u32(struct nouveau_channel *chan, uint32_t *map,
457 unsigned start, unsigned count)
458 {
459 map += start;
460
461 while (count) {
462 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
463
464 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), nr);
465 OUT_RINGp (chan, map, nr);
466
467 map += nr;
468 count -= nr;
469 }
470 }
471
472 static void
473 nvc0_draw_elements_inline_u32_short(struct nouveau_channel *chan, uint32_t *map,
474 unsigned start, unsigned count)
475 {
476 map += start;
477
478 if (count & 1) {
479 count--;
480 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
481 OUT_RING (chan, *map++);
482 }
483 while (count) {
484 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
485
486 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
487 for (i = 0; i < nr; ++i) {
488 OUT_RING(chan, (map[1] << 16) | map[0]);
489 map += 2;
490 }
491 count -= nr * 2;
492 }
493 }
494
495 static void
496 nvc0_draw_elements(struct nvc0_context *nvc0, boolean shorten,
497 unsigned mode, unsigned start, unsigned count,
498 unsigned instance_count, int32_t index_bias)
499 {
500 struct nouveau_channel *chan = nvc0->screen->base.channel;
501 void *data;
502 unsigned prim;
503 const unsigned index_size = nvc0->idxbuf.index_size;
504
505 prim = nvc0_prim_gl(mode);
506
507 if (index_bias != nvc0->state.index_bias) {
508 BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
509 OUT_RING (chan, index_bias);
510 nvc0->state.index_bias = index_bias;
511 }
512
513 if (nouveau_resource_mapped_by_gpu(nvc0->idxbuf.buffer)) {
514 struct nv04_resource *res = nv04_resource(nvc0->idxbuf.buffer);
515 unsigned offset = nvc0->idxbuf.offset;
516 unsigned limit = nvc0->idxbuf.buffer->width0 - 1;
517
518 while (instance_count--) {
519 MARK_RING (chan, 11, 4);
520 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
521 OUT_RING (chan, mode);
522 BEGIN_RING(chan, RING_3D(INDEX_ARRAY_START_HIGH), 7);
523 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
524 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
525 OUT_RESRCh(chan, res, limit, NOUVEAU_BO_RD);
526 OUT_RESRCl(chan, res, limit, NOUVEAU_BO_RD);
527 OUT_RING (chan, index_size >> 1);
528 OUT_RING (chan, start);
529 OUT_RING (chan, count);
530 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
531
532 nvc0_resource_fence(res, NOUVEAU_BO_RD);
533
534 mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
535 }
536 } else {
537 data = nouveau_resource_map_offset(&nvc0->base,
538 nv04_resource(nvc0->idxbuf.buffer),
539 nvc0->idxbuf.offset, NOUVEAU_BO_RD);
540 if (!data)
541 return;
542
543 while (instance_count--) {
544 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
545 OUT_RING (chan, prim);
546 switch (index_size) {
547 case 1:
548 nvc0_draw_elements_inline_u08(chan, data, start, count);
549 break;
550 case 2:
551 nvc0_draw_elements_inline_u16(chan, data, start, count);
552 break;
553 case 4:
554 if (shorten)
555 nvc0_draw_elements_inline_u32_short(chan, data, start, count);
556 else
557 nvc0_draw_elements_inline_u32(chan, data, start, count);
558 break;
559 default:
560 assert(0);
561 return;
562 }
563 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
564
565 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
566 }
567 }
568 }
569
570 static void
571 nvc0_draw_stream_output(struct nvc0_context *nvc0,
572 const struct pipe_draw_info *info)
573 {
574 struct nouveau_channel *chan = nvc0->screen->base.channel;
575 struct nvc0_so_target *so = nvc0_so_target(info->count_from_stream_output);
576 struct nv04_resource *res = nv04_resource(so->pipe.buffer);
577 unsigned mode = nvc0_prim_gl(info->mode);
578 unsigned num_instances = info->instance_count;
579
580 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
581 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
582 IMMED_RING(chan, RING_3D(SERIALIZE), 0);
583 nvc0_query_fifo_wait(chan, so->pq);
584 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 0);
585 }
586
587 while (num_instances--) {
588 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
589 OUT_RING (chan, mode);
590 BEGIN_RING(chan, RING_3D(DRAW_TFB_BASE), 1);
591 OUT_RING (chan, 0);
592 BEGIN_RING(chan, RING_3D(DRAW_TFB_STRIDE), 1);
593 OUT_RING (chan, so->stride);
594 BEGIN_RING(chan, RING_3D(DRAW_TFB_BYTES), 1);
595 nvc0_query_pushbuf_submit(chan, so->pq, 0x4);
596 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
597
598 mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
599 }
600 }
601
602 void
603 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
604 {
605 struct nvc0_context *nvc0 = nvc0_context(pipe);
606 struct nouveau_channel *chan = nvc0->screen->base.channel;
607
608 /* For picking only a few vertices from a large user buffer, push is better,
609 * if index count is larger and we expect repeated vertices, suggest upload.
610 */
611 nvc0->vbo_push_hint = /* the 64 is heuristic */
612 !(info->indexed &&
613 ((info->max_index - info->min_index + 64) < info->count));
614
615 nvc0->vbo_min_index = info->min_index;
616 nvc0->vbo_max_index = info->max_index;
617
618 if (nvc0->vbo_push_hint != !!nvc0->vbo_fifo)
619 nvc0->dirty |= NVC0_NEW_ARRAYS;
620
621 if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS)))
622 nvc0_update_user_vbufs(nvc0);
623
624 /* 8 as minimum to avoid immediate double validation of new buffers */
625 nvc0_state_validate(nvc0, ~0, 8);
626
627 chan->flush_notify = nvc0_draw_vbo_flush_notify;
628
629 if (nvc0->vbo_fifo) {
630 nvc0_push_vbo(nvc0, info);
631 chan->flush_notify = nvc0_default_flush_notify;
632 return;
633 }
634
635 if (nvc0->state.instance_base != info->start_instance) {
636 nvc0->state.instance_base = info->start_instance;
637 /* NOTE: this does not affect the shader input, should it ? */
638 BEGIN_RING(chan, RING_3D(VB_INSTANCE_BASE), 1);
639 OUT_RING (chan, info->start_instance);
640 }
641
642 if (nvc0->base.vbo_dirty) {
643 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 1);
644 OUT_RING (chan, 0);
645 nvc0->base.vbo_dirty = FALSE;
646 }
647
648 if (unlikely(info->count_from_stream_output)) {
649 nvc0_draw_stream_output(nvc0, info);
650 } else
651 if (!info->indexed) {
652 nvc0_draw_arrays(nvc0,
653 info->mode, info->start, info->count,
654 info->instance_count);
655 } else {
656 boolean shorten = info->max_index <= 65535;
657
658 assert(nvc0->idxbuf.buffer);
659
660 if (info->primitive_restart != nvc0->state.prim_restart) {
661 if (info->primitive_restart) {
662 BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 2);
663 OUT_RING (chan, 1);
664 OUT_RING (chan, info->restart_index);
665
666 if (info->restart_index > 65535)
667 shorten = FALSE;
668 } else {
669 IMMED_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 0);
670 }
671 nvc0->state.prim_restart = info->primitive_restart;
672 } else
673 if (info->primitive_restart) {
674 BEGIN_RING(chan, RING_3D(PRIM_RESTART_INDEX), 1);
675 OUT_RING (chan, info->restart_index);
676
677 if (info->restart_index > 65535)
678 shorten = FALSE;
679 }
680
681 nvc0_draw_elements(nvc0, shorten,
682 info->mode, info->start, info->count,
683 info->instance_count, info->index_bias);
684 }
685 chan->flush_notify = nvc0_default_flush_notify;
686
687 nvc0_release_user_vbufs(nvc0);
688 }